- Timestamp:
- Jan 8, 2024 9:48:55 PM (13 months ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 3 edited
-
bs3-cpu-weird-1-template.mac (modified) (1 diff)
-
bs3-cpu-weird-1-x0.c (modified) (6 diffs)
-
bs3-cpu-weird-1.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-weird-1-template.mac
r102779 r102789 225 225 ; 226 226 227 BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_fs_Ud2, BS3_PBC_NEAR 228 push fs 229 .ud2_again: 230 ud2 231 jmp .ud2_again 232 AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_fs_Ud2) == 2) 233 BS3_PROC_END_CMN bs3CpuWeird1_Push_fs_Ud2 234 235 236 BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_fs_Ud2, BS3_PBC_NEAR 237 pop fs 238 .ud2_again: 239 ud2 240 jmp .ud2_again 241 AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_fs_Ud2) == 2) 242 BS3_PROC_END_CMN bs3CpuWeird1_Pop_fs_Ud2 243 244 245 BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_fs_Ud2, BS3_PBC_NEAR 246 db 066h 247 push fs 248 .ud2_again: 249 ud2 250 jmp .ud2_again 251 AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_fs_Ud2) == 3) 252 BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_fs_Ud2 253 254 255 BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_fs_Ud2, BS3_PBC_NEAR 256 db 066h 257 pop fs 258 .ud2_again: 259 ud2 260 jmp .ud2_again 261 AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_fs_Ud2) == 3) 262 BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_fs_Ud2 263 227 %ifndef DEFINED_DO_PUSH_POP_MACROS 228 %define DEFINED_DO_PUSH_POP_MACROS 229 %macro DoPushSeg 2 230 231 BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_ %+ %1 %+ _Ud2, BS3_PBC_NEAR 232 push %1 233 .ud2_again: 234 ud2 235 jmp .ud2_again 236 AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_ %+ %1 %+ _Ud2) == %2) 237 BS3_PROC_END_CMN bs3CpuWeird1_Push_ %+ %1 %+ _Ud2 238 239 BS3_PROC_BEGIN_CMN bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2, BS3_PBC_NEAR 240 db 066h 241 push %1 242 .ud2_again: 243 ud2 244 jmp .ud2_again 245 AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2) == (%2 + 1)) 246 BS3_PROC_END_CMN bs3CpuWeird1_Push_opsize_ %+ %1 %+ _Ud2 247 248 %endmacro ; DoPushSeg 249 250 %macro DoPopSeg 2 251 252 BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2, BS3_PBC_NEAR 253 pop %1 254 .ud2_again: 255 ud2 256 jmp .ud2_again 257 AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2) == %2) 258 BS3_PROC_END_CMN bs3CpuWeird1_Pop_ %+ %1 %+ _Ud2 259 260 BS3_PROC_BEGIN_CMN bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2, BS3_PBC_NEAR 261 db 066h 262 pop %1 263 .ud2_again: 264 ud2 265 jmp .ud2_again 266 AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2) == (%2 + 1)) 267 BS3_PROC_END_CMN bs3CpuWeird1_Pop_opsize_ %+ %1 %+ _Ud2 268 269 %endmacro ; DoPopSeg 270 %endif ; !DEFINED_DO_PUSH_POP_MACROS 271 272 DoPushSeg fs, 2 273 DoPopSeg fs, 2 274 DoPushSeg gs, 2 275 DoPopSeg gs, 2 276 %if TMPL_BITS == 32 || TMPL_BITS == 16 277 DoPushSeg es, 1 278 DoPopSeg es, 1 279 DoPushSeg ds, 1 280 DoPopSeg ds, 1 281 DoPushSeg ss, 1 282 DoPopSeg ss, 1 283 DoPushSeg cs, 1 284 %endif 264 285 265 286 %endif ; BS3_INSTANTIATING_CMN -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-weird-1-x0.c
r102780 r102789 1390 1390 a_Template ## _c32, \ 1391 1391 a_Template ## _c64 1392 PROTO_ALL(bs3CpuWeird1_Push_cs_Ud2); 1393 PROTO_ALL(bs3CpuWeird1_Push_ss_Ud2); 1394 PROTO_ALL(bs3CpuWeird1_Push_ds_Ud2); 1395 PROTO_ALL(bs3CpuWeird1_Push_es_Ud2); 1392 1396 PROTO_ALL(bs3CpuWeird1_Push_fs_Ud2); 1397 PROTO_ALL(bs3CpuWeird1_Push_gs_Ud2); 1398 PROTO_ALL(bs3CpuWeird1_Pop_ss_Ud2); 1399 PROTO_ALL(bs3CpuWeird1_Pop_ds_Ud2); 1400 PROTO_ALL(bs3CpuWeird1_Pop_es_Ud2); 1393 1401 PROTO_ALL(bs3CpuWeird1_Pop_fs_Ud2); 1402 PROTO_ALL(bs3CpuWeird1_Pop_gs_Ud2); 1403 PROTO_ALL(bs3CpuWeird1_Push_opsize_cs_Ud2); 1404 PROTO_ALL(bs3CpuWeird1_Push_opsize_ss_Ud2); 1405 PROTO_ALL(bs3CpuWeird1_Push_opsize_ds_Ud2); 1406 PROTO_ALL(bs3CpuWeird1_Push_opsize_es_Ud2); 1394 1407 PROTO_ALL(bs3CpuWeird1_Push_opsize_fs_Ud2); 1408 PROTO_ALL(bs3CpuWeird1_Push_opsize_gs_Ud2); 1409 PROTO_ALL(bs3CpuWeird1_Pop_opsize_ss_Ud2); 1410 PROTO_ALL(bs3CpuWeird1_Pop_opsize_ds_Ud2); 1411 PROTO_ALL(bs3CpuWeird1_Pop_opsize_es_Ud2); 1395 1412 PROTO_ALL(bs3CpuWeird1_Pop_opsize_fs_Ud2); 1413 PROTO_ALL(bs3CpuWeird1_Pop_opsize_gs_Ud2); 1396 1414 #undef PROTO_ALL 1397 1415 … … 1409 1427 } s_aTests[] = 1410 1428 { 1429 { bs3CpuWeird1_Push_cs_Ud2_c16, 16, true, -2, RT_UOFFSETOF(BS3REGCTX, cs), 1 }, 1430 { bs3CpuWeird1_Push_ss_Ud2_c16, 16, true, -2, RT_UOFFSETOF(BS3REGCTX, ss), 1 }, 1431 { bs3CpuWeird1_Push_ds_Ud2_c16, 16, true, -2, RT_UOFFSETOF(BS3REGCTX, ds), 1 }, 1432 { bs3CpuWeird1_Push_es_Ud2_c16, 16, true, -2, RT_UOFFSETOF(BS3REGCTX, es), 1 }, 1411 1433 { bs3CpuWeird1_Push_fs_Ud2_c16, 16, true, -2, RT_UOFFSETOF(BS3REGCTX, fs), 2 }, 1434 { bs3CpuWeird1_Push_gs_Ud2_c16, 16, true, -2, RT_UOFFSETOF(BS3REGCTX, gs), 2 }, 1435 { bs3CpuWeird1_Pop_ss_Ud2_c16, 16, false, +2, RT_UOFFSETOF(BS3REGCTX, ss), 1 }, 1436 { bs3CpuWeird1_Pop_ds_Ud2_c16, 16, false, +2, RT_UOFFSETOF(BS3REGCTX, ds), 1 }, 1437 { bs3CpuWeird1_Pop_es_Ud2_c16, 16, false, +2, RT_UOFFSETOF(BS3REGCTX, es), 1 }, 1412 1438 { bs3CpuWeird1_Pop_fs_Ud2_c16, 16, false, +2, RT_UOFFSETOF(BS3REGCTX, fs), 2 }, 1439 { bs3CpuWeird1_Pop_gs_Ud2_c16, 16, false, +2, RT_UOFFSETOF(BS3REGCTX, gs), 2 }, 1440 { bs3CpuWeird1_Push_opsize_cs_Ud2_c16, 16, true, -4, RT_UOFFSETOF(BS3REGCTX, cs), 2 }, 1441 { bs3CpuWeird1_Push_opsize_ss_Ud2_c16, 16, true, -4, RT_UOFFSETOF(BS3REGCTX, ss), 2 }, 1442 { bs3CpuWeird1_Push_opsize_ds_Ud2_c16, 16, true, -4, RT_UOFFSETOF(BS3REGCTX, ds), 2 }, 1443 { bs3CpuWeird1_Push_opsize_es_Ud2_c16, 16, true, -4, RT_UOFFSETOF(BS3REGCTX, es), 2 }, 1413 1444 { bs3CpuWeird1_Push_opsize_fs_Ud2_c16, 16, true, -4, RT_UOFFSETOF(BS3REGCTX, fs), 3 }, 1445 { bs3CpuWeird1_Push_opsize_gs_Ud2_c16, 16, true, -4, RT_UOFFSETOF(BS3REGCTX, gs), 3 }, 1446 { bs3CpuWeird1_Pop_opsize_ss_Ud2_c16, 16, false, +4, RT_UOFFSETOF(BS3REGCTX, ss), 2 }, 1447 { bs3CpuWeird1_Pop_opsize_ds_Ud2_c16, 16, false, +4, RT_UOFFSETOF(BS3REGCTX, ds), 2 }, 1448 { bs3CpuWeird1_Pop_opsize_es_Ud2_c16, 16, false, +4, RT_UOFFSETOF(BS3REGCTX, es), 2 }, 1414 1449 { bs3CpuWeird1_Pop_opsize_fs_Ud2_c16, 16, false, +4, RT_UOFFSETOF(BS3REGCTX, fs), 3 }, 1415 1450 { bs3CpuWeird1_Pop_opsize_gs_Ud2_c16, 16, false, +4, RT_UOFFSETOF(BS3REGCTX, gs), 3 }, 1451 1452 { bs3CpuWeird1_Push_cs_Ud2_c32, 32, true, -4, RT_UOFFSETOF(BS3REGCTX, cs), 1 }, 1453 { bs3CpuWeird1_Push_ss_Ud2_c32, 32, true, -4, RT_UOFFSETOF(BS3REGCTX, ss), 1 }, 1454 { bs3CpuWeird1_Push_ds_Ud2_c32, 32, true, -4, RT_UOFFSETOF(BS3REGCTX, ds), 1 }, 1455 { bs3CpuWeird1_Push_es_Ud2_c32, 32, true, -4, RT_UOFFSETOF(BS3REGCTX, es), 1 }, 1416 1456 { bs3CpuWeird1_Push_fs_Ud2_c32, 32, true, -4, RT_UOFFSETOF(BS3REGCTX, fs), 2 }, 1457 { bs3CpuWeird1_Push_gs_Ud2_c32, 32, true, -4, RT_UOFFSETOF(BS3REGCTX, gs), 2 }, 1458 { bs3CpuWeird1_Pop_ss_Ud2_c32, 32, false, +4, RT_UOFFSETOF(BS3REGCTX, ss), 1 }, 1459 { bs3CpuWeird1_Pop_ds_Ud2_c32, 32, false, +4, RT_UOFFSETOF(BS3REGCTX, ds), 1 }, 1460 { bs3CpuWeird1_Pop_es_Ud2_c32, 32, false, +4, RT_UOFFSETOF(BS3REGCTX, es), 1 }, 1417 1461 { bs3CpuWeird1_Pop_fs_Ud2_c32, 32, false, +4, RT_UOFFSETOF(BS3REGCTX, fs), 2 }, 1462 { bs3CpuWeird1_Pop_gs_Ud2_c32, 32, false, +4, RT_UOFFSETOF(BS3REGCTX, gs), 2 }, 1463 { bs3CpuWeird1_Push_opsize_cs_Ud2_c32, 32, true, -2, RT_UOFFSETOF(BS3REGCTX, cs), 2 }, 1464 { bs3CpuWeird1_Push_opsize_ss_Ud2_c32, 32, true, -2, RT_UOFFSETOF(BS3REGCTX, ss), 2 }, 1465 { bs3CpuWeird1_Push_opsize_ds_Ud2_c32, 32, true, -2, RT_UOFFSETOF(BS3REGCTX, ds), 2 }, 1466 { bs3CpuWeird1_Push_opsize_es_Ud2_c32, 32, true, -2, RT_UOFFSETOF(BS3REGCTX, es), 2 }, 1418 1467 { bs3CpuWeird1_Push_opsize_fs_Ud2_c32, 32, true, -2, RT_UOFFSETOF(BS3REGCTX, fs), 3 }, 1468 { bs3CpuWeird1_Push_opsize_gs_Ud2_c32, 32, true, -2, RT_UOFFSETOF(BS3REGCTX, gs), 3 }, 1469 { bs3CpuWeird1_Pop_opsize_ss_Ud2_c32, 32, false, +2, RT_UOFFSETOF(BS3REGCTX, ss), 2 }, 1470 { bs3CpuWeird1_Pop_opsize_ds_Ud2_c32, 32, false, +2, RT_UOFFSETOF(BS3REGCTX, ds), 2 }, 1471 { bs3CpuWeird1_Pop_opsize_es_Ud2_c32, 32, false, +2, RT_UOFFSETOF(BS3REGCTX, es), 2 }, 1419 1472 { bs3CpuWeird1_Pop_opsize_fs_Ud2_c32, 32, false, +2, RT_UOFFSETOF(BS3REGCTX, fs), 3 }, 1473 { bs3CpuWeird1_Pop_opsize_gs_Ud2_c32, 32, false, +2, RT_UOFFSETOF(BS3REGCTX, gs), 3 }, 1420 1474 1421 1475 { bs3CpuWeird1_Push_fs_Ud2_c64, 64, true, -8, RT_UOFFSETOF(BS3REGCTX, fs), 2 }, 1476 { bs3CpuWeird1_Push_gs_Ud2_c64, 64, true, -8, RT_UOFFSETOF(BS3REGCTX, gs), 2 }, 1422 1477 { bs3CpuWeird1_Pop_fs_Ud2_c64, 64, false, +8, RT_UOFFSETOF(BS3REGCTX, fs), 2 }, 1478 { bs3CpuWeird1_Pop_gs_Ud2_c64, 64, false, +8, RT_UOFFSETOF(BS3REGCTX, gs), 2 }, 1423 1479 { bs3CpuWeird1_Push_opsize_fs_Ud2_c64, 64, true, -2, RT_UOFFSETOF(BS3REGCTX, fs), 3 }, 1480 { bs3CpuWeird1_Push_opsize_gs_Ud2_c64, 64, true, -2, RT_UOFFSETOF(BS3REGCTX, gs), 3 }, 1424 1481 { bs3CpuWeird1_Pop_opsize_fs_Ud2_c64, 64, false, +2, RT_UOFFSETOF(BS3REGCTX, fs), 3 }, 1482 { bs3CpuWeird1_Pop_opsize_gs_Ud2_c64, 64, false, +2, RT_UOFFSETOF(BS3REGCTX, gs), 3 }, 1425 1483 }; 1426 1484 BS3TRAPFRAME TrapCtx; … … 1430 1488 uint16_t const uPopSel = BS3_SEL_R3_SS16; 1431 1489 bool const fFullWrite = BS3_MODE_IS_64BIT_CODE(bTestMode) /* 64-bit mode writes are full (10980XE). */ 1432 || (g_enmCpuVendor = Bs3GetCpuVendor()) == BS3CPUVENDOR_AMD 1433 || g_enmCpuVendor == BS3CPUVENDOR_HYGON; 1490 || (g_enmCpuVendor = Bs3GetCpuVendor()) != BS3CPUVENDOR_INTEL; 1434 1491 bool const fFullRead = false /* But, 64-bit mode reads are word sized (10980XE). */ 1435 || (g_enmCpuVendor = Bs3GetCpuVendor()) == BS3CPUVENDOR_AMD 1436 || g_enmCpuVendor == BS3CPUVENDOR_HYGON; 1492 || g_enmCpuVendor != BS3CPUVENDOR_INTEL; 1437 1493 bool const fInRmWrHiEfl = true /* 10890XE writes EFLAGS[31:16] in the high word of a 'o32 PUSH FS'. */ 1438 1494 && !fFullWrite; … … 1575 1631 } 1576 1632 uNominalEsp = Ctx.rsp.u32; 1577 1578 1633 for (iTest = 0; iTest < RT_ELEMENTS(s_aTests); iTest++) 1579 1634 { 1580 1635 if (s_aTests[iTest].cBits == cTestBits) 1581 1636 { 1582 uint16_t BS3_FAR *pRegCtx = (uint16_t BS3_FAR *)((uint8_t BS3_FAR *)&Ctx + s_aTests[iTest].offReg); 1583 uint16_t BS3_FAR *pRegExpect = (uint16_t BS3_FAR *)((uint8_t BS3_FAR *)&TrapExpect.Ctx + s_aTests[iTest].offReg); 1584 uint16_t const uSavedSel = *pRegCtx; 1585 uint8_t const cbItem = RT_ABS(s_aTests[iTest].cbAdjSp); 1637 uint16_t BS3_FAR *pRegCtx = (uint16_t BS3_FAR *)((uint8_t BS3_FAR *)&Ctx + s_aTests[iTest].offReg); 1638 uint16_t BS3_FAR *pRegExpect = (uint16_t BS3_FAR *)((uint8_t BS3_FAR *)&TrapExpect.Ctx + s_aTests[iTest].offReg); 1639 uint16_t const uSavedSel = *pRegCtx; 1640 uint8_t const cbItem = RT_ABS(s_aTests[iTest].cbAdjSp); 1641 bool const fDefaultSel = s_aTests[iTest].offReg == RT_UOFFSETOF(BS3REGCTX, ss) 1642 || s_aTests[iTest].offReg == RT_UOFFSETOF(BS3REGCTX, cs); 1586 1643 unsigned iRep; /**< This is to trigger native recompilation. */ 1587 1644 BS3PTRUNION PtrStack2; 1588 1645 1589 *pRegCtx = uInitialSel; 1646 if (!fDefaultSel) 1647 *pRegCtx = uInitialSel; 1590 1648 1591 1649 /* Calculate the stack read/write location for this test. PtrStack … … 1660 1718 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 1661 1719 if (bs3CpuWeird1_ComparePushPop(&TrapCtx, &TrapExpect)) 1720 { 1721 ASMHalt(); 1662 1722 break; 1663 1664 //if (iVariation < 3) 1723 } 1724 1725 if (*PtrStack2.pu64 != u64ExpectPushed.u) 1665 1726 { 1666 if (*PtrStack2.pu64 != u64ExpectPushed.u) 1667 { 1668 Bs3TestFailedF("%u - Unexpected stack value after push: %RX64, expected %RX64", 1669 g_usBs3TestStep, *PtrStack2.pu64, u64ExpectPushed); 1670 break; 1671 } 1727 Bs3TestFailedF("%u - Unexpected stack value after push: %RX64, expected %RX64", 1728 g_usBs3TestStep, *PtrStack2.pu64, u64ExpectPushed); 1729 break; 1672 1730 } 1673 //else if (*PtrStack2.pu16 != u64ExpectPushed.au16[0])1674 //{1675 // Bs3TestFailedF("%u - Unexpected stack value after push: %RX16, expected %RX16",1676 // g_usBs3TestStep, *PtrStack2.pu16, u64ExpectPushed.au16[0]);1677 // break;1678 //}1679 1731 } 1680 1732 #endif … … 1687 1739 */ 1688 1740 if (TrapExpect.bXcpt == X86_XCPT_UD) 1689 *pRegExpect = uPopSel;1741 *pRegExpect = !fDefaultSel ? uPopSel : *pRegCtx; 1690 1742 1691 1743 for (iRep = 0; iRep < 256; iRep++) 1692 1744 { 1693 1745 bs3CpuWeird1_PushPopInitStack(PtrStack2); 1694 *PtrStack2.pu16 = uPopSel;1746 *PtrStack2.pu16 = !fDefaultSel ? uPopSel : *pRegCtx; 1695 1747 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 1696 1748 if (bs3CpuWeird1_ComparePushPop(&TrapCtx, &TrapExpect)) 1749 { 1750 ASMHalt(); 1697 1751 break; 1752 } 1698 1753 } 1699 1754 #endif -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-weird-1.c
r102779 r102789 57 57 static const BS3TESTMODEBYONEENTRY g_aModeByOneTests[] = 58 58 { 59 #if 1/** @todo fails in native recompiler atm. */ /** @todo asserts in ring-0 on VT-x! */59 #if 0 /** @todo fails in native recompiler atm. */ /** @todo asserts in ring-0 on VT-x! */ 60 60 { "dbg+inhibit+ringxfer", bs3CpuWeird1_DbgInhibitRingXfer_f16, 0 }, 61 61 #endif 62 #if 1/** @todo asserts in native recompiler debug builds, but seems to work otherwise. */62 #if 0 /** @todo asserts in native recompiler debug builds, but seems to work otherwise. */ 63 63 { "pc wrapping", bs3CpuWeird1_PcWrapping_f16, 0 }, 64 64 #endif 65 { "push/pop", bs3CpuWeird1_PushPop_f16, 0 },65 // { "push/pop", bs3CpuWeird1_PushPop_f16, 0 }, 66 66 { "push/pop sreg", bs3CpuWeird1_PushPopSReg_f16, 0 }, 67 67 };
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