- Timestamp:
- Feb 4, 2024 11:41:47 PM (12 months ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 2 edited
-
IEMAllInstOneByte.cpp.h (modified) (1 diff)
-
IEMAllInstTwoByte0f.cpp.h (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h
r103190 r103191 13777 13777 13778 13778 /** 13779 * @opmaps grp3_f613780 * @opcode /013779 * @opmaps grp3_f6 13780 * @opcode /0 13781 13781 * @opflclass logical 13782 13782 * @todo also /1 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
r103185 r103191 9583 9583 * Common worker for iemOp_shrd_Ev_Gv_Ib and iemOp_shld_Ev_Gv_Ib. 9584 9584 */ 9585 FNIEMOP_DEF_1(iemOpCommonShldShrd_Ib, PCIEMOPSHIFTDBLSIZES, pImpl) 9586 { 9587 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);9588 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_OF);9589 9590 if (IEM_IS_MODRM_REG_MODE(bRm))9591 {9592 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);9593 9594 switch (pVCpu->iem.s.enmEffOpSize)9595 {9596 case IEMMODE_16BIT:9597 IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0);9598 IEM OP_HLP_DONE_DECODING_NO_LOCK_PREFIX();9599 IEM _MC_ARG(uint16_t *, pu16Dst, 0);9600 IEM_MC_ARG(uint16_t , u16Src, 1);9601 IEM_MC_ARG _CONST(uint8_t, cShiftArg, /*=*/cShift, 2);9602 IEM_MC_ARG (uint32_t *, pEFlags, 3);9603 9604 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm));9605 IEM_MC_ REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm));9606 IEM_MC_REF_ EFLAGS(pEFlags);9607 IEM_MC_ CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);9608 9609 IEM_MC_ADVANCE_RIP_AND_FINISH();9610 IEM_MC_ END();9611 break;9612 9613 case IEMMODE_32BIT:9614 IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0);9615 IEM OP_HLP_DONE_DECODING_NO_LOCK_PREFIX();9616 IEM _MC_ARG(uint32_t *, pu32Dst, 0);9617 IEM_MC_ARG(uint32_t , u32Src, 1);9618 IEM_MC_ARG _CONST(uint8_t, cShiftArg, /*=*/cShift, 2);9619 IEM_MC_ARG (uint32_t *, pEFlags, 3);9620 9621 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm));9622 IEM_MC_ REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm));9623 IEM_MC_REF_ EFLAGS(pEFlags);9624 IEM_MC_ CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);9625 9626 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm));9627 IEM_MC_ ADVANCE_RIP_AND_FINISH();9628 IEM_MC_ END();9629 break;9630 9631 case IEMMODE_64BIT:9632 IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0);9633 IEM OP_HLP_DONE_DECODING_NO_LOCK_PREFIX();9634 IEM _MC_ARG(uint64_t *, pu64Dst, 0);9635 IEM_MC_ARG(uint64_t , u64Src, 1);9636 IEM_MC_ARG _CONST(uint8_t, cShiftArg, /*=*/cShift, 2);9637 IEM_MC_ARG (uint32_t *, pEFlags, 3);9638 9639 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm));9640 IEM_MC_ REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm));9641 IEM_MC_REF_ EFLAGS(pEFlags);9642 IEM_MC_ CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);9643 9644 IEM_MC_ADVANCE_RIP_AND_FINISH();9645 IEM_MC_ END();9646 break;9647 9648 IEM_NOT_REACHED_DEFAULT_CASE_RET();9649 }9650 }9651 else9652 {9653 switch (pVCpu->iem.s.enmEffOpSize)9654 {9655 case IEMMODE_16BIT:9656 IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0);9657 IEM_MC_ LOCAL(RTGCPTR, GCPtrEffDst);9658 IEM_MC_ CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);9659 9660 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);9661 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();9662 9663 IEM_MC_LOCAL(uint8_t, bUnmapInfo);9664 IEM_MC_ ARG(uint16_t *, pu16Dst, 0);9665 IEM_MC_ MEM_MAP_U16_RW(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst);9666 9667 IEM_MC_ARG(uint16_t, u16Src, 1);9668 IEM_MC_ FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm));9669 IEM_MC_ ARG_CONST(uint8_t, cShiftArg,/*=*/ cShift, 2);9670 IEM_MC_ARG_ LOCAL_EFLAGS( pEFlags, EFlags, 3);9671 IEM_MC_ FETCH_EFLAGS(EFlags);9672 IEM_MC_ CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags);9673 9674 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo);9675 IEM_MC_ COMMIT_EFLAGS(EFlags);9676 IEM_MC_ ADVANCE_RIP_AND_FINISH();9677 IEM_MC_ END();9678 break;9679 9680 case IEMMODE_32BIT:9681 IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0);9682 IEM_MC_ LOCAL(RTGCPTR, GCPtrEffDst);9683 IEM_MC_ CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);9684 9685 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);9686 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();9687 9688 IEM_MC_LOCAL(uint8_t, bUnmapInfo);9689 IEM_MC_ ARG(uint32_t *, pu32Dst, 0);9690 IEM_MC_ MEM_MAP_U32_RW(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst);9691 9692 IEM_MC_ARG(uint32_t, u32Src, 1);9693 IEM_MC_ FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm));9694 IEM_MC_ ARG_CONST(uint8_t, cShiftArg,/*=*/ cShift, 2);9695 IEM_MC_ARG_ LOCAL_EFLAGS( pEFlags, EFlags, 3);9696 IEM_MC_ FETCH_EFLAGS(EFlags);9697 IEM_MC_ CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags);9698 9699 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo);9700 IEM_MC_ COMMIT_EFLAGS(EFlags);9701 IEM_MC_ ADVANCE_RIP_AND_FINISH();9702 IEM_MC_ END();9703 break;9704 9705 case IEMMODE_64BIT:9706 IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT, 0);9707 IEM_MC_ LOCAL(RTGCPTR, GCPtrEffDst);9708 IEM_MC_ CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1);9709 9710 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift);9711 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();9712 9713 IEM_MC_LOCAL(uint8_t, bUnmapInfo);9714 IEM_MC_ ARG(uint64_t *, pu64Dst, 0);9715 IEM_MC_ MEM_MAP_U64_RW(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst);9716 9717 IEM_MC_ARG(uint64_t, u64Src, 1);9718 IEM_MC_ FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm));9719 IEM_MC_ ARG_CONST(uint8_t, cShiftArg,/*=*/ cShift, 2);9720 IEM_MC_ARG_ LOCAL_EFLAGS( pEFlags, EFlags, 3);9721 IEM_MC_ FETCH_EFLAGS(EFlags);9722 9723 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags);9724 9725 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo);9726 IEM_MC_ COMMIT_EFLAGS(EFlags);9727 IEM_MC_ ADVANCE_RIP_AND_FINISH();9728 IEM_MC_ END();9729 break;9730 9731 IEM_NOT_REACHED_DEFAULT_CASE_RET();9732 }9733 }9734 } 9585 #define IEMOP_BODY_SHLD_SHR_Ib(a_pImplExpr) \ 9586 PCIEMOPSHIFTDBLSIZES const pImpl = (a_pImplExpr); \ 9587 \ 9588 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \ 9589 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_OF); \ 9590 \ 9591 if (IEM_IS_MODRM_REG_MODE(bRm)) \ 9592 { \ 9593 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift); \ 9594 \ 9595 switch (pVCpu->iem.s.enmEffOpSize) \ 9596 { \ 9597 case IEMMODE_16BIT: \ 9598 IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0); \ 9599 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9600 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 9601 IEM_MC_ARG(uint16_t, u16Src, 1); \ 9602 IEM_MC_ARG_CONST(uint8_t, cShiftArg, /*=*/cShift, 2); \ 9603 IEM_MC_ARG(uint32_t *, pEFlags, 3); \ 9604 \ 9605 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9606 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9607 IEM_MC_REF_EFLAGS(pEFlags); \ 9608 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags); \ 9609 \ 9610 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9611 IEM_MC_END(); \ 9612 break; \ 9613 \ 9614 case IEMMODE_32BIT: \ 9615 IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0); \ 9616 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9617 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 9618 IEM_MC_ARG(uint32_t, u32Src, 1); \ 9619 IEM_MC_ARG_CONST(uint8_t, cShiftArg, /*=*/cShift, 2); \ 9620 IEM_MC_ARG(uint32_t *, pEFlags, 3); \ 9621 \ 9622 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9623 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9624 IEM_MC_REF_EFLAGS(pEFlags); \ 9625 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags); \ 9626 \ 9627 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9628 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9629 IEM_MC_END(); \ 9630 break; \ 9631 \ 9632 case IEMMODE_64BIT: \ 9633 IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0); \ 9634 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9635 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 9636 IEM_MC_ARG(uint64_t, u64Src, 1); \ 9637 IEM_MC_ARG_CONST(uint8_t, cShiftArg, /*=*/cShift, 2); \ 9638 IEM_MC_ARG(uint32_t *, pEFlags, 3); \ 9639 \ 9640 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9641 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9642 IEM_MC_REF_EFLAGS(pEFlags); \ 9643 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags); \ 9644 \ 9645 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9646 IEM_MC_END(); \ 9647 break; \ 9648 \ 9649 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 9650 } \ 9651 } \ 9652 else \ 9653 { \ 9654 switch (pVCpu->iem.s.enmEffOpSize) \ 9655 { \ 9656 case IEMMODE_16BIT: \ 9657 IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0); \ 9658 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9659 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1); \ 9660 \ 9661 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift); \ 9662 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9663 \ 9664 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9665 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 9666 IEM_MC_MEM_MAP_U16_RW(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9667 \ 9668 IEM_MC_ARG(uint16_t, u16Src, 1); \ 9669 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9670 IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=*/ cShift, 2); \ 9671 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3); \ 9672 IEM_MC_FETCH_EFLAGS(EFlags); \ 9673 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags); \ 9674 \ 9675 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9676 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9677 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9678 IEM_MC_END(); \ 9679 break; \ 9680 \ 9681 case IEMMODE_32BIT: \ 9682 IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0); \ 9683 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9684 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1); \ 9685 \ 9686 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift); \ 9687 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9688 \ 9689 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9690 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 9691 IEM_MC_MEM_MAP_U32_RW(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9692 \ 9693 IEM_MC_ARG(uint32_t, u32Src, 1); \ 9694 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9695 IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=*/ cShift, 2); \ 9696 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3); \ 9697 IEM_MC_FETCH_EFLAGS(EFlags); \ 9698 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags); \ 9699 \ 9700 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9701 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9702 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9703 IEM_MC_END(); \ 9704 break; \ 9705 \ 9706 case IEMMODE_64BIT: \ 9707 IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT, 0); \ 9708 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9709 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1); \ 9710 \ 9711 uint8_t cShift; IEM_OPCODE_GET_NEXT_U8(&cShift); \ 9712 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9713 \ 9714 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9715 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 9716 IEM_MC_MEM_MAP_U64_RW(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9717 \ 9718 IEM_MC_ARG(uint64_t, u64Src, 1); \ 9719 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9720 IEM_MC_ARG_CONST(uint8_t, cShiftArg,/*=*/ cShift, 2); \ 9721 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3); \ 9722 IEM_MC_FETCH_EFLAGS(EFlags); \ 9723 \ 9724 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags); \ 9725 \ 9726 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9727 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9728 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9729 IEM_MC_END(); \ 9730 break; \ 9731 \ 9732 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 9733 } \ 9734 } (void)0 9735 9735 9736 9736 … … 9738 9738 * Common worker for iemOp_shrd_Ev_Gv_CL and iemOp_shld_Ev_Gv_CL. 9739 9739 */ 9740 FNIEMOP_DEF_1(iemOpCommonShldShrd_CL, PCIEMOPSHIFTDBLSIZES, pImpl) 9741 { 9742 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 9743 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_OF); 9744 9745 if (IEM_IS_MODRM_REG_MODE(bRm)) 9746 { 9747 switch (pVCpu->iem.s.enmEffOpSize) 9748 { 9749 case IEMMODE_16BIT: 9750 IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0); 9751 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9752 IEM_MC_ARG(uint16_t *, pu16Dst, 0); 9753 IEM_MC_ARG(uint16_t, u16Src, 1); 9754 IEM_MC_ARG(uint8_t, cShiftArg, 2); 9755 IEM_MC_ARG(uint32_t *, pEFlags, 3); 9756 9757 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); 9758 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); 9759 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); 9760 IEM_MC_REF_EFLAGS(pEFlags); 9761 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags); 9762 9763 IEM_MC_ADVANCE_RIP_AND_FINISH(); 9764 IEM_MC_END(); 9765 break; 9766 9767 case IEMMODE_32BIT: 9768 IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0); 9769 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9770 IEM_MC_ARG(uint32_t *, pu32Dst, 0); 9771 IEM_MC_ARG(uint32_t, u32Src, 1); 9772 IEM_MC_ARG(uint8_t, cShiftArg, 2); 9773 IEM_MC_ARG(uint32_t *, pEFlags, 3); 9774 9775 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); 9776 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); 9777 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); 9778 IEM_MC_REF_EFLAGS(pEFlags); 9779 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags); 9780 9781 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); 9782 IEM_MC_ADVANCE_RIP_AND_FINISH(); 9783 IEM_MC_END(); 9784 break; 9785 9786 case IEMMODE_64BIT: 9787 IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0); 9788 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9789 IEM_MC_ARG(uint64_t *, pu64Dst, 0); 9790 IEM_MC_ARG(uint64_t, u64Src, 1); 9791 IEM_MC_ARG(uint8_t, cShiftArg, 2); 9792 IEM_MC_ARG(uint32_t *, pEFlags, 3); 9793 9794 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); 9795 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); 9796 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); 9797 IEM_MC_REF_EFLAGS(pEFlags); 9798 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags); 9799 9800 IEM_MC_ADVANCE_RIP_AND_FINISH(); 9801 IEM_MC_END(); 9802 break; 9803 9804 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 9805 } 9806 } 9807 else 9808 { 9809 switch (pVCpu->iem.s.enmEffOpSize) 9810 { 9811 case IEMMODE_16BIT: 9812 IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0); 9813 IEM_MC_ARG(uint16_t *, pu16Dst, 0); 9814 IEM_MC_ARG(uint16_t, u16Src, 1); 9815 IEM_MC_ARG(uint8_t, cShiftArg, 2); 9816 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3); 9817 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 9818 IEM_MC_LOCAL(uint8_t, bUnmapInfo); 9819 9820 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 9821 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9822 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); 9823 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); 9824 IEM_MC_FETCH_EFLAGS(EFlags); 9825 IEM_MC_MEM_MAP_U16_RW(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 9826 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags); 9827 9828 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); 9829 IEM_MC_COMMIT_EFLAGS(EFlags); 9830 IEM_MC_ADVANCE_RIP_AND_FINISH(); 9831 IEM_MC_END(); 9832 break; 9833 9834 case IEMMODE_32BIT: 9835 IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0); 9836 IEM_MC_ARG(uint32_t *, pu32Dst, 0); 9837 IEM_MC_ARG(uint32_t, u32Src, 1); 9838 IEM_MC_ARG(uint8_t, cShiftArg, 2); 9839 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3); 9840 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 9841 IEM_MC_LOCAL(uint8_t, bUnmapInfo); 9842 9843 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 9844 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9845 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); 9846 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); 9847 IEM_MC_FETCH_EFLAGS(EFlags); 9848 IEM_MC_MEM_MAP_U32_RW(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 9849 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags); 9850 9851 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); 9852 IEM_MC_COMMIT_EFLAGS(EFlags); 9853 IEM_MC_ADVANCE_RIP_AND_FINISH(); 9854 IEM_MC_END(); 9855 break; 9856 9857 case IEMMODE_64BIT: 9858 IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT, 0); 9859 IEM_MC_ARG(uint64_t *, pu64Dst, 0); 9860 IEM_MC_ARG(uint64_t, u64Src, 1); 9861 IEM_MC_ARG(uint8_t, cShiftArg, 2); 9862 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3); 9863 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 9864 IEM_MC_LOCAL(uint8_t, bUnmapInfo); 9865 9866 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 9867 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9868 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); 9869 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); 9870 IEM_MC_FETCH_EFLAGS(EFlags); 9871 IEM_MC_MEM_MAP_U64_RW(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 9872 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags); 9873 9874 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); 9875 IEM_MC_COMMIT_EFLAGS(EFlags); 9876 IEM_MC_ADVANCE_RIP_AND_FINISH(); 9877 IEM_MC_END(); 9878 break; 9879 9880 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 9881 } 9882 } 9883 } 9884 9885 9886 9887 /** Opcode 0x0f 0xa4. */ 9740 #define IEMOP_BODY_SHLD_SHRD_Ev_Gv_CL(a_pImplExpr) \ 9741 PCIEMOPSHIFTDBLSIZES const pImpl = (a_pImplExpr); \ 9742 \ 9743 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); \ 9744 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF | X86_EFL_OF); \ 9745 \ 9746 if (IEM_IS_MODRM_REG_MODE(bRm)) \ 9747 { \ 9748 switch (pVCpu->iem.s.enmEffOpSize) \ 9749 { \ 9750 case IEMMODE_16BIT: \ 9751 IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0); \ 9752 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9753 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 9754 IEM_MC_ARG(uint16_t, u16Src, 1); \ 9755 IEM_MC_ARG(uint8_t, cShiftArg, 2); \ 9756 IEM_MC_ARG(uint32_t *, pEFlags, 3); \ 9757 \ 9758 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9759 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); \ 9760 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9761 IEM_MC_REF_EFLAGS(pEFlags); \ 9762 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags); \ 9763 \ 9764 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9765 IEM_MC_END(); \ 9766 break; \ 9767 \ 9768 case IEMMODE_32BIT: \ 9769 IEM_MC_BEGIN(4, 0, IEM_MC_F_MIN_386, 0); \ 9770 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9771 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 9772 IEM_MC_ARG(uint32_t, u32Src, 1); \ 9773 IEM_MC_ARG(uint8_t, cShiftArg, 2); \ 9774 IEM_MC_ARG(uint32_t *, pEFlags, 3); \ 9775 \ 9776 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9777 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); \ 9778 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9779 IEM_MC_REF_EFLAGS(pEFlags); \ 9780 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags); \ 9781 \ 9782 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9783 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9784 IEM_MC_END(); \ 9785 break; \ 9786 \ 9787 case IEMMODE_64BIT: \ 9788 IEM_MC_BEGIN(4, 0, IEM_MC_F_64BIT, 0); \ 9789 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9790 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 9791 IEM_MC_ARG(uint64_t, u64Src, 1); \ 9792 IEM_MC_ARG(uint8_t, cShiftArg, 2); \ 9793 IEM_MC_ARG(uint32_t *, pEFlags, 3); \ 9794 \ 9795 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9796 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); \ 9797 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9798 IEM_MC_REF_EFLAGS(pEFlags); \ 9799 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags); \ 9800 \ 9801 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9802 IEM_MC_END(); \ 9803 break; \ 9804 \ 9805 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 9806 } \ 9807 } \ 9808 else \ 9809 { \ 9810 switch (pVCpu->iem.s.enmEffOpSize) \ 9811 { \ 9812 case IEMMODE_16BIT: \ 9813 IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0); \ 9814 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 9815 IEM_MC_ARG(uint16_t, u16Src, 1); \ 9816 IEM_MC_ARG(uint8_t, cShiftArg, 2); \ 9817 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3); \ 9818 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9819 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9820 \ 9821 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 9822 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9823 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9824 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); \ 9825 IEM_MC_FETCH_EFLAGS(EFlags); \ 9826 IEM_MC_MEM_MAP_U16_RW(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9827 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags); \ 9828 \ 9829 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9830 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9831 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9832 IEM_MC_END(); \ 9833 break; \ 9834 \ 9835 case IEMMODE_32BIT: \ 9836 IEM_MC_BEGIN(4, 3, IEM_MC_F_MIN_386, 0); \ 9837 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 9838 IEM_MC_ARG(uint32_t, u32Src, 1); \ 9839 IEM_MC_ARG(uint8_t, cShiftArg, 2); \ 9840 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3); \ 9841 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9842 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9843 \ 9844 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 9845 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9846 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9847 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); \ 9848 IEM_MC_FETCH_EFLAGS(EFlags); \ 9849 IEM_MC_MEM_MAP_U32_RW(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9850 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU32, pu32Dst, u32Src, cShiftArg, pEFlags); \ 9851 \ 9852 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9853 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9854 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9855 IEM_MC_END(); \ 9856 break; \ 9857 \ 9858 case IEMMODE_64BIT: \ 9859 IEM_MC_BEGIN(4, 3, IEM_MC_F_64BIT, 0); \ 9860 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 9861 IEM_MC_ARG(uint64_t, u64Src, 1); \ 9862 IEM_MC_ARG(uint8_t, cShiftArg, 2); \ 9863 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 3); \ 9864 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 9865 IEM_MC_LOCAL(uint8_t, bUnmapInfo); \ 9866 \ 9867 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 9868 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 9869 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm)); \ 9870 IEM_MC_FETCH_GREG_U8(cShiftArg, X86_GREG_xCX); \ 9871 IEM_MC_FETCH_EFLAGS(EFlags); \ 9872 IEM_MC_MEM_MAP_U64_RW(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \ 9873 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags); \ 9874 \ 9875 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9876 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9877 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 9878 IEM_MC_END(); \ 9879 break; \ 9880 \ 9881 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 9882 } \ 9883 } (void)0 9884 9885 9886 /** 9887 * @opcode 0xa4 9888 * @opflclass shift_count 9889 */ 9888 9890 FNIEMOP_DEF(iemOp_shld_Ev_Gv_Ib) 9889 9891 { 9890 9892 IEMOP_MNEMONIC(shld_Ev_Gv_Ib, "shld Ev,Gv,Ib"); 9891 9893 IEMOP_HLP_MIN_386(); 9892 return FNIEMOP_CALL_1(iemOpCommonShldShrd_Ib, IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shld_eflags)); 9893 } 9894 9895 9896 /** Opcode 0x0f 0xa5. */ 9894 IEMOP_BODY_SHLD_SHR_Ib(IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shld_eflags)); 9895 } 9896 9897 9898 /** 9899 * @opcode 0xa5 9900 * @opflclass shift_count 9901 */ 9897 9902 FNIEMOP_DEF(iemOp_shld_Ev_Gv_CL) 9898 9903 { 9899 9904 IEMOP_MNEMONIC(shld_Ev_Gv_CL, "shld Ev,Gv,CL"); 9900 9905 IEMOP_HLP_MIN_386(); 9901 return FNIEMOP_CALL_1(iemOpCommonShldShrd_CL,IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shld_eflags));9906 IEMOP_BODY_SHLD_SHRD_Ev_Gv_CL(IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shld_eflags)); 9902 9907 } 9903 9908 … … 9957 9962 9958 9963 9959 /** Opcode 0x0f 0xac. */ 9964 /** 9965 * @opcode 0xac 9966 * @opflclass shift_count 9967 */ 9960 9968 FNIEMOP_DEF(iemOp_shrd_Ev_Gv_Ib) 9961 9969 { 9962 9970 IEMOP_MNEMONIC(shrd_Ev_Gv_Ib, "shrd Ev,Gv,Ib"); 9963 9971 IEMOP_HLP_MIN_386(); 9964 return FNIEMOP_CALL_1(iemOpCommonShldShrd_Ib, IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shrd_eflags)); 9965 } 9966 9967 9968 /** Opcode 0x0f 0xad. */ 9972 IEMOP_BODY_SHLD_SHR_Ib(IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shrd_eflags)); 9973 } 9974 9975 9976 /** 9977 * @opcode 0xad 9978 * @opflclass shift_count 9979 */ 9969 9980 FNIEMOP_DEF(iemOp_shrd_Ev_Gv_CL) 9970 9981 { 9971 9982 IEMOP_MNEMONIC(shrd_Ev_Gv_CL, "shrd Ev,Gv,CL"); 9972 9983 IEMOP_HLP_MIN_386(); 9973 return FNIEMOP_CALL_1(iemOpCommonShldShrd_CL,IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shrd_eflags));9984 IEMOP_BODY_SHLD_SHRD_Ev_Gv_CL(IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_shrd_eflags)); 9974 9985 } 9975 9986
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