Changeset 103265 in vbox for trunk/src/VBox
- Timestamp:
- Feb 8, 2024 5:22:21 AM (12 months ago)
- svn:sync-xref-src-repo-rev:
- 161556
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
r103184 r103265 4471 4471 IEMIMPL_SHIFT_OPT_F3 vpslld 4472 4472 IEMIMPL_SHIFT_OPT_F3 vpsllq 4473 IEMIMPL_SHIFT_OPT_F3 vpsraw 4474 IEMIMPL_SHIFT_OPT_F3 vpsrad 4473 4475 4474 4476 -
trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
r103264 r103265 10205 10205 #endif 10206 10206 10207 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsraw_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, uint8_t uShift)) 10208 { 10209 RTUINT128U uSrc1 = *puSrc1; 10210 10211 uShift = RT_MIN(15, uShift); 10212 10213 puDst->ai16[0] = uSrc1.ai16[0] >> uShift; 10214 puDst->ai16[1] = uSrc1.ai16[1] >> uShift; 10215 puDst->ai16[2] = uSrc1.ai16[2] >> uShift; 10216 puDst->ai16[3] = uSrc1.ai16[3] >> uShift; 10217 puDst->ai16[4] = uSrc1.ai16[4] >> uShift; 10218 puDst->ai16[5] = uSrc1.ai16[5] >> uShift; 10219 puDst->ai16[6] = uSrc1.ai16[6] >> uShift; 10220 puDst->ai16[7] = uSrc1.ai16[7] >> uShift; 10221 } 10222 10223 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsraw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2)) 10224 { 10225 iemAImpl_vpsraw_imm_u128_fallback(puDst, puSrc1, RT_MIN(15, puSrc2->au64[0])); 10226 } 10227 10228 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsraw_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, uint8_t uShift)) 10229 { 10230 iemAImpl_vpsraw_imm_u128_fallback(puDst, puSrc1, uShift); 10231 } 10232 10233 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsraw_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, uint8_t uShift)) 10234 { 10235 RTUINT256U uSrc1 = *puSrc1; 10236 10237 uShift = RT_MIN(15, uShift); 10238 10239 puDst->ai16[0] = uSrc1.ai16[0] >> uShift; 10240 puDst->ai16[1] = uSrc1.ai16[1] >> uShift; 10241 puDst->ai16[2] = uSrc1.ai16[2] >> uShift; 10242 puDst->ai16[3] = uSrc1.ai16[3] >> uShift; 10243 puDst->ai16[4] = uSrc1.ai16[4] >> uShift; 10244 puDst->ai16[5] = uSrc1.ai16[5] >> uShift; 10245 puDst->ai16[6] = uSrc1.ai16[6] >> uShift; 10246 puDst->ai16[7] = uSrc1.ai16[7] >> uShift; 10247 puDst->ai16[8] = uSrc1.ai16[8] >> uShift; 10248 puDst->ai16[9] = uSrc1.ai16[9] >> uShift; 10249 puDst->ai16[10] = uSrc1.ai16[10] >> uShift; 10250 puDst->ai16[11] = uSrc1.ai16[11] >> uShift; 10251 puDst->ai16[12] = uSrc1.ai16[12] >> uShift; 10252 puDst->ai16[13] = uSrc1.ai16[13] >> uShift; 10253 puDst->ai16[14] = uSrc1.ai16[14] >> uShift; 10254 puDst->ai16[15] = uSrc1.ai16[15] >> uShift; 10255 } 10256 10257 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsraw_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, uint8_t uShift)) 10258 { 10259 iemAImpl_vpsraw_imm_u256_fallback(puDst, puSrc1, uShift); 10260 } 10261 10262 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsraw_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2)) 10263 { 10264 iemAImpl_vpsraw_imm_u256_fallback(puDst, puSrc1, RT_MIN(15, puSrc2->au64[0])); 10265 } 10266 10207 10267 10208 10268 /* … … 10514 10574 10515 10575 #endif 10576 10577 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrad_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, uint8_t uShift)) 10578 { 10579 RTUINT128U uSrc1 = *puSrc1; 10580 10581 uShift = RT_MIN(31, uShift); 10582 10583 puDst->ai32[0] = uSrc1.ai32[0] >> uShift; 10584 puDst->ai32[1] = uSrc1.ai32[1] >> uShift; 10585 puDst->ai32[2] = uSrc1.ai32[2] >> uShift; 10586 puDst->ai32[3] = uSrc1.ai32[3] >> uShift; 10587 } 10588 10589 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrad_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, uint8_t uShift)) 10590 { 10591 iemAImpl_vpsrad_imm_u128_fallback(puDst, puSrc1, uShift); 10592 } 10593 10594 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrad_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2)) 10595 { 10596 iemAImpl_vpsrad_imm_u128_fallback(puDst, puSrc1, RT_MIN(31, puSrc2->au64[0])); 10597 } 10598 10599 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrad_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, uint8_t uShift)) 10600 { 10601 RTUINT256U uSrc1 = *puSrc1; 10602 10603 uShift = RT_MIN(31, uShift); 10604 10605 puDst->ai32[0] = uSrc1.ai32[0] >> uShift; 10606 puDst->ai32[1] = uSrc1.ai32[1] >> uShift; 10607 puDst->ai32[2] = uSrc1.ai32[2] >> uShift; 10608 puDst->ai32[3] = uSrc1.ai32[3] >> uShift; 10609 puDst->ai32[4] = uSrc1.ai32[4] >> uShift; 10610 puDst->ai32[5] = uSrc1.ai32[5] >> uShift; 10611 puDst->ai32[6] = uSrc1.ai32[6] >> uShift; 10612 puDst->ai32[7] = uSrc1.ai32[7] >> uShift; 10613 } 10614 10615 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrad_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2)) 10616 { 10617 iemAImpl_vpsrad_imm_u256_fallback(puDst, puSrc1, RT_MIN(31, puSrc2->au64[0])); 10618 } 10619 10620 IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrad_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, uint8_t uShift)) 10621 { 10622 iemAImpl_vpsrad_imm_u256_fallback(puDst, puSrc1, uShift); 10623 } 10516 10624 10517 10625 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h
r103256 r103265 3641 3641 /* Opcode VEX.0F 0x71 11/4 - invalid */ 3642 3642 /** Opcode VEX.66.0F 0x71 11/4. */ 3643 FNIEMOP_STUB_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm); 3643 FNIEMOP_DEF_1(iemOp_VGrp12_vpsraw_Hx_Ux_Ib, uint8_t, bRm) 3644 { 3645 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRAW, vpsraw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); 3646 if (pVCpu->iem.s.uVexLength) 3647 { 3648 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm, 3649 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback)); 3650 } 3651 else 3652 { 3653 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm, 3654 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback)); 3655 } 3656 } 3644 3657 3645 3658 /* Opcode VEX.0F 0x71 11/6 - invalid */ … … 3697 3710 /* Opcode VEX.0F 0x72 11/4 - invalid. */ 3698 3711 /** Opcode VEX.66.0F 0x72 11/4. */ 3699 FNIEMOP_STUB_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm); 3712 FNIEMOP_DEF_1(iemOp_VGrp13_vpsrad_Hx_Ux_Ib, uint8_t, bRm) 3713 { 3714 IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRAD, vpsrad, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); 3715 if (pVCpu->iem.s.uVexLength) 3716 { 3717 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm, 3718 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback)); 3719 } 3720 else 3721 { 3722 return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm, 3723 IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback)); 3724 } 3725 } 3700 3726 3701 3727 /* Opcode VEX.0F 0x72 11/6 - invalid. */ … … 5054 5080 /* Opcode VEX.0F 0xe1 - invalid */ 5055 5081 /** Opcode VEX.66.0F 0xe1 - vpsraw Vx, Hx, W */ 5056 FNIEMOP_STUB(iemOp_vpsraw_Vx_Hx_W); 5082 FNIEMOP_DEF(iemOp_vpsraw_Vx_Hx_W) 5083 { 5084 IEMOP_MNEMONIC3(VEX_RVM, VPSRAW, vpsraw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); 5085 IEMOPMEDIAOPTF3_INIT_VARS(vpsraw); 5086 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback)); 5087 } 5088 5057 5089 /* Opcode VEX.F3.0F 0xe1 - invalid */ 5058 5090 /* Opcode VEX.F2.0F 0xe1 - invalid */ … … 5060 5092 /* Opcode VEX.0F 0xe2 - invalid */ 5061 5093 /** Opcode VEX.66.0F 0xe2 - vpsrad Vx, Hx, Wx */ 5062 FNIEMOP_STUB(iemOp_vpsrad_Vx_Hx_Wx); 5094 FNIEMOP_DEF(iemOp_vpsrad_Vx_Hx_Wx) 5095 { 5096 IEMOP_MNEMONIC3(VEX_RVM, VPSRAD, vpsrad, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0); 5097 IEMOPMEDIAOPTF3_INIT_VARS(vpsrad); 5098 return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback)); 5099 } 5100 5063 5101 /* Opcode VEX.F3.0F 0xe2 - invalid */ 5064 5102 /* Opcode VEX.F2.0F 0xe2 - invalid */ -
trunk/src/VBox/VMM/include/IEMInternal.h
r103256 r103265 3151 3151 FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpslld_u128, iemAImpl_vpslld_u128_fallback; 3152 3152 FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsllq_u128, iemAImpl_vpsllq_u128_fallback; 3153 FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128, iemAImpl_vpsraw_u128_fallback; 3154 FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128, iemAImpl_vpsrad_u128_fallback; 3153 3155 3154 3156 FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback; … … 3225 3227 FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpslld_u256, iemAImpl_vpslld_u256_fallback; 3226 3228 FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsllq_u256, iemAImpl_vpsllq_u256_fallback; 3229 FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256, iemAImpl_vpsraw_u256_fallback; 3230 FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256, iemAImpl_vpsrad_u256_fallback; 3227 3231 3228 3232 FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback; … … 3555 3559 FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsllq_imm_u128, iemAImpl_vpsllq_imm_u128_fallback; 3556 3560 FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsllq_imm_u256, iemAImpl_vpsllq_imm_u256_fallback; 3561 3562 FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsraw_imm_u128, iemAImpl_vpsraw_imm_u128_fallback; 3563 FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsraw_imm_u256, iemAImpl_vpsraw_imm_u256_fallback; 3564 FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback; 3565 FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback; 3557 3566 /** @} */ 3558 3567
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