Changeset 103267 in vbox for trunk/src/VBox

Timestamp:

Feb 8, 2024 6:34:32 AM (12 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

161558

Message:

VMM/IEM: Implement vpsrl[wdq] 'reg/mem' instruction dispatch & emulation
VMM/IEM: Implement vpsrl[wdq] 'imm8' instruction decode, dispatch & emulation
bugref:9898

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllAImpl.asm (modified) (1 diff)
• VMMAll/IEMAllAImplC.cpp (modified) (3 diffs)
• VMMAll/IEMAllInstVexMap1.cpp.h (modified) (6 diffs)
• include/IEMInternal.h (modified) (3 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -4473 +4473 @@
 IEMIMPL_SHIFT_OPT_F3 vpsraw
 IEMIMPL_SHIFT_OPT_F3 vpsrad
+IEMIMPL_SHIFT_OPT_F3 vpsrlw
+IEMIMPL_SHIFT_OPT_F3 vpsrld
+IEMIMPL_SHIFT_OPT_F3 vpsrlq
 
 

trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

@@ -10130 +10130 @@
 #endif
 
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlw_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, uint8_t uShift))
+{
+    RTUINT128U uSrc1 = *puSrc1;
+ 
+    if (uShift <= 15)
+    {
+        puDst->au16[0] = uSrc1.au16[0] >> uShift;
+        puDst->au16[1] = uSrc1.au16[1] >> uShift;
+        puDst->au16[2] = uSrc1.au16[2] >> uShift;
+        puDst->au16[3] = uSrc1.au16[3] >> uShift;
+        puDst->au16[4] = uSrc1.au16[4] >> uShift;
+        puDst->au16[5] = uSrc1.au16[5] >> uShift;
+        puDst->au16[6] = uSrc1.au16[6] >> uShift;
+        puDst->au16[7] = uSrc1.au16[7] >> uShift;
+    }
+    else
+    {
+        puDst->au64[0] = 0;
+        puDst->au64[1] = 0;
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2))
+{
+    iemAImpl_vpsrlw_imm_u128_fallback(puDst, puSrc1, RT_MIN(15, puSrc2->au64[0]));
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlw_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, uint8_t uShift))
+{
+     iemAImpl_vpsrlw_imm_u128_fallback(puDst, puSrc1, uShift);
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlw_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, uint8_t uShift))
+{
+    RTUINT256U uSrc1 = *puSrc1;
+
+    if (uShift <= 15)
+    {
+        puDst->au16[0] = uSrc1.au16[0] >> uShift;
+        puDst->au16[1] = uSrc1.au16[1] >> uShift;
+        puDst->au16[2] = uSrc1.au16[2] >> uShift;
+        puDst->au16[3] = uSrc1.au16[3] >> uShift;
+        puDst->au16[4] = uSrc1.au16[4] >> uShift;
+        puDst->au16[5] = uSrc1.au16[5] >> uShift;
+        puDst->au16[6] = uSrc1.au16[6] >> uShift;
+        puDst->au16[7] = uSrc1.au16[7] >> uShift;
+        puDst->au16[8] = uSrc1.au16[8] >> uShift;
+        puDst->au16[9] = uSrc1.au16[9] >> uShift;
+        puDst->au16[10] = uSrc1.au16[10] >> uShift;
+        puDst->au16[11] = uSrc1.au16[11] >> uShift;
+        puDst->au16[12] = uSrc1.au16[12] >> uShift;
+        puDst->au16[13] = uSrc1.au16[13] >> uShift;
+        puDst->au16[14] = uSrc1.au16[14] >> uShift;
+        puDst->au16[15] = uSrc1.au16[15] >> uShift;
+    }
+    else
+    {
+        puDst->au64[0] = 0;
+        puDst->au64[1] = 0;
+        puDst->au64[2] = 0;
+        puDst->au64[3] = 0;
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlw_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, uint8_t uShift))
+{
+    iemAImpl_vpsrlw_imm_u256_fallback(puDst, puSrc1, uShift);
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlw_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2))
+{
+    iemAImpl_vpsrlw_imm_u256_fallback(puDst, puSrc1, RT_MIN(15, puSrc2->au64[0]));
+}
+
 
 /*
@@ -10512 +10586 @@
 #endif
 
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrld_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, uint8_t uShift))
+{
+    RTUINT128U uSrc1 = *puSrc1;
+ 
+    if (uShift <= 31)
+    {
+        puDst->au32[0] = uSrc1.au32[0] >> uShift;
+        puDst->au32[1] = uSrc1.au32[1] >> uShift;
+        puDst->au32[2] = uSrc1.au32[2] >> uShift;
+        puDst->au32[3] = uSrc1.au32[3] >> uShift;
+    }
+    else
+    {
+        puDst->au64[0] = 0;
+        puDst->au64[1] = 0;
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrld_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, uint8_t uShift))
+{
+    iemAImpl_vpsrld_imm_u128_fallback(puDst, puSrc1, uShift);
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrld_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2))
+{
+    iemAImpl_vpsrld_imm_u128_fallback(puDst, puSrc1, RT_MIN(31, puSrc2->au64[0]));
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrld_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, uint8_t uShift))
+{
+    RTUINT256U uSrc1 = *puSrc1;
+ 
+    if (uShift <= 31)
+    {
+       puDst->au32[0] = uSrc1.au32[0] >> uShift;
+       puDst->au32[1] = uSrc1.au32[1] >> uShift;
+       puDst->au32[2] = uSrc1.au32[2] >> uShift;
+       puDst->au32[3] = uSrc1.au32[3] >> uShift;
+       puDst->au32[4] = uSrc1.au32[4] >> uShift;
+       puDst->au32[5] = uSrc1.au32[5] >> uShift;
+       puDst->au32[6] = uSrc1.au32[6] >> uShift;
+       puDst->au32[7] = uSrc1.au32[7] >> uShift;
+    }
+    else
+    {
+        puDst->au64[0] = 0;
+        puDst->au64[1] = 0;
+        puDst->au64[2] = 0;
+        puDst->au64[3] = 0;
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrld_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2))
+{
+    iemAImpl_vpsrld_imm_u256_fallback(puDst, puSrc1, RT_MIN(31, puSrc2->au64[0]));
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrld_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, uint8_t uShift))
+{
+    iemAImpl_vpsrld_imm_u256_fallback(puDst, puSrc1, uShift);
+}
+
 
 /*
@@ -10840 +10976 @@
 
 #endif
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlq_imm_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, uint8_t uShift))
+{
+    RTUINT128U uSrc1 = *puSrc1;
+ 
+    if (uShift <= 63)
+    {
+        puDst->au64[0] = uSrc1.au64[0] >> uShift;
+        puDst->au64[1] = uSrc1.au64[1] >> uShift;
+    }
+    else
+    {
+        puDst->au64[0] = 0;
+        puDst->au64[1] = 0;
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlq_imm_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, uint8_t uShift))
+{
+    iemAImpl_vpsrlq_imm_u128_fallback(puDst, puSrc1, uShift);
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlq_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2))
+{
+    iemAImpl_vpsrlq_imm_u128_fallback(puDst, puSrc1, RT_MIN(31, puSrc2->au64[0]));
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlq_imm_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, uint8_t uShift))
+{
+    RTUINT256U uSrc1 = *puSrc1;
+ 
+    if (uShift <= 63)
+    {
+        puDst->au64[0] = uSrc1.au64[0] >> uShift;
+        puDst->au64[1] = uSrc1.au64[1] >> uShift;
+        puDst->au64[2] = uSrc1.au64[2] >> uShift;
+        puDst->au64[3] = uSrc1.au64[3] >> uShift;
+    }
+    else
+    {
+        puDst->au64[0] = 0;
+        puDst->au64[1] = 0;
+        puDst->au64[2] = 0;
+        puDst->au64[3] = 0;
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlq_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2))
+{
+    iemAImpl_vpsrlq_imm_u256_fallback(puDst, puSrc1, RT_MIN(31, puSrc2->au64[0]));
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlq_imm_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, uint8_t uShift))
+{
+    iemAImpl_vpsrlq_imm_u256_fallback(puDst, puSrc1, uShift);
+}
 
 

trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h

@@ -3637 +3637 @@
 /*  Opcode VEX.0F 0x71 11/2 - invalid. */
 /** Opcode VEX.66.0F 0x71 11/2. */
-FNIEMOP_STUB_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_VGrp12_vpsrlw_Hx_Ux_Ib, uint8_t, bRm)
+{
+    IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLW, vpsrlw, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
+    if (pVCpu->iem.s.uVexLength)
+    {
+        return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
+                              IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback));
+    }
+    else
+    {
+        return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
+                              IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback));
+    }
+}
+
 
 /*  Opcode VEX.0F 0x71 11/4 - invalid */
@@ -3706 +3720 @@
 /*  Opcode VEX.0F 0x72 11/2 - invalid. */
 /** Opcode VEX.66.0F 0x72 11/2. */
-FNIEMOP_STUB_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_VGrp13_vpsrld_Hx_Ux_Ib, uint8_t, bRm)
+{
+    IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLD, vpsrld, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
+    if (pVCpu->iem.s.uVexLength)
+    {
+        return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
+                              IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback));
+    }
+    else
+    {
+        return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
+                              IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback));
+    }
+}
+
 
 /*  Opcode VEX.0F 0x72 11/4 - invalid. */
@@ -3774 +3802 @@
 /*  Opcode VEX.0F 0x73 11/2 - invalid. */
 /** Opcode VEX.66.0F 0x73 11/2. */
-FNIEMOP_STUB_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm);
+FNIEMOP_DEF_1(iemOp_VGrp14_vpsrlq_Hx_Ux_Ib, uint8_t, bRm)
+{
+    IEMOP_MNEMONIC3(VEX_VMI_REG, VPSRLQ, vpsrlq, Hx, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
+    if (pVCpu->iem.s.uVexLength)
+    {
+        return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u256, bRm,
+                              IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback));
+    }
+    else
+    {
+        return FNIEMOP_CALL_2(iemOpCommonAvxAvx2_Hx_Ux_Ib_u128, bRm,
+                              IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback));
+    }
+}
+
 
 /** Opcode VEX.66.0F 0x73 11/3. */
@@ -4790 +4832 @@
 /*  Opcode VEX.0F 0xd1 - invalid */
 /** Opcode VEX.66.0F 0xd1 - vpsrlw Vx, Hx, W */
-FNIEMOP_STUB(iemOp_vpsrlw_Vx_Hx_W);
+FNIEMOP_DEF(iemOp_vpsrlw_Vx_Hx_W)
+{
+    IEMOP_MNEMONIC3(VEX_RVM, VPSRLW, vpsrlw, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
+    IEMOPMEDIAOPTF3_INIT_VARS(vpsrlw);
+    return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
+}
+
 /*  Opcode VEX.F3.0F 0xd1 - invalid */
 /*  Opcode VEX.F2.0F 0xd1 - invalid */
@@ -4796 +4844 @@
 /*  Opcode VEX.0F 0xd2 - invalid */
 /** Opcode VEX.66.0F 0xd2 - vpsrld Vx, Hx, Wx */
-FNIEMOP_STUB(iemOp_vpsrld_Vx_Hx_Wx);
+FNIEMOP_DEF(iemOp_vpsrld_Vx_Hx_Wx)
+{
+    IEMOP_MNEMONIC3(VEX_RVM, VPSRLD, vpsrld, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
+    IEMOPMEDIAOPTF3_INIT_VARS(vpsrld);
+    return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
+}
+
 /*  Opcode VEX.F3.0F 0xd2 - invalid */
 /*  Opcode VEX.F2.0F 0xd2 - invalid */
@@ -4802 +4856 @@
 /*  Opcode VEX.0F 0xd3 - invalid */
 /** Opcode VEX.66.0F 0xd3 - vpsrlq Vx, Hx, Wx */
-FNIEMOP_STUB(iemOp_vpsrlq_Vx_Hx_Wx);
+FNIEMOP_DEF(iemOp_vpsrlq_Vx_Hx_Wx)
+{
+    IEMOP_MNEMONIC3(VEX_RVM, VPSRLQ, vpsrlq, Vx, Hx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, 0);
+    IEMOPMEDIAOPTF3_INIT_VARS(vpsrlq);
+    return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
+}
+
 /*  Opcode VEX.F3.0F 0xd3 - invalid */
 /*  Opcode VEX.F2.0F 0xd3 - invalid */

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -3153 +3153 @@
 FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsraw_u128,     iemAImpl_vpsraw_u128_fallback;
 FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrad_u128,     iemAImpl_vpsrad_u128_fallback;
+FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlw_u128,     iemAImpl_vpsrlw_u128_fallback;
+FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrld_u128,     iemAImpl_vpsrld_u128_fallback;
+FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsrlq_u128,     iemAImpl_vpsrlq_u128_fallback;
 
 FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128,     iemAImpl_vpabsb_u128_fallback;
@@ -3229 +3232 @@
 FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsraw_u256,     iemAImpl_vpsraw_u256_fallback;
 FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrad_u256,     iemAImpl_vpsrad_u256_fallback;
+FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlw_u256,     iemAImpl_vpsrlw_u256_fallback;
+FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrld_u256,     iemAImpl_vpsrld_u256_fallback;
+FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsrlq_u256,     iemAImpl_vpsrlq_u256_fallback;
 
 FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256,     iemAImpl_vpabsb_u256_fallback;
@@ -3564 +3570 @@
 FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrad_imm_u128, iemAImpl_vpsrad_imm_u128_fallback;
 FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrad_imm_u256, iemAImpl_vpsrad_imm_u256_fallback;
+
+FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlw_imm_u128, iemAImpl_vpsrlw_imm_u128_fallback;
+FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlw_imm_u256, iemAImpl_vpsrlw_imm_u256_fallback;
+FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrld_imm_u128, iemAImpl_vpsrld_imm_u128_fallback;
+FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrld_imm_u256, iemAImpl_vpsrld_imm_u256_fallback;
+FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_vpsrlq_imm_u128, iemAImpl_vpsrlq_imm_u128_fallback;
+FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpsrlq_imm_u256, iemAImpl_vpsrlq_imm_u256_fallback;
 /** @} */