Changeset 103268 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Feb 8, 2024 6:35:31 AM (12 months ago)
- File:
-
- 1 edited
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r103266 r103268 9341 9341 { bs3CpuInstr3_psrlw_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9342 9342 { bs3CpuInstr3_psrlw_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9343 #undef VPSRL_IMPLEMENTED_YET // @todo r=blubkin These testcases are being committed before the corresponding IEM code (coming soon)9344 #if defined(VPSRL_IMPLEMENTED_YET)9345 9343 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9346 9344 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, … … 9351 9349 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9352 9350 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9353 #endif // VPSRL_IMPLEMENTED_YET9354 9351 9355 9352 { bs3CpuInstr3_psrld_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, … … 9361 9358 { bs3CpuInstr3_psrld_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9362 9359 { bs3CpuInstr3_psrld_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9363 #if defined(VPSRL_IMPLEMENTED_YET)9364 9360 { bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9365 9361 { bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, … … 9370 9366 { bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9371 9367 { bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9372 #endif // VPSRL_IMPLEMENTED_YET9373 9368 9374 9369 { bs3CpuInstr3_psrlq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, … … 9380 9375 { bs3CpuInstr3_psrlq_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9381 9376 { bs3CpuInstr3_psrlq_XMM1_012h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9382 #if defined(VPSRL_IMPLEMENTED_YET)9383 9377 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9384 9378 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, … … 9389 9383 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9390 9384 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9391 #endif // VPSRL_IMPLEMENTED_YET9392 9385 }; 9393 9386 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = … … 9401 9394 { bs3CpuInstr3_psrlw_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9402 9395 { bs3CpuInstr3_psrlw_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9403 #if defined(VPSRL_IMPLEMENTED_YET)9404 9396 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9405 9397 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, … … 9410 9402 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9411 9403 { bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9412 #endif // VPSRL_IMPLEMENTED_YET9413 9404 9414 9405 { bs3CpuInstr3_psrld_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, … … 9420 9411 { bs3CpuInstr3_psrld_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9421 9412 { bs3CpuInstr3_psrld_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9422 #if defined(VPSRL_IMPLEMENTED_YET)9423 9413 { bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9424 9414 { bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, … … 9429 9419 { bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9430 9420 { bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9431 #endif // VPSRL_IMPLEMENTED_YET9432 9421 9433 9422 { bs3CpuInstr3_psrlq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, … … 9439 9428 { bs3CpuInstr3_psrlq_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9440 9429 { bs3CpuInstr3_psrlq_XMM1_012h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9441 #if defined(VPSRL_IMPLEMENTED_YET)9442 9430 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9443 9431 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, … … 9448 9436 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9449 9437 { bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9450 #endif // VPSRL_IMPLEMENTED_YET9451 9438 }; 9452 9439 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = … … 9460 9447 { bs3CpuInstr3_psrlw_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9461 9448 { bs3CpuInstr3_psrlw_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9462 #if defined(VPSRL_IMPLEMENTED_YET)9463 9449 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues16), s_aValues16 }, 9464 9450 { bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16 }, … … 9477 9463 { bs3CpuInstr3_vpsrlw_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01 }, 9478 9464 { bs3CpuInstr3_vpsrlw_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12 }, 9479 #endif // VPSRL_IMPLEMENTED_YET9480 9465 9481 9466 { bs3CpuInstr3_psrld_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues32), s_aValues32 }, … … 9487 9472 { bs3CpuInstr3_psrld_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9488 9473 { bs3CpuInstr3_psrld_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9489 #if defined(VPSRL_IMPLEMENTED_YET)9490 9474 { bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues32), s_aValues32 }, 9491 9475 { bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32 }, … … 9504 9488 { bs3CpuInstr3_vpsrld_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01 }, 9505 9489 { bs3CpuInstr3_vpsrld_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12 }, 9506 #endif // VPSRL_IMPLEMENTED_YET9507 9490 9508 9491 { bs3CpuInstr3_psrlq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, … … 9514 9497 { bs3CpuInstr3_psrlq_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9515 9498 { bs3CpuInstr3_psrlq_XMM1_012h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9516 #if defined(VPSRL_IMPLEMENTED_YET)9517 9499 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues64), s_aValues64 }, 9518 9500 { bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, … … 9531 9513 { bs3CpuInstr3_vpsrlq_YMM8_YMM9_001h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01 }, 9532 9514 { bs3CpuInstr3_vpsrlq_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12 }, 9533 #endif // VPSRL_IMPLEMENTED_YET9534 9515 }; 9535 9516 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
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