Index: /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
===================================================================
--- /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32	(revision 103267)
+++ /trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32	(revision 103268)
@@ -9341,6 +9341,4 @@
         {  bs3CpuInstr3_psrlw_XMM1_001h_icebp_c16,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01  },
         {  bs3CpuInstr3_psrlw_XMM1_012h_icebp_c16,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12  },
-#undef VPSRL_IMPLEMENTED_YET // @todo r=blubkin These testcases are being committed before the corresponding IEM code (coming soon)
-#if defined(VPSRL_IMPLEMENTED_YET)
         {  bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c16,   255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues16), s_aValues16  },
         {  bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c16,  X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16  },
@@ -9351,5 +9349,4 @@
         {  bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp_c16,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01  },
         {  bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp_c16,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12  },
-#endif // VPSRL_IMPLEMENTED_YET
 
         {  bs3CpuInstr3_psrld_MM1_MM2_icebp_c16,           255,         RM_REG, T_MMX,       1, 1,   2, RT_ELEMENTS(s_aValues32), s_aValues32  },
@@ -9361,5 +9358,4 @@
         {  bs3CpuInstr3_psrld_XMM1_001h_icebp_c16,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01  },
         {  bs3CpuInstr3_psrld_XMM1_012h_icebp_c16,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12  },
-#if defined(VPSRL_IMPLEMENTED_YET)
         {  bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c16,   255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
         {  bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c16,  X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
@@ -9370,5 +9366,4 @@
         {  bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp_c16,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01  },
         {  bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp_c16,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12  },
-#endif // VPSRL_IMPLEMENTED_YET
 
         {  bs3CpuInstr3_psrlq_MM1_MM2_icebp_c16,           255,         RM_REG, T_MMX,       1, 1,   2, RT_ELEMENTS(s_aValues64), s_aValues64  },
@@ -9380,5 +9375,4 @@
         {  bs3CpuInstr3_psrlq_XMM1_001h_icebp_c16,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01  },
         {  bs3CpuInstr3_psrlq_XMM1_012h_icebp_c16,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12  },
-#if defined(VPSRL_IMPLEMENTED_YET)
         {  bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c16,   255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
         {  bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c16,  X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
@@ -9389,5 +9383,4 @@
         {  bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp_c16,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01  },
         {  bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp_c16,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12  },
-#endif // VPSRL_IMPLEMENTED_YET
     };
     static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
@@ -9401,5 +9394,4 @@
         {  bs3CpuInstr3_psrlw_XMM1_001h_icebp_c32,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01  },
         {  bs3CpuInstr3_psrlw_XMM1_012h_icebp_c32,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12  },
-#if defined(VPSRL_IMPLEMENTED_YET)
         {  bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c32,   255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues16), s_aValues16  },
         {  bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c32,  X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16  },
@@ -9410,5 +9402,4 @@
         {  bs3CpuInstr3_vpsrlw_YMM1_YMM2_001h_icebp_c32,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01  },
         {  bs3CpuInstr3_vpsrlw_YMM1_YMM2_012h_icebp_c32,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12  },
-#endif // VPSRL_IMPLEMENTED_YET
 
         {  bs3CpuInstr3_psrld_MM1_MM2_icebp_c32,           255,         RM_REG, T_MMX,       1, 1,   2, RT_ELEMENTS(s_aValues32), s_aValues32  },
@@ -9420,5 +9411,4 @@
         {  bs3CpuInstr3_psrld_XMM1_001h_icebp_c32,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01  },
         {  bs3CpuInstr3_psrld_XMM1_012h_icebp_c32,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12  },
-#if defined(VPSRL_IMPLEMENTED_YET)
         {  bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c32,   255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
         {  bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c32,  X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
@@ -9429,5 +9419,4 @@
         {  bs3CpuInstr3_vpsrld_YMM1_YMM2_001h_icebp_c32,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01  },
         {  bs3CpuInstr3_vpsrld_YMM1_YMM2_012h_icebp_c32,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12  },
-#endif // VPSRL_IMPLEMENTED_YET
 
         {  bs3CpuInstr3_psrlq_MM1_MM2_icebp_c32,           255,         RM_REG, T_MMX,       1, 1,   2, RT_ELEMENTS(s_aValues64), s_aValues64  },
@@ -9439,5 +9428,4 @@
         {  bs3CpuInstr3_psrlq_XMM1_001h_icebp_c32,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01  },
         {  bs3CpuInstr3_psrlq_XMM1_012h_icebp_c32,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12  },
-#if defined(VPSRL_IMPLEMENTED_YET)
         {  bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c32,   255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
         {  bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c32,  X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
@@ -9448,5 +9436,4 @@
         {  bs3CpuInstr3_vpsrlq_YMM1_YMM2_001h_icebp_c32,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01  },
         {  bs3CpuInstr3_vpsrlq_YMM1_YMM2_012h_icebp_c32,   255,         RM_REG, T_AVX2_256,  1, 2,   1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12  },
-#endif // VPSRL_IMPLEMENTED_YET
     };
     static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
@@ -9460,5 +9447,4 @@
         {  bs3CpuInstr3_psrlw_XMM1_001h_icebp_c64,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues16_01), s_aValues16_01  },
         {  bs3CpuInstr3_psrlw_XMM1_012h_icebp_c64,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues16_12), s_aValues16_12  },
-#if defined(VPSRL_IMPLEMENTED_YET)
         {  bs3CpuInstr3_vpsrlw_XMM1_XMM2_XMM3_icebp_c64,   255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues16), s_aValues16  },
         {  bs3CpuInstr3_vpsrlw_XMM1_XMM2_FSxBX_icebp_c64,  X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues16), s_aValues16  },
@@ -9477,5 +9463,4 @@
         {  bs3CpuInstr3_vpsrlw_YMM8_YMM9_001h_icebp_c64,   255,         RM_REG, T_AVX2_256,  8, 9,   1, RT_ELEMENTS(s_aValues16_01), s_aValues16_01  },
         {  bs3CpuInstr3_vpsrlw_YMM8_YMM9_012h_icebp_c64,   255,         RM_REG, T_AVX2_256,  8, 9,   1, RT_ELEMENTS(s_aValues16_12), s_aValues16_12  },
-#endif // VPSRL_IMPLEMENTED_YET
 
         {  bs3CpuInstr3_psrld_MM1_MM2_icebp_c64,           255,         RM_REG, T_MMX,       1, 1,   2, RT_ELEMENTS(s_aValues32), s_aValues32  },
@@ -9487,5 +9472,4 @@
         {  bs3CpuInstr3_psrld_XMM1_001h_icebp_c64,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues32_01), s_aValues32_01  },
         {  bs3CpuInstr3_psrld_XMM1_012h_icebp_c64,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues32_12), s_aValues32_12  },
-#if defined(VPSRL_IMPLEMENTED_YET)
         {  bs3CpuInstr3_vpsrld_XMM1_XMM2_XMM3_icebp_c64,   255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
         {  bs3CpuInstr3_vpsrld_XMM1_XMM2_FSxBX_icebp_c64,  X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
@@ -9504,5 +9488,4 @@
         {  bs3CpuInstr3_vpsrld_YMM8_YMM9_001h_icebp_c64,   255,         RM_REG, T_AVX2_256,  8, 9,   1, RT_ELEMENTS(s_aValues32_01), s_aValues32_01  },
         {  bs3CpuInstr3_vpsrld_YMM8_YMM9_012h_icebp_c64,   255,         RM_REG, T_AVX2_256,  8, 9,   1, RT_ELEMENTS(s_aValues32_12), s_aValues32_12  },
-#endif // VPSRL_IMPLEMENTED_YET
 
         {  bs3CpuInstr3_psrlq_MM1_MM2_icebp_c64,           255,         RM_REG, T_MMX,       1, 1,   2, RT_ELEMENTS(s_aValues64), s_aValues64  },
@@ -9514,5 +9497,4 @@
         {  bs3CpuInstr3_psrlq_XMM1_001h_icebp_c64,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues64_01), s_aValues64_01  },
         {  bs3CpuInstr3_psrlq_XMM1_012h_icebp_c64,         255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues64_12), s_aValues64_12  },
-#if defined(VPSRL_IMPLEMENTED_YET)
         {  bs3CpuInstr3_vpsrlq_XMM1_XMM2_XMM3_icebp_c64,   255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
         {  bs3CpuInstr3_vpsrlq_XMM1_XMM2_FSxBX_icebp_c64,  X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
@@ -9531,5 +9513,4 @@
         {  bs3CpuInstr3_vpsrlq_YMM8_YMM9_001h_icebp_c64,   255,         RM_REG, T_AVX2_256,  8, 9,   1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01  },
         {  bs3CpuInstr3_vpsrlq_YMM8_YMM9_012h_icebp_c64,   255,         RM_REG, T_AVX2_256,  8, 9,   1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12  },
-#endif // VPSRL_IMPLEMENTED_YET
     };
     static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
