Changeset 103371 in vbox
- Timestamp:
- Feb 14, 2024 8:15:01 PM (11 months ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR3/DBGFR3Flow.cpp
r101539 r103371 723 723 724 724 725 #if 0 /* unused */ 725 726 /** 726 727 * Returns the CPU mode based on the given assembler flags. … … 748 749 749 750 return enmMode; 751 } 752 #endif 753 754 755 /** 756 * Returns the (PC) pointer size based on given assembler flags. 757 * 758 * @returns 2, 4, or 8. 759 * @param pUVM The user mode VM handle. 760 * @param idCpu CPU id for disassembling. 761 * @param fFlagsDisasm The flags used for disassembling. 762 */ 763 DECLINLINE(uint32_t) dbgfR3FlowGetDisasPtrSize(PUVM pUVM, VMCPUID idCpu, uint32_t fFlagsDisasm) 764 { 765 switch (fFlagsDisasm & DBGF_DISAS_FLAGS_MODE_MASK) 766 { 767 case DBGF_DISAS_FLAGS_16BIT_MODE: 768 case DBGF_DISAS_FLAGS_16BIT_REAL_MODE: 769 return sizeof(uint16_t); 770 case DBGF_DISAS_FLAGS_32BIT_MODE: 771 return sizeof(uint32_t); 772 case DBGF_DISAS_FLAGS_64BIT_MODE: 773 return sizeof(uint64_t); 774 default: 775 AssertMsgFailed(("%#x\n", fFlagsDisasm)); 776 RT_FALL_THRU(); 777 case DBGF_DISAS_FLAGS_DEFAULT_MODE: 778 { 779 CPUMMODE const enmMode = DBGFR3CpuGetMode(pUVM, idCpu); 780 switch (enmMode) 781 { 782 case CPUMMODE_REAL: 783 return sizeof(uint16_t); 784 case CPUMMODE_PROTECTED: 785 case CPUMMODE_ARMV8_AARCH32: 786 return sizeof(uint32_t); 787 default: 788 AssertFailed(); 789 RT_FALL_THRU(); 790 case CPUMMODE_LONG: 791 case CPUMMODE_ARMV8_AARCH64: 792 return sizeof(uint64_t); 793 } 794 break; 795 } 796 } 750 797 } 751 798 … … 922 969 uint8_t idxGenRegBase, uint32_t cbPtr, PUVM pUVM, VMCPUID idCpu, bool fBranchTbl) 923 970 { 924 int rc = VINF_SUCCESS; 925 971 int rc; 926 972 if (!fBranchTbl) 927 973 { 928 union { uint16_t u16Val; uint32_t u32Val; uint64_t u64Val; } uVal; 929 rc = DBGFR3MemRead(pUVM, idCpu, pAddrBranchTgt, &uVal, cbPtr); 974 RTUINT64U uVal = { 0 }; 975 Assert(cbPtr <= sizeof(uVal)); 976 rc = DBGFR3MemRead(pUVM, idCpu, pAddrBranchTgt, &uVal, cbPtr); /* (parfait wrong about potential buffer overflow, cbPtr is known) */ 930 977 if (RT_SUCCESS(rc)) 931 978 { 932 979 DBGFADDRESS AddrTgt; 933 RTGCUINTPTR GCPtr = cbPtr == sizeof(uint64_t) 934 ? uVal. u64Val980 RTGCUINTPTR GCPtr = cbPtr == sizeof(uint64_t) /* (We could use uVal directly on little endian machines.) */ 981 ? uVal.au64[0] 935 982 : cbPtr == sizeof(uint32_t) 936 ? uVal. u32Val937 : uVal. u16Val;983 ? uVal.au32[0] 984 : uVal.au16[0]; 938 985 if (DBGFADDRESS_IS_FLAT(pAddrBranchTgt)) 939 986 DBGFR3AddrFromFlat(pUVM, &AddrTgt, GCPtr); … … 946 993 pFlowBb->AddrTarget = AddrTgt; 947 994 rc = dbgfR3FlowBbSuccessorAdd(pThis, &AddrTgt, 948 (pFlowBb->fFlags & DBGF_FLOW_BB_F_BRANCH_TABLE),995 pFlowBb->fFlags & DBGF_FLOW_BB_F_BRANCH_TABLE, 949 996 pFlowBb->pFlowBranchTbl); 950 997 } … … 977 1024 Assert(dbgfR3FlowBranchTargetIsIndirect(pDisParam)); 978 1025 979 uint32_t cbPtr = 0;980 CPUMMODE enmMode = dbgfR3FlowGetDisasCpuMode(pUVM, idCpu, fFlagsDisasm);981 982 switch (enmMode)983 {984 case CPUMMODE_REAL:985 cbPtr = sizeof(uint16_t);986 break;987 case CPUMMODE_PROTECTED:988 cbPtr = sizeof(uint32_t);989 break;990 case CPUMMODE_LONG:991 cbPtr = sizeof(uint64_t);992 break;993 default:994 AssertMsgFailed(("Invalid CPU mode %u\n", enmMode));995 }996 997 1026 if (pDisParam->fUse & DISUSE_BASE) 998 1027 { 999 uint8_t idxRegBase = pDisParam->x86.Base.idxGenReg; 1028 uint8_t const idxRegBase = pDisParam->x86.Base.idxGenReg; 1029 uint32_t const cbPtr = dbgfR3FlowGetDisasPtrSize(pUVM, idCpu, fFlagsDisasm); 1000 1030 1001 1031 /* Check that the used register size and the pointer size match. */ … … 1064 1094 Assert(pFlowBb->fFlags & DBGF_FLOW_BB_F_BRANCH_TABLE && pFlowBb->pFlowBranchTbl); 1065 1095 1066 uint32_t cbPtr = 0;1067 CPUMMODE enmMode = dbgfR3FlowGetDisasCpuMode(pUVM, idCpu, fFlagsDisasm);1068 1069 switch (enmMode)1070 {1071 case CPUMMODE_REAL:1072 cbPtr = sizeof(uint16_t);1073 break;1074 case CPUMMODE_PROTECTED:1075 cbPtr = sizeof(uint32_t);1076 break;1077 case CPUMMODE_LONG:1078 cbPtr = sizeof(uint64_t);1079 break;1080 default:1081 AssertMsgFailed(("Invalid CPU mode %u\n", enmMode));1082 }1083 1084 1096 if (pDisParam->fUse & DISUSE_BASE) 1085 1097 { 1086 uint8_t idxRegBase = pDisParam->x86.Base.idxGenReg; 1098 uint8_t const idxRegBase = pDisParam->x86.Base.idxGenReg; 1099 uint32_t const cbPtr = dbgfR3FlowGetDisasPtrSize(pUVM, idCpu, fFlagsDisasm); 1087 1100 1088 1101 /* Check that the used register size and the pointer size match. */ … … 1124 1137 */ 1125 1138 static int dbgfR3FlowBbProcess(PUVM pUVM, VMCPUID idCpu, PDBGFFLOWINT pThis, PDBGFFLOWBBINT pFlowBb, 1126 uint32_t cbDisasmMax, uint32_t fFlags)1139 uint32_t cbDisasmMax, uint32_t fFlags) 1127 1140 { 1128 1141 int rc = VINF_SUCCESS;
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