Changeset 103588 in vbox
- Timestamp:
- Feb 27, 2024 3:39:36 PM (9 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r103516 r103588 4223 4223 return iemRaiseXcptOrInt(pVCpu, 0, X86_XCPT_NM, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); 4224 4224 } 4225 4226 4227 #ifdef IEM_WITH_SETJMP 4228 /** \#NM - 07. */ 4229 DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP 4230 { 4231 iemRaiseXcptOrIntJmp(pVCpu, 0, X86_XCPT_NM, IEM_XCPT_FLAGS_T_CPU_XCPT, 0, 0); 4232 } 4233 #endif 4225 4234 4226 4235 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r103585 r103588 3105 3105 'IEM_MC_NOREF': (McBlock.parseMcGeneric, False, False, True, ), 3106 3106 'IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT': (McBlock.parseMcGeneric, True, True, False, ), 3107 'IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE': (McBlock.parseMcGeneric, True, True, False,),3107 'IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE': (McBlock.parseMcGeneric, True, True, True, ), 3108 3108 'IEM_MC_MAYBE_RAISE_FPU_XCPT': (McBlock.parseMcGeneric, True, True, False, ), 3109 3109 'IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT': (McBlock.parseMcGeneric, True, True, False, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
r103548 r103588 1719 1719 IEM_MC_ARG_CONST(RTGCPTR, GCPtrEffDst, NIL_RTGCPTR, 1); 1720 1720 IEM_MC_FETCH_GREG_U16(u16Tmp, IEM_GET_MODRM_RM(pVCpu, bRm)); 1721 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, 0, iemCImpl_lmsw, u16Tmp, GCPtrEffDst); 1721 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, RT_BIT_64(kIemNativeGstReg_Cr0), 1722 iemCImpl_lmsw, u16Tmp, GCPtrEffDst); 1722 1723 IEM_MC_END(); 1723 1724 } … … 1730 1731 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1731 1732 IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 1732 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, 0, iemCImpl_lmsw, u16Tmp, GCPtrEffDst); 1733 IEM_MC_CALL_CIMPL_2(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, RT_BIT_64(kIemNativeGstReg_Cr0), 1734 iemCImpl_lmsw, u16Tmp, GCPtrEffDst); 1733 1735 IEM_MC_END(); 1734 1736 } … … 1978 1980 IEMOP_MNEMONIC(syscall, "syscall"); /** @todo 286 LOADALL */ 1979 1981 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1982 /** @todo r=aeichner Clobbers cr0 only if this is a 286 LOADALL instruction. */ 1980 1983 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_BRANCH_INDIRECT | IEM_CIMPL_F_BRANCH_FAR | IEM_CIMPL_F_BRANCH_STACK_FAR 1981 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB, 0,1982 iemCImpl_syscall);1984 | IEM_CIMPL_F_MODE | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_END_TB, 1985 RT_BIT_64(kIemNativeGstReg_Cr0), iemCImpl_syscall); 1983 1986 } 1984 1987 … … 1989 1992 IEMOP_MNEMONIC(clts, "clts"); 1990 1993 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1991 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, 0, iemCImpl_clts);1994 IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_VMEXIT, RT_BIT_64(kIemNativeGstReg_Cr0), iemCImpl_clts); 1992 1995 } 1993 1996 … … 3381 3384 IEMOP_HLP_DONE_DECODING(); 3382 3385 3386 /** @todo r=aeichner Split this up as flushing the cr0 is excessive for crX != 0? */ 3383 3387 if (iCrReg & (2 | 8)) 3384 3388 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_VMEXIT, 0, 3385 3389 iemCImpl_mov_Cd_Rd, iCrReg, IEM_GET_MODRM_RM(pVCpu, bRm)); 3386 3390 else 3387 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, 0,3391 IEM_MC_DEFER_TO_CIMPL_2_RET(IEM_CIMPL_F_MODE | IEM_CIMPL_F_VMEXIT, RT_BIT_64(kIemNativeGstReg_Cr0), 3388 3392 iemCImpl_mov_Cd_Rd, iCrReg, IEM_GET_MODRM_RM(pVCpu, bRm)); 3389 3393 } -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
r103585 r103588 1598 1598 1599 1599 /** 1600 * Used by TB code when it wants to raise a \#NM. 1601 */ 1602 IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseNm,(PVMCPUCC pVCpu)) 1603 { 1604 iemRaiseDeviceNotAvailableJmp(pVCpu); 1605 #ifndef _MSC_VER 1606 return VINF_IEM_RAISED_XCPT; /* not reached */ 1607 #endif 1608 } 1609 1610 1611 /** 1600 1612 * Used by TB code when detecting opcode changes. 1601 1613 * @see iemThreadeFuncWorkerObsoleteTb … … 2906 2918 pReNative->Core.u64ArgVars = UINT64_MAX; 2907 2919 2908 AssertCompile(RT_ELEMENTS(pReNative->aidxUniqueLabels) == 9);2920 AssertCompile(RT_ELEMENTS(pReNative->aidxUniqueLabels) == 10); 2909 2921 pReNative->aidxUniqueLabels[0] = UINT32_MAX; 2910 2922 pReNative->aidxUniqueLabels[1] = UINT32_MAX; … … 2916 2928 pReNative->aidxUniqueLabels[7] = UINT32_MAX; 2917 2929 pReNative->aidxUniqueLabels[8] = UINT32_MAX; 2930 pReNative->aidxUniqueLabels[9] = UINT32_MAX; 2918 2931 2919 2932 /* Full host register reinit: */ … … 3485 3498 /* [kIemNativeGstReg_GprFirst + X86_GREG_x15] = */ { CPUMCTX_OFF_AND_SIZE(r15), "r15", }, 3486 3499 /* [kIemNativeGstReg_Pc] = */ { CPUMCTX_OFF_AND_SIZE(rip), "rip", }, 3487 /* [kIemNativeGstReg_ LivenessPadding17] = */ { UINT32_MAX / 4, 0, "pad17", },3500 /* [kIemNativeGstReg_Cr0] = */ { CPUMCTX_OFF_AND_SIZE(cr0), "cr0", }, 3488 3501 /* [kIemNativeGstReg_LivenessPadding18] = */ { UINT32_MAX / 4, 0, "pad18", }, 3489 3502 /* [kIemNativeGstReg_LivenessPadding19] = */ { UINT32_MAX / 4, 0, "pad19", }, … … 5768 5781 5769 5782 /** 5783 * Emits the code at the RaiseNm label. 5784 */ 5785 static uint32_t iemNativeEmitRaiseNm(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t idxReturnLabel) 5786 { 5787 uint32_t const idxLabel = iemNativeLabelFind(pReNative, kIemNativeLabelType_RaiseNm); 5788 if (idxLabel != UINT32_MAX) 5789 { 5790 iemNativeLabelDefine(pReNative, idxLabel, off); 5791 5792 /* iemNativeHlpExecRaiseNm(PVMCPUCC pVCpu) */ 5793 off = iemNativeEmitLoadGprFromGpr(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, IEMNATIVE_REG_FIXED_PVMCPU); 5794 off = iemNativeEmitCallImm(pReNative, off, (uintptr_t)iemNativeHlpExecRaiseNm); 5795 5796 /* jump back to the return sequence. */ 5797 off = iemNativeEmitJmpToLabel(pReNative, off, idxReturnLabel); 5798 } 5799 return off; 5800 } 5801 5802 5803 /** 5770 5804 * Emits the code at the ReturnWithFlags label (returns 5771 5805 * VINF_IEM_REEXEC_FINISH_WITH_FLAGS). … … 6578 6612 iemNativeVarRegisterRelease(pReNative, idxVarPc); 6579 6613 /** @todo implictly free the variable? */ 6614 6615 return off; 6616 } 6617 6618 6619 6620 /********************************************************************************************************************************* 6621 * Emitters for raising exceptions (IEM_MC_MAYBE_RAISE_XXX) * 6622 *********************************************************************************************************************************/ 6623 6624 #define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \ 6625 off = iemNativeEmitMaybeRaiseDeviceNotAvailable(pReNative, off, pCallEntry->idxInstr) 6626 6627 /** 6628 * Emits code to check if a \#NM exception should be raised. 6629 * 6630 * @returns New code buffer offset, UINT32_MAX on failure. 6631 * @param pReNative The native recompile state. 6632 * @param off The code buffer offset. 6633 */ 6634 DECL_INLINE_THROW(uint32_t) 6635 iemNativeEmitMaybeRaiseDeviceNotAvailable(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr) 6636 { 6637 /* 6638 * Make sure we don't have any outstanding guest register writes as we may 6639 * raise an #NM and all guest register must be up to date in CPUMCTX. 6640 * 6641 * @todo r=aeichner Can we postpone this to the RaiseNm path? 6642 */ 6643 off = iemNativeRegFlushPendingWrites(pReNative, off); 6644 6645 #ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING 6646 off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr)); 6647 #else 6648 RT_NOREF(idxInstr); 6649 #endif 6650 6651 /* Allocate a temporary CR0 register. */ 6652 uint8_t const idxCr0Reg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Cr0, kIemNativeGstRegUse_ReadOnly); 6653 uint8_t const idxLabelRaiseNm = iemNativeLabelCreate(pReNative, kIemNativeLabelType_RaiseNm); 6654 6655 /* 6656 * if (cr0 & (X86_CR0_EM | X86_CR0_TS) != 0) 6657 * return raisexcpt(); 6658 */ 6659 /* Test and jump. */ 6660 off = iemNativeEmitTestAnyBitsInGprAndJmpToLabelIfAnySet(pReNative, off, idxCr0Reg, X86_CR0_EM | X86_CR0_TS, idxLabelRaiseNm); 6661 6662 /* Free but don't flush the CR0 register. */ 6663 iemNativeRegFreeTmp(pReNative, idxCr0Reg); 6580 6664 6581 6665 return off; … … 13639 13723 pszName = "RaiseGp0"; 13640 13724 break; 13725 case kIemNativeLabelType_RaiseNm: 13726 pszName = "RaiseNm"; 13727 break; 13641 13728 case kIemNativeLabelType_ObsoleteTb: 13642 13729 pszName = "ObsoleteTb"; … … 14186 14273 if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_RaiseGp0)) 14187 14274 off = iemNativeEmitRaiseGp0(pReNative, off, idxReturnLabel); 14275 if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_RaiseNm)) 14276 off = iemNativeEmitRaiseNm(pReNative, off, idxReturnLabel); 14188 14277 if (pReNative->bmLabelTypes & RT_BIT_64(kIemNativeLabelType_ObsoleteTb)) 14189 14278 off = iemNativeEmitObsoleteTb(pReNative, off, idxReturnLabel); -
trunk/src/VBox/VMM/include/IEMInternal.h
r103561 r103588 5148 5148 VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT; 5149 5149 VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT; 5150 #ifdef IEM_WITH_SETJMP 5151 DECL_NO_RETURN(void) iemRaiseDeviceNotAvailableJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP; 5152 #endif 5150 5153 VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT; 5151 5154 VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT; -
trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
r103393 r103588 319 319 kIemNativeLabelType_NonZeroRetOrPassUp, 320 320 kIemNativeLabelType_RaiseGp0, 321 kIemNativeLabelType_RaiseNm, 321 322 kIemNativeLabelType_ObsoleteTb, 322 323 kIemNativeLabelType_NeedCsLimChecking, … … 686 687 kIemNativeGstReg_GprLast = kIemNativeGstReg_GprFirst + 15, 687 688 kIemNativeGstReg_Pc, 688 kIemNativeGstReg_ LivenessPadding17,689 kIemNativeGstReg_Cr0, 689 690 kIemNativeGstReg_LivenessPadding18, 690 691 kIemNativeGstReg_LivenessPadding19,
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