Changeset 103604 in vbox for trunk/include

Timestamp:

Feb 29, 2024 2:11:36 AM (15 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

161962

Message:

iprt/armv8.h: CSEL and friends. bugref:10376

Location:

trunk/include/iprt

Files:

• armv8.h (modified) (2 diffs)
• cdefs.h (modified) (1 diff)

trunk/include/iprt/armv8.h

@@ -3507 +3507 @@
     kArmv8InstrCond_Lt,                         /**< b - Signed less than. */
 
-    kArmv8InstrCond_Gt,                         /**< c - Signed less or equal. */
+    kArmv8InstrCond_Gt,                         /**< c - Signed greater than. */
     kArmv8InstrCond_Le,                         /**< d - Signed less or equal. */
 
@@ -3649 +3649 @@
 
 /**
+ * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
+ *
+ * @returns The encoded instruction.
+ * @param   uOp         Opcode bit 30.
+ * @param   uOp2        Opcode bits 11:10.
+ * @param   iRegResult  The result register. SP is NOT valid, but ZR is.
+ * @param   iRegSrc1    The 1st source register. SP is NOT valid, but ZR is.
+ * @param   iRegSrc2    The 2nd source register. SP is NOT valid, but ZR is.
+ * @param   enmCond     The condition guarding the compare.
+ * @param   f64Bit      true for 64-bit GRPs (default), false for 32-bit GPRs.
+ */
+DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
+                                                      uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
+{
+    Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
+
+    return ((uint32_t)f64Bit       << 31)
+         | (uOp                    << 30)
+         | UINT32_C(0x1a800000)
+         | (iRegSrc2               << 16)
+         | ((uint32_t)enmCond      << 12)
+         | (uOp2                   << 10)
+         | (iRegSrc1               <<  5)
+         | iRegResult;
+}
+
+
+/** A64: Encodes CSEL.
+ * @see Armv8A64MkInstrCondSelect for details. */
+DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
+                                                ARMV8INSTRCOND enmCond, bool f64Bit = true)
+{
+    return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
+}
+
+
+/** A64: Encodes CSINC.
+ * @see Armv8A64MkInstrCondSelect for details. */
+DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
+                                                 ARMV8INSTRCOND enmCond, bool f64Bit = true)
+{
+    return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
+}
+
+
+/** A64: Encodes CSET.
+ * @see Armv8A64MkInstrCondSelect for details. */
+DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
+{
+    Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
+    enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
+    return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
+}
+
+
+/** A64: Encodes CSINV.
+ * @see Armv8A64MkInstrCondSelect for details. */
+DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
+                                                 ARMV8INSTRCOND enmCond, bool f64Bit = true)
+{
+    return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
+}
+
+/** A64: Encodes CSETM.
+ * @see Armv8A64MkInstrCondSelect for details. */
+DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
+{
+    Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
+    enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
+    return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
+}
+
+
+/** A64: Encodes CSNEG.
+ * @see Armv8A64MkInstrCondSelect for details. */
+DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
+                                                 ARMV8INSTRCOND enmCond, bool f64Bit = true)
+{
+    return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
+}
+
+
+/**
  * A64: Encodes REV instruction.
  *

trunk/include/iprt/cdefs.h

@@ -197 +197 @@
   != 1
 # error "Exactly one RT_ARCH_XXX macro shall be defined"
+#endif
+
+/** @name RT_ARCH_VAL_XXX - Architectures.
+ *
+ * These are values used by RT_ARCH_VAL among others as an alternative to
+ * RT_ARCH_X86, RT_ARCH_AMD64 and friends for identifying the compiler target
+ * architecture.  Each value is a power of two (single bit), so they can be
+ * combined together to form an architecture mask if desirable.
+ *
+ * @{ */
+/**  */
+#define RT_ARCH_VAL_X86_16        0x00000001
+#define RT_ARCH_VAL_X86           0x00000002
+#define RT_ARCH_VAL_AMD64         0x00000004
+#define RT_ARCH_VAL_ARM32         0x00000010
+#define RT_ARCH_VAL_ARM64         0x00000020
+#define RT_ARCH_VAL_SPAR32        0x00000100
+#define RT_ARCH_VAL_SPAR64        0x00000200
+/** @} */
+
+
+/** @def RT_ARCH_VAL
+ * The RT_ARCH_VAL_XXX for the compiler target architecture. */
+#if defined(RT_ARCH_AMD64)
+# define RT_ARCH_VAL                    RT_ARCH_VAL_AMD64
+#elif defined(RT_ARCH_ARM64)
+# define RT_ARCH_VAL                    RT_ARCH_VAL_ARM64
+#elif defined(RT_ARCH_X86)
+# define RT_ARCH_VAL                    RT_ARCH_VAL_X86
+#elif defined(RT_ARCH_ARM32)
+# define RT_ARCH_VAL                    RT_ARCH_VAL_ARM32
+#elif defined(RT_ARCH_SPARC)
+# define RT_ARCH_VAL                    RT_ARCH_VAL_SPARC32
+#elif defined(RT_ARCH_SPARC64)
+# define RT_ARCH_VAL                    RT_ARCH_VAL_SPARC64
+#else
+# error "RT_ARCH_VAL: port me"
 #endif