Changeset 103605 in vbox for trunk/include/iprt/armv8.h
- Timestamp:
- Feb 29, 2024 2:14:14 AM (9 months ago)
- File:
-
- 1 edited
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trunk/include/iprt/armv8.h
r103604 r103605 3507 3507 kArmv8InstrCond_Lt, /**< b - Signed less than. */ 3508 3508 3509 kArmv8InstrCond_Gt, /**< c - Signed greater than. */3509 kArmv8InstrCond_Gt, /**< c - Signed less or equal. */ 3510 3510 kArmv8InstrCond_Le, /**< d - Signed less or equal. */ 3511 3511 … … 3649 3649 3650 3650 /** 3651 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)3652 *3653 * @returns The encoded instruction.3654 * @param uOp Opcode bit 30.3655 * @param uOp2 Opcode bits 11:10.3656 * @param iRegResult The result register. SP is NOT valid, but ZR is.3657 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.3658 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.3659 * @param enmCond The condition guarding the compare.3660 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.3661 */3662 DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,3663 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)3664 {3665 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);3666 3667 return ((uint32_t)f64Bit << 31)3668 | (uOp << 30)3669 | UINT32_C(0x1a800000)3670 | (iRegSrc2 << 16)3671 | ((uint32_t)enmCond << 12)3672 | (uOp2 << 10)3673 | (iRegSrc1 << 5)3674 | iRegResult;3675 }3676 3677 3678 /** A64: Encodes CSEL.3679 * @see Armv8A64MkInstrCondSelect for details. */3680 DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,3681 ARMV8INSTRCOND enmCond, bool f64Bit = true)3682 {3683 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);3684 }3685 3686 3687 /** A64: Encodes CSINC.3688 * @see Armv8A64MkInstrCondSelect for details. */3689 DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,3690 ARMV8INSTRCOND enmCond, bool f64Bit = true)3691 {3692 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);3693 }3694 3695 3696 /** A64: Encodes CSET.3697 * @see Armv8A64MkInstrCondSelect for details. */3698 DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)3699 {3700 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);3701 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);3702 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);3703 }3704 3705 3706 /** A64: Encodes CSINV.3707 * @see Armv8A64MkInstrCondSelect for details. */3708 DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,3709 ARMV8INSTRCOND enmCond, bool f64Bit = true)3710 {3711 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);3712 }3713 3714 /** A64: Encodes CSETM.3715 * @see Armv8A64MkInstrCondSelect for details. */3716 DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)3717 {3718 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);3719 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);3720 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);3721 }3722 3723 3724 /** A64: Encodes CSNEG.3725 * @see Armv8A64MkInstrCondSelect for details. */3726 DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,3727 ARMV8INSTRCOND enmCond, bool f64Bit = true)3728 {3729 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);3730 }3731 3732 3733 /**3734 3651 * A64: Encodes REV instruction. 3735 3652 *
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