VirtualBox

Changeset 103611 in vbox for trunk/src/VBox/ValidationKit


Ignore:
Timestamp:
Feb 29, 2024 11:26:29 AM (13 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
161969
Message:

ValKit/bs3-cpu-instr-2: Test the alternate reg/reg encoding of and, or, xor, add, adc, sub, sbb and cmp. Extended x86extra.mac with macros for manually encoding reg/reg instructions like this. bugref:10376

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.c

    r103603 r103611  
    7373        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r9b_r8b); \
    7474        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _al_r13b); \
     75        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _dl_r14b); \
     76        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _r8b_bl); \
    7577        /* 16-bit */ \
    7678        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r8w_cx); \
    7779        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r15w_r10w); \
     80        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _r13w_ax); \
     81        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _si_r9w); \
    7882        /* 32-bit */ \
    7983        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _eax_r8d); \
    8084        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r9d_ecx); \
    8185        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r13d_r14d); \
     86        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _r15d_esi); \
     87        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _eax_r10d); \
    8288        /* 64-bit */ \
    8389        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _rax_rbx); \
    8490        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r8_rax); \
    85         extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _rdx_r10);
     91        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _rdx_r10); \
     92        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _r15_rsi); \
     93        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _rbx_r14);
    8694
    8795# define BS3CPUINSTR2CMNBINTEST_ENTRIES_8_64BIT(a_Ins) \
    88         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _sil_dil), X86_GREG_xSI, X86_GREG_xDI   }, \
    89         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r9b_r8b), X86_GREG_x9,  X86_GREG_x8    }, \
    90         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _al_r13b), X86_GREG_xAX, X86_GREG_x13   },
     96        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _sil_dil),      X86_GREG_xSI, X86_GREG_xDI }, \
     97        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r9b_r8b),      X86_GREG_x9,  X86_GREG_x8  }, \
     98        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _al_r13b),      X86_GREG_xAX, X86_GREG_x13 },
     99# define BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8_64BIT(a_Ins) \
     100        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _dl_r14b),  X86_GREG_xDX, X86_GREG_x14 }, \
     101        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _r8b_bl),   X86_GREG_x8,  X86_GREG_xBX },
    91102# define BS3CPUINSTR2CMNBINTEST_ENTRIES_16_64BIT(a_Ins) \
    92         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r8w_cx),    X86_GREG_x8,  X86_GREG_xCX }, \
    93         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r15w_r10w), X86_GREG_x15, X86_GREG_x10 },
     103        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r8w_cx),       X86_GREG_x8,  X86_GREG_xCX }, \
     104        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r15w_r10w),    X86_GREG_x15, X86_GREG_x10 },
     105# define BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16_64BIT(a_Ins) \
     106        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _r13w_ax),  X86_GREG_x13, X86_GREG_xAX }, \
     107        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _si_r9w),   X86_GREG_xSI, X86_GREG_x9  },
    94108# define BS3CPUINSTR2CMNBINTEST_ENTRIES_32_64BIT(a_Ins) \
    95         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _eax_r8d),   X86_GREG_xAX, X86_GREG_x8  }, \
    96         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r9d_ecx),   X86_GREG_x9,  X86_GREG_xCX }, \
    97         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r13d_r14d), X86_GREG_x13, X86_GREG_x14 },
     109        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _eax_r8d),      X86_GREG_xAX, X86_GREG_x8  }, \
     110        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r9d_ecx),      X86_GREG_x9,  X86_GREG_xCX }, \
     111        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r13d_r14d),    X86_GREG_x13, X86_GREG_x14 },
     112# define BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32_64BIT(a_Ins) \
     113        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _r15d_esi), X86_GREG_x15, X86_GREG_xSI }, \
     114        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _eax_r10d), X86_GREG_xAX, X86_GREG_x10 },
    98115# define BS3CPUINSTR2CMNBINTEST_ENTRIES_64(a_Ins) \
    99         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _rax_rbx), X86_GREG_xAX, X86_GREG_xBX   }, \
    100         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r8_rax),  X86_GREG_x8,  X86_GREG_xAX   }, \
    101         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _rdx_r10), X86_GREG_xDX, X86_GREG_x10   },
     116        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _rax_rbx),      X86_GREG_xAX, X86_GREG_xBX }, \
     117        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _r8_rax),       X86_GREG_x8,  X86_GREG_xAX }, \
     118        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _rdx_r10),      X86_GREG_xDX, X86_GREG_x10 },
     119# define BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_64(a_Ins) \
     120        BS3CPUINSTR2CMNBINTEST_ENTRIES_64(a_Ins) \
     121        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _r15_rsi),  X86_GREG_x15, X86_GREG_xSI }, \
     122        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _rbx_r14),  X86_GREG_xBX, X86_GREG_x14 },
    102123# else
    103124#  define BS3CPUINSTR2_BINARY_OP_PROTO64(a_Ins)
    104 # define BS3CPUINSTR2CMNBINTEST_ENTRIES_8_64BIT(aIns)
    105 # define BS3CPUINSTR2CMNBINTEST_ENTRIES_16_64BIT(aIns)
    106 # define BS3CPUINSTR2CMNBINTEST_ENTRIES_32_64BIT(aIns)
     125#  define BS3CPUINSTR2CMNBINTEST_ENTRIES_8_64BIT(aIns)
     126#  define BS3CPUINSTR2CMNBINTEST_ENTRIES_16_64BIT(aIns)
     127#  define BS3CPUINSTR2CMNBINTEST_ENTRIES_32_64BIT(aIns)
     128#  define BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8_64BIT(aIns)
     129#  define BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16_64BIT(aIns)
     130#  define BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32_64BIT(aIns)
    107131# endif
    108132# define BS3CPUINSTR2_BINARY_OP_PROTO(a_Ins) \
    … …  
    112136        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _ch_bh); \
    113137        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _dl_ah); \
     138        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _dh_cl); \
    114139        /* 16-bit */ \
    115140        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _di_si); \
    116141        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _cx_bp); \
     142        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _bp_bx); \
    117143        /* 32-bit */ \
    118144        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _eax_ebx); \
    119145        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _ecx_ebp); \
    120         extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _edx_edi)
     146        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _edx_edi); \
     147        extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _edi_esi)
    121148
    122149# define BS3CPUINSTR2CMNBINTEST_ENTRIES_8(a_Ins) \
    123         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _al_dl), X86_GREG_xAX,    X86_GREG_xDX    }, \
    124         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _ch_bh), X86_GREG_xCX+16, X86_GREG_xBX+16 }, \
    125         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _dl_ah), X86_GREG_xDX,    X86_GREG_xAX+16 }, \
     150        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _al_dl),       X86_GREG_xAX,    X86_GREG_xDX    }, \
     151        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _ch_bh),       X86_GREG_xCX+16, X86_GREG_xBX+16 }, \
     152        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _dl_ah),       X86_GREG_xDX,    X86_GREG_xAX+16 }, \
    126153        BS3CPUINSTR2CMNBINTEST_ENTRIES_8_64BIT(a_Ins)
     154# define BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8(a_Ins) \
     155        BS3CPUINSTR2CMNBINTEST_ENTRIES_8(a_Ins) \
     156        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _dh_cl),   X86_GREG_xDX+16, X86_GREG_xCX    }, \
     157        BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8_64BIT(a_Ins)
     158
    127159# define BS3CPUINSTR2CMNBINTEST_ENTRIES_16(a_Ins) \
    128         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _di_si), X86_GREG_xDI, X86_GREG_xSI       }, \
    129         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _cx_bp), X86_GREG_xCX, X86_GREG_xBP       }, \
     160        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _di_si),       X86_GREG_xDI, X86_GREG_xSI       }, \
     161        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _cx_bp),       X86_GREG_xCX, X86_GREG_xBP       }, \
    130162        BS3CPUINSTR2CMNBINTEST_ENTRIES_16_64BIT(a_Ins)
     163# define BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16(a_Ins) \
     164        BS3CPUINSTR2CMNBINTEST_ENTRIES_16(a_Ins) \
     165        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _bp_bx),   X86_GREG_xBP, X86_GREG_xBX       }, \
     166        BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16_64BIT(a_Ins)
     167
    131168# define BS3CPUINSTR2CMNBINTEST_ENTRIES_32(a_Ins) \
    132         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _eax_ebx), X86_GREG_xAX, X86_GREG_xBX     }, \
    133         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _ecx_ebp), X86_GREG_xCX, X86_GREG_xBP     }, \
    134         { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _edx_edi), X86_GREG_xDX, X86_GREG_xDI     }, \
     169        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _eax_ebx),     X86_GREG_xAX, X86_GREG_xBX       }, \
     170        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _ecx_ebp),     X86_GREG_xCX, X86_GREG_xBP       }, \
     171        { BS3_CMN_NM(bs3CpuInstr2_ ## a_Ins ## _edx_edi),     X86_GREG_xDX, X86_GREG_xDI       }, \
     172        BS3CPUINSTR2CMNBINTEST_ENTRIES_32_64BIT(a_Ins)
     173# define BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32(a_Ins) \
     174        BS3CPUINSTR2CMNBINTEST_ENTRIES_32(a_Ins) \
     175        { BS3_CMN_NM(bs3CpuInstr2_alt_ ## a_Ins ## _edi_esi), X86_GREG_xDI, X86_GREG_xSI       }, \
    135176        BS3CPUINSTR2CMNBINTEST_ENTRIES_32_64BIT(a_Ins)
    136177
    … …  
    536577BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_and)(uint8_t bMode)
    537578{
    538     static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_8(and) };
    539     static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_16(and) };
    540     static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_32(and) };
     579    static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8(and) };
     580    static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16(and) };
     581    static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32(and) };
    541582#if ARCH_BITS == 64
    542     static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_64(and) };
     583    static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_64(and) };
    543584#endif
    544585    bs3CpuInstr2_CommonBinaryU8(bMode, s_aTests8, RT_ELEMENTS(s_aTests8), 0 /*fPassthruEfl*/,
    … …  
    558599BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_or)(uint8_t bMode)
    559600{
    560     static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_8(or) };
    561     static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_16(or) };
    562     static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_32(or) };
     601    static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8(or) };
     602    static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16(or) };
     603    static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32(or) };
    563604#if ARCH_BITS == 64
    564     static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_64(or) };
     605    static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_64(or) };
    565606#endif
    566607    bs3CpuInstr2_CommonBinaryU8(bMode, s_aTests8, RT_ELEMENTS(s_aTests8), 0 /*fPassthruEfl*/,
    … …  
    580621BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_xor)(uint8_t bMode)
    581622{
    582     static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_8(xor) };
    583     static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_16(xor) };
    584     static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_32(xor) };
     623    static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8(xor) };
     624    static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16(xor) };
     625    static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32(xor) };
    585626#if ARCH_BITS == 64
    586     static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_64(xor) };
     627    static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_64(xor) };
    587628#endif
    588629    bs3CpuInstr2_CommonBinaryU8(bMode, s_aTests8, RT_ELEMENTS(s_aTests8), 0 /*fPassthruEfl*/,
    … …  
    624665BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_add)(uint8_t bMode)
    625666{
    626     static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_8(add) };
    627     static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_16(add) };
    628     static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_32(add) };
     667    static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8(add) };
     668    static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16(add) };
     669    static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32(add) };
    629670#if ARCH_BITS == 64
    630     static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_64(add) };
     671    static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_64(add) };
    631672#endif
    632673    bs3CpuInstr2_CommonBinaryU8(bMode, s_aTests8, RT_ELEMENTS(s_aTests8), 0 /*fPassthruEfl*/,
    … …  
    646687BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_adc)(uint8_t bMode)
    647688{
    648     static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_8(adc) };
    649     static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_16(adc) };
    650     static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_32(adc) };
     689    static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8(adc) };
     690    static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16(adc) };
     691    static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32(adc) };
    651692#if ARCH_BITS == 64
    652     static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_64(adc) };
     693    static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_64(adc) };
    653694#endif
    654695    bs3CpuInstr2_CommonBinaryU8(bMode, s_aTests8, RT_ELEMENTS(s_aTests8), 0 /*fPassthruEfl*/,
    … …  
    668709BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_sub)(uint8_t bMode)
    669710{
    670     static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_8(sub) };
    671     static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_16(sub) };
    672     static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_32(sub) };
     711    static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8(sub) };
     712    static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16(sub) };
     713    static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32(sub) };
    673714#if ARCH_BITS == 64
    674     static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_64(sub) };
     715    static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_64(sub) };
    675716#endif
    676717    bs3CpuInstr2_CommonBinaryU8(bMode, s_aTests8, RT_ELEMENTS(s_aTests8), 0 /*fPassthruEfl*/,
    … …  
    690731BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_sbb)(uint8_t bMode)
    691732{
    692     static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_8(sbb) };
    693     static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_16(sbb) };
    694     static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_32(sbb) };
     733    static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8(sbb) };
     734    static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16(sbb) };
     735    static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32(sbb) };
    695736#if ARCH_BITS == 64
    696     static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_64(sbb) };
     737    static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_64(sbb) };
    697738#endif
    698739    bs3CpuInstr2_CommonBinaryU8(bMode, s_aTests8, RT_ELEMENTS(s_aTests8), 0 /*fPassthruEfl*/,
    … …  
    712753BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_cmp)(uint8_t bMode)
    713754{
    714     static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_8(cmp) };
    715     static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_16(cmp) };
    716     static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_32(cmp) };
     755    static const BS3CPUINSTR2CMNBINTEST s_aTests8[]  = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_8(cmp) };
     756    static const BS3CPUINSTR2CMNBINTEST s_aTests16[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_16(cmp) };
     757    static const BS3CPUINSTR2CMNBINTEST s_aTests32[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_32(cmp) };
    717758#if ARCH_BITS == 64
    718     static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_64(cmp) };
     759    static const BS3CPUINSTR2CMNBINTEST s_aTests64[] = { BS3CPUINSTR2CMNBINTEST_ENTRIES_ALT_64(cmp) };
    719760#endif
    720761    bs3CpuInstr2_CommonBinaryU8(bMode, s_aTests8, RT_ELEMENTS(s_aTests8), 0 /*fPassthruEfl*/,

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.mac

    r103602 r103611  
    7575%endif
    7676
     77;;
     78; @param 1      The instruction menmonic.
     79; @param 2      Whether there is an 8-bit form of the instruction (1) or not 0.
     80; @param 3      Whether there are alternative forms of the instruction.
    7781%ifndef  BS3CPUINSTR2_BINARY_OP_DEFINED
    7882 %define BS3CPUINSTR2_BINARY_OP_DEFINED
    79  %macro  BS3CPUINSTR2_BINARY_OP 2
     83 %macro  BS3CPUINSTR2_BINARY_OP 3
    8084  %if %2 != 0
    8185        ; 8-bit
    … …  
    8387        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ch  %+ _bh,     %1 ch, bh
    8488        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _dl  %+ _ah,     %1 dl, ah
     89   %if %3 != 0
     90        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _dh %+ _cl, ALT_INSTRUCTION8_ %+ %1 dh, cl
     91   %endif
    8592   %ifdef TMPL_64BIT
    8693        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _sil  %+ _dil,   %1 sil, dil
    8794        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9b  %+ _r8b,   %1 r9b, r8b
    8895        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _al   %+ _r13b,  %1 al, r13b
     96    %if %3 != 0
     97        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _dl %+ _r14b, ALT_INSTRUCTION8_ %+ %1 dl, r14b
     98        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r8b %+ _bl,  ALT_INSTRUCTION8_ %+ %1 r8b, bl
     99    %endif
    89100   %endif
    90101  %endif
    … …  
    92103        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _di  %+ _si,     %1 di, si
    93104        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _cx  %+ _bp,     %1 cx, bp
     105  %if %3 != 0
     106        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _bp %+ _bx, ALT_INSTRUCTION16_ %+ %1 bp, bx
     107  %endif
    94108  %ifdef TMPL_64BIT
    95109        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8w  %+ _cx,    %1 r8w, cx
    96110        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r15w %+ _r10w,  %1 r15w, r10w
     111   %if %3 != 0
     112        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r13w %+ _ax, ALT_INSTRUCTION16_ %+ %1 r13w, ax
     113        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _si %+ _r9w,  ALT_INSTRUCTION16_ %+ %1 si, r9w
     114   %endif
    97115  %endif
    98116        ; 32-bit
    … …  
    100118        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _ecx %+ _ebp,    %1 ecx, ebp
    101119        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _edx %+ _edi,    %1 edx, edi
     120  %if %3 != 0
     121        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _edi %+ _esi, ALT_INSTRUCTION32_ %+ %1 edi, esi
     122  %endif
    102123  %ifdef TMPL_64BIT
    103124        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _eax %+ _r8d,    %1 eax, r8d
    104125        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r9d %+ _ecx,    %1 r9d, ecx
    105126        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r13d %+ _r14d,  %1 r13d, r14d
     127   %if %3 != 0
     128        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r15d %+ _esi, ALT_INSTRUCTION32_ %+ %1 r15d, esi
     129        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _eax %+ _r10d, ALT_INSTRUCTION32_ %+ %1 eax, r10d
     130   %endif
    106131  %endif
    107132        ; 64-bit
    … …  
    110135        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _r8  %+ _rax,    %1 r8, rax
    111136        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_ %+ %1 %+ _rdx %+ _r10,    %1 rdx, r10
     137    %if %3 != 0
     138        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _r15 %+ _rsi, ALT_INSTRUCTION64_ %+ %1 r15, rsi
     139        BS3CPUINSTR2_EMIT_INSTR_UD2 bs3CpuInstr2_alt_ %+ %1 %+ _rbx %+ _r14, ALT_INSTRUCTION64_ %+ %1 rbx, r14
     140    %endif
    112141  %endif
    113142 %endmacro
    … …  
    127156%ifdef BS3_INSTANTIATING_CMN
    128157
    129 BS3CPUINSTR2_BINARY_OP and,  1
    130 BS3CPUINSTR2_BINARY_OP or,   1
    131 BS3CPUINSTR2_BINARY_OP xor,  1
    132 BS3CPUINSTR2_BINARY_OP test, 1
    133 
    134 BS3CPUINSTR2_BINARY_OP add,  1
    135 BS3CPUINSTR2_BINARY_OP adc,  1
    136 BS3CPUINSTR2_BINARY_OP sub,  1
    137 BS3CPUINSTR2_BINARY_OP sbb,  1
    138 BS3CPUINSTR2_BINARY_OP cmp,  1
    139 
    140 BS3CPUINSTR2_BINARY_OP bt,   0
    141 BS3CPUINSTR2_BINARY_OP btc,  0
    142 BS3CPUINSTR2_BINARY_OP btr,  0
    143 BS3CPUINSTR2_BINARY_OP bts,  0
     158%ifndef ALT_INSTRUCTION_MACROS_DEFINED
     159 %define ALT_INSTRUCTION_MACROS_DEFINED
     160 %macro ALT_INSTRUCTION8_REG_RM 3+
     161        X86_MKOP_REX8 %1, %2
     162        db      %3
     163        X86_MKOP_MODRM8 X86_MOD_REG, %1, %2
     164 %endmacro
     165
     166 %macro ALT_INSTRUCTION16_REG_RM 3+
     167  %if TMPL_BITS != 16
     168        db      X86_OP_PRF_SIZE_OP
     169  %endif
     170        X86_MKOP_REX16 %1, %2
     171        db      %3
     172        X86_MKOP_MODRM16 X86_MOD_REG, %1, %2
     173 %endmacro
     174
     175 %macro ALT_INSTRUCTION32_REG_RM 3+
     176  %if TMPL_BITS == 16
     177        db      X86_OP_PRF_SIZE_OP
     178  %endif
     179        X86_MKOP_REX32 %1, %2
     180        db      %3
     181        X86_MKOP_MODRM32 X86_MOD_REG, %1, %2
     182 %endmacro
     183
     184 %macro ALT_INSTRUCTION64_REG_RM 3+
     185        X86_MKOP_REX64 %1, %2
     186        db      %3
     187        X86_MKOP_MODRM64 X86_MOD_REG, %1, %2
     188 %endmacro
     189
     190 ; nasm v2.16.02rc1 encodes the 20h and 21h variants (AND rm,reg)
     191 %macro ALT_INSTRUCTION8_and 2
     192       ALT_INSTRUCTION8_REG_RM %1, %2, 22h
     193 %endmacro
     194 %macro ALT_INSTRUCTION16_and 2
     195       ALT_INSTRUCTION16_REG_RM %1, %2, 23h
     196 %endmacro
     197 %macro ALT_INSTRUCTION32_and 2
     198       ALT_INSTRUCTION32_REG_RM %1, %2, 23h
     199 %endmacro
     200 %macro ALT_INSTRUCTION64_and 2
     201       ALT_INSTRUCTION64_REG_RM %1, %2, 23h
     202 %endmacro
     203
     204 ; nasm v2.16.02rc1 encodes the 08h and 09h variants (OR rm,reg)
     205 %macro ALT_INSTRUCTION8_or 2
     206       ALT_INSTRUCTION8_REG_RM %1, %2, 0ah
     207 %endmacro
     208 %macro ALT_INSTRUCTION16_or 2
     209       ALT_INSTRUCTION16_REG_RM %1, %2, 0bh
     210 %endmacro
     211 %macro ALT_INSTRUCTION32_or 2
     212       ALT_INSTRUCTION32_REG_RM %1, %2, 0bh
     213 %endmacro
     214 %macro ALT_INSTRUCTION64_or 2
     215       ALT_INSTRUCTION64_REG_RM %1, %2, 0bh
     216 %endmacro
     217
     218 ; nasm v2.16.02rc1 encodes the 30h and 31h variants (XOR rm,reg)
     219 %macro ALT_INSTRUCTION8_xor 2
     220       ALT_INSTRUCTION8_REG_RM %1, %2, 32h
     221 %endmacro
     222 %macro ALT_INSTRUCTION16_xor 2
     223       ALT_INSTRUCTION16_REG_RM %1, %2, 33h
     224 %endmacro
     225 %macro ALT_INSTRUCTION32_xor 2
     226       ALT_INSTRUCTION32_REG_RM %1, %2, 33h
     227 %endmacro
     228 %macro ALT_INSTRUCTION64_xor 2
     229       ALT_INSTRUCTION64_REG_RM %1, %2, 33h
     230 %endmacro
     231
     232 ; nasm v2.16.02rc1 encodes the 00h and 01h variants (ADD rm,reg)
     233 %macro ALT_INSTRUCTION8_add 2
     234       ALT_INSTRUCTION8_REG_RM %1, %2, 02h
     235 %endmacro
     236 %macro ALT_INSTRUCTION16_add 2
     237       ALT_INSTRUCTION16_REG_RM %1, %2, 03h
     238 %endmacro
     239 %macro ALT_INSTRUCTION32_add 2
     240       ALT_INSTRUCTION32_REG_RM %1, %2, 03h
     241 %endmacro
     242 %macro ALT_INSTRUCTION64_add 2
     243       ALT_INSTRUCTION64_REG_RM %1, %2, 03h
     244 %endmacro
     245
     246 ; nasm v2.16.02rc1 encodes the 10h and 11h variants (ADC rm,reg)
     247 %macro ALT_INSTRUCTION8_adc 2
     248       ALT_INSTRUCTION8_REG_RM %1, %2, 12h
     249 %endmacro
     250 %macro ALT_INSTRUCTION16_adc 2
     251       ALT_INSTRUCTION16_REG_RM %1, %2, 13h
     252 %endmacro
     253 %macro ALT_INSTRUCTION32_adc 2
     254       ALT_INSTRUCTION32_REG_RM %1, %2, 13h
     255 %endmacro
     256 %macro ALT_INSTRUCTION64_adc 2
     257       ALT_INSTRUCTION64_REG_RM %1, %2, 13h
     258 %endmacro
     259
     260 ; nasm v2.16.02rc1 encodes the 28h and 29h variants (SUB rm,reg)
     261 %macro ALT_INSTRUCTION8_sub 2
     262       ALT_INSTRUCTION8_REG_RM %1, %2, 2ah
     263 %endmacro
     264 %macro ALT_INSTRUCTION16_sub 2
     265       ALT_INSTRUCTION16_REG_RM %1, %2, 2bh
     266 %endmacro
     267 %macro ALT_INSTRUCTION32_sub 2
     268       ALT_INSTRUCTION32_REG_RM %1, %2, 2bh
     269 %endmacro
     270 %macro ALT_INSTRUCTION64_sub 2
     271       ALT_INSTRUCTION64_REG_RM %1, %2, 2bh
     272 %endmacro
     273
     274 ; nasm v2.16.02rc1 encodes the 18h and 19h variants (SBB rm,reg)
     275 %macro ALT_INSTRUCTION8_sbb 2
     276       ALT_INSTRUCTION8_REG_RM %1, %2, 1ah
     277 %endmacro
     278 %macro ALT_INSTRUCTION16_sbb 2
     279       ALT_INSTRUCTION16_REG_RM %1, %2, 1bh
     280 %endmacro
     281 %macro ALT_INSTRUCTION32_sbb 2
     282       ALT_INSTRUCTION32_REG_RM %1, %2, 1bh
     283 %endmacro
     284 %macro ALT_INSTRUCTION64_sbb 2
     285       ALT_INSTRUCTION64_REG_RM %1, %2, 1bh
     286 %endmacro
     287
     288 ; nasm v2.16.02rc1 encodes the 38h and 39h variants (CMP rm,reg)
     289 %macro ALT_INSTRUCTION8_cmp 2
     290       ALT_INSTRUCTION8_REG_RM %1, %2, 3ah
     291 %endmacro
     292 %macro ALT_INSTRUCTION16_cmp 2
     293       ALT_INSTRUCTION16_REG_RM %1, %2, 3bh
     294 %endmacro
     295 %macro ALT_INSTRUCTION32_cmp 2
     296       ALT_INSTRUCTION32_REG_RM %1, %2, 3bh
     297 %endmacro
     298 %macro ALT_INSTRUCTION64_cmp 2
     299       ALT_INSTRUCTION64_REG_RM %1, %2, 3bh
     300 %endmacro
     301
     302%endif ; !ALT_INSTRUCTION_MACROS_DEFINED
     303
     304BS3CPUINSTR2_BINARY_OP and,  1, 1
     305BS3CPUINSTR2_BINARY_OP or,   1, 1
     306BS3CPUINSTR2_BINARY_OP xor,  1, 1
     307BS3CPUINSTR2_BINARY_OP test, 1, 0
     308
     309BS3CPUINSTR2_BINARY_OP add,  1, 1
     310BS3CPUINSTR2_BINARY_OP adc,  1, 1
     311BS3CPUINSTR2_BINARY_OP sub,  1, 1
     312BS3CPUINSTR2_BINARY_OP sbb,  1, 1
     313BS3CPUINSTR2_BINARY_OP cmp,  1, 1
     314
     315BS3CPUINSTR2_BINARY_OP bt,   0, 0
     316BS3CPUINSTR2_BINARY_OP btc,  0, 0
     317BS3CPUINSTR2_BINARY_OP btr,  0, 0
     318BS3CPUINSTR2_BINARY_OP bts,  0, 0
    144319
    145320
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