Changeset 103635 in vbox for trunk/src/VBox

Timestamp:

Mar 1, 2024 2:43:15 PM (11 months ago)

Author:

vboxsync

Message:

VMM/IEM: Emit native code for 64-bit and 16-bit xor reg/reg variants as well. bugref:10376

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAllInstOneByte.cpp.h (modified) (2 diffs)
• IEMAllN8veRecompiler.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h

@@ -1556 +1556 @@
                 IEM_MC_BEGIN(3, 0, 0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-                IEM_MC_ARG(uint16_t *, pu16Dst, 0);
                 IEM_MC_ARG(uint16_t,   u16Src,  1);
-                IEM_MC_ARG(uint32_t *, pEFlags, 2);
                 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-                IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm));
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u16, pu16Dst, u16Src, pEFlags);
+                IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) {
+                    IEM_MC_LOCAL(uint16_t, u16Dst);
+                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm));
+                    /// @todo IEM_MC_LOCAL_EFLAGS(uEFlags);
+                    IEM_MC_LOCAL(uint32_t, uEFlags);
+                    IEM_MC_FETCH_EFLAGS(uEFlags);
+                    IEM_MC_NATIVE_EMIT_4(iemNativeEmit_xor_r_r_efl, u16Dst, u16Src, uEFlags, 16);
+                    IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst);
+                    IEM_MC_COMMIT_EFLAGS(uEFlags);
+                } IEM_MC_NATIVE_ELSE() {
+                    IEM_MC_ARG(uint16_t *, pu16Dst, 0);
+                    IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm));
+                    IEM_MC_ARG(uint32_t *, pEFlags, 2);
+                    IEM_MC_REF_EFLAGS(pEFlags);
+                    IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u16, pu16Dst, u16Src, pEFlags);
+                } IEM_MC_NATIVE_ENDIF();
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
                 IEM_MC_END();
@@ -1596 +1607 @@
                 IEM_MC_BEGIN(3, 0, IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-                IEM_MC_ARG(uint64_t *, pu64Dst, 0);
                 IEM_MC_ARG(uint64_t,   u64Src,  1);
-                IEM_MC_ARG(uint32_t *, pEFlags, 2);
-
                 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-                IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm));
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u64, pu64Dst, u64Src, pEFlags);
-
+                IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) {
+                    IEM_MC_LOCAL(uint64_t, u64Dst);
+                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm));
+                    /// @todo IEM_MC_LOCAL_EFLAGS(uEFlags);
+                    IEM_MC_LOCAL(uint32_t, uEFlags);
+                    IEM_MC_FETCH_EFLAGS(uEFlags);
+                    IEM_MC_NATIVE_EMIT_4(iemNativeEmit_xor_r_r_efl, u64Dst, u64Src, uEFlags, 64);
+                    IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst);
+                    IEM_MC_COMMIT_EFLAGS(uEFlags);
+                } IEM_MC_NATIVE_ELSE() {
+                    IEM_MC_ARG(uint64_t *, pu64Dst, 0);
+                    IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm));
+                    IEM_MC_ARG(uint32_t *, pEFlags, 2);
+                    IEM_MC_REF_EFLAGS(pEFlags);
+                    IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xor_u64, pu64Dst, u64Src, pEFlags);
+                } IEM_MC_NATIVE_ENDIF();
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
                 IEM_MC_END();

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp

@@ -6246 +6246 @@
         else
             off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, idxRegResult, ARMV8_A64_REG_XZR);
-# if 0
-        off = iemNativeEmitLoadGpr32ImmEx(pCodeBuf, off, idxTmpReg, X86_EFL_ZF);
-        pCodeBuf[off++] = Armv8A64MkInstrCSel(idxTmpReg, idxTmpReg, ARMV8_A64_REG_XZR, kArmv8InstrCond_Eq, false /*f64Bit*/);
-        pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegEfl, idxRegEfl, idxTmpReg, false /*f64Bit*/);
-# else
         pCodeBuf[off++] = Armv8A64MkInstrCSet(idxTmpReg, kArmv8InstrCond_Eq, false /*f64Bit*/);
         pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegEfl, idxRegEfl, idxTmpReg, false /*f64Bit*/, X86_EFL_ZF_BIT);
-# endif
 
         /* Calculate signed: We could use the native SF flag, but it's just as simple to calculate it by shifting. */
         pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxRegResult, cOpBits - 1, cOpBits > 32 /*f64Bit*/);
+# if 0 /* BFI and ORR hsould have the same performance characteristics, so use BFI like we'll have to do for SUB/ADD/++. */
         pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegEfl, idxRegEfl, idxTmpReg, false /*f64Bit*/, X86_EFL_SF_BIT);
+# else
+        pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_SF_BIT, 1, false /*f64Bit*/);
+# endif
 
         /* Calculate 8-bit parity of the result. */
@@ -6288 +6286 @@
      * The XOR instruction will clear OF, CF and AF (latter is off undefined),
      * so we don't need the initial destination value.
+     *
+     * On AMD64 we must use the correctly sizeed XOR instructions to get the
+     * right EFLAGS.SF value, while the rest will just lump 16-bit and 8-bit
+     * in the 32-bit ones.
      */
     uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
     uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/);
     //off = iemNativeEmitBrk(pReNative, off, 0x2222);
-    if (cOpBits > 32)
-        off = iemNativeEmitXorGprByGpr(pReNative, off, idxRegDst, idxRegSrc);
-    else
-        off = iemNativeEmitXorGpr32ByGpr32(pReNative, off, idxRegDst, idxRegSrc);
+    switch (cOpBits)
+    {
+        case 32:
+#ifndef RT_ARCH_AMD64
+        case 16:
+        case 8:
+#endif
+            off = iemNativeEmitXorGpr32ByGpr32(pReNative, off, idxRegDst, idxRegSrc);
+            break;
+
+        default: AssertFailed(); RT_FALL_THRU();
+        case 64:
+            off = iemNativeEmitXorGprByGpr(pReNative, off, idxRegDst, idxRegSrc);
+            break;
+
+#ifdef RT_ARCH_AMD64
+        case 16:
+        {
+            PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
+            pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+            off = iemNativeEmitXorGpr32ByGpr32(pReNative, off, idxRegDst, idxRegSrc);
+            break;
+        }
+
+        case 8:
+        {
+            PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
+            if (idxRegDst >= 8 || idxRegSrc >= 8)
+                pCodeBuf[off++] = (idxRegDst >= 8 ? X86_OP_REX_R : 0) | (idxRegSrc >= 8 ? X86_OP_REX_B : 0);
+            else if (idxRegDst >= 4 || idxRegSrc >= 4)
+                pCodeBuf[off++] = X86_OP_REX;
+            pCodeBuf[off++] = 0x32;
+            pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxRegDst & 7, idxRegSrc & 7);
+            IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+            break;
+        }
+#endif
+    }
     iemNativeVarRegisterRelease(pReNative, idxVarSrc);