Changeset 103639 in vbox

Timestamp:

Mar 1, 2024 8:56:46 PM (9 months ago)

Author:

vboxsync

Message:

VMM/IEM: Moved iemNativeEmit_xor_r_r_efl and iemNativeEmitEFlagsForLogical into a separate file under the new target-x86 subdir. [missing file] bugref:10376

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp

@@ -6188 +6188 @@
 
 
-/**
- * This is an implementation of IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL
- * and friends.
- *
- * It takes liveness stuff into account.
- */
-DECL_INLINE_THROW(uint32_t)
-iemNativeEmitEFlagsForLogical(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarEfl,
-                              uint8_t cOpBits, uint8_t idxRegResult)
-{
-#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
-    if (1) /** @todo check if all bits are clobbered. */
-#endif
-    {
-#ifdef RT_ARCH_AMD64
-        /*
-         * Collect flags and merge them with eflags.
-         */
-        /** @todo we could alternatively use SAHF here when host rax is free since,
-         *        OF is cleared. */
-        PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
-        /* pushf - do this before any reg allocations as they may emit instructions too. */
-        pCodeBuf[off++] = 0x9c;
-
-        uint8_t const idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /*fInitialized*/);
-        uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
-        pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2 + 7 + 7 + 3);
-        /* pop   tmp */
-        if (idxTmpReg >= 8)
-            pCodeBuf[off++] = X86_OP_REX_B;
-        pCodeBuf[off++] = 0x58 + (idxTmpReg & 7);
-        /* and  tmp, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF */
-        off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxTmpReg, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF);
-        /* Clear the status bits in EFLs. */
-        off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegEfl, ~X86_EFL_STATUS_BITS);
-        /* OR in the flags we collected. */
-        off = iemNativeEmitOrGpr32ByGprEx(pCodeBuf, off, idxRegEfl, idxTmpReg);
-        iemNativeVarRegisterRelease(pReNative, idxVarEfl);
-        iemNativeRegFreeTmp(pReNative, idxTmpReg);
-        RT_NOREF(cOpBits, idxRegResult);
-
-#elif defined(RT_ARCH_ARM64)
-        /*
-         * Calculate flags.
-         */
-        uint8_t const         idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /*fInitialized*/);
-        uint8_t const         idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
-        PIEMNATIVEINSTR const pCodeBuf  = iemNativeInstrBufEnsure(pReNative, off, 15);
-
-        /* Clear the status bits. ~0x8D5 (or ~0x8FD) can't be AND immediate, so use idxTmpReg for constant. */
-        off = iemNativeEmitLoadGpr32ImmEx(pCodeBuf, off, idxTmpReg, ~X86_EFL_STATUS_BITS);
-        off = iemNativeEmitAndGpr32ByGpr32Ex(pCodeBuf, off, idxRegEfl, idxTmpReg);
-
-        /* Calculate zero: mov tmp, zf; cmp result,zero; csel.eq tmp,tmp,wxr */
-        if (cOpBits > 32)
-            off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, idxRegResult, ARMV8_A64_REG_XZR);
-        else
-            off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, idxRegResult, ARMV8_A64_REG_XZR);
-        pCodeBuf[off++] = Armv8A64MkInstrCSet(idxTmpReg, kArmv8InstrCond_Eq, false /*f64Bit*/);
-        pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegEfl, idxRegEfl, idxTmpReg, false /*f64Bit*/, X86_EFL_ZF_BIT);
-
-        /* Calculate signed: We could use the native SF flag, but it's just as simple to calculate it by shifting. */
-        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxRegResult, cOpBits - 1, cOpBits > 32 /*f64Bit*/);
-# if 0 /* BFI and ORR hsould have the same performance characteristics, so use BFI like we'll have to do for SUB/ADD/++. */
-        pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegEfl, idxRegEfl, idxTmpReg, false /*f64Bit*/, X86_EFL_SF_BIT);
-# else
-        pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_SF_BIT, 1, false /*f64Bit*/);
-# endif
-
-        /* Calculate 8-bit parity of the result. */
-        pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxRegResult, idxRegResult, false /*f64Bit*/,
-                                             4 /*offShift6*/, kArmv8A64InstrShift_Lsr);
-        pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg,    idxTmpReg,    false /*f64Bit*/,
-                                             2 /*offShift6*/, kArmv8A64InstrShift_Lsr);
-        pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg,    idxTmpReg,    false /*f64Bit*/,
-                                             1 /*offShift6*/, kArmv8A64InstrShift_Lsr);
-        Assert(Armv8A64ConvertImmRImmS2Mask32(0, 0) == 1);
-        pCodeBuf[off++] = Armv8A64MkInstrEorImm(idxTmpReg, idxTmpReg, 0, 0, false /*f64Bit*/);
-        pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_PF_BIT, 1,  false /*f64Bit*/);
-
-        iemNativeVarRegisterRelease(pReNative, idxVarEfl);
-        iemNativeRegFreeTmp(pReNative, idxTmpReg);
-#else
-# error "port me"
-#endif
-        IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
-    }
-    return off;
-}
-
-/** @todo move this somewhere else ... */
-DECL_INLINE_THROW(uint32_t)
-iemNativeEmit_xor_r_r_efl(PIEMRECOMPILERSTATE pReNative, uint32_t off,
-                          uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
-{
-    /*
-     * The XOR instruction will clear OF, CF and AF (latter is off undefined),
-     * so we don't need the initial destination value.
-     *
-     * On AMD64 we must use the correctly sizeed XOR instructions to get the
-     * right EFLAGS.SF value, while the rest will just lump 16-bit and 8-bit
-     * in the 32-bit ones.
-     */
-    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
-    uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/);
-    //off = iemNativeEmitBrk(pReNative, off, 0x2222);
-    switch (cOpBits)
-    {
-        case 32:
-#ifndef RT_ARCH_AMD64
-        case 16:
-        case 8:
-#endif
-            off = iemNativeEmitXorGpr32ByGpr32(pReNative, off, idxRegDst, idxRegSrc);
-            break;
-
-        default: AssertFailed(); RT_FALL_THRU();
-        case 64:
-            off = iemNativeEmitXorGprByGpr(pReNative, off, idxRegDst, idxRegSrc);
-            break;
-
-#ifdef RT_ARCH_AMD64
-        case 16:
-        {
-            PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
-            pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
-            off = iemNativeEmitXorGpr32ByGpr32(pReNative, off, idxRegDst, idxRegSrc);
-            break;
-        }
-
-        case 8:
-        {
-            PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
-            if (idxRegDst >= 8 || idxRegSrc >= 8)
-                pCodeBuf[off++] = (idxRegDst >= 8 ? X86_OP_REX_R : 0) | (idxRegSrc >= 8 ? X86_OP_REX_B : 0);
-            else if (idxRegDst >= 4 || idxRegSrc >= 4)
-                pCodeBuf[off++] = X86_OP_REX;
-            pCodeBuf[off++] = 0x32;
-            pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxRegDst & 7, idxRegSrc & 7);
-            IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
-            break;
-        }
-#endif
-    }
-    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
-
-    off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
-    iemNativeVarRegisterRelease(pReNative, idxVarDst);
-    return off;
-}
-
 
 /*********************************************************************************************************************************
@@ -13637 +13486 @@
 *********************************************************************************************************************************/
 
+/*
+ * Include instruction emitters.
+ */
+#include "target-x86/IEMAllN8veEmit-x86.h"
 
 /*