Changeset 10364 in vbox
- Timestamp:
- Jul 8, 2008 1:09:13 PM (17 years ago)
- svn:sync-xref-src-repo-rev:
- 33001
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp
r10363 r10364 248 248 { 249 249 Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX); 250 const unsigned off = GCPhysFault & PAGE_OFFSET_MASK; 251 252 LogFlow(("pgmPoolMonitorChainChanging: %VGv phys=%VGp kind=%d\n", pvAddress, GCPhysFault, pPage->enmKind)); 250 const unsigned off = GCPhysFault & PAGE_OFFSET_MASK; 251 const unsigned cbWrite = pgmPoolDisasWriteSize(pCpu); 252 253 LogFlow(("pgmPoolMonitorChainChanging: %VGv phys=%VGp kind=%d cbWrite=%d\n", pvAddress, GCPhysFault, pPage->enmKind, cbWrite)); 253 254 254 255 for (;;) … … 322 323 if ( pCpu 323 324 && (off & 7) 324 && (off & 7) + pgmPoolDisasWriteSize(pCpu)> sizeof(X86PTEPAE))325 && (off & 7) + cbWrite > sizeof(X86PTEPAE)) 325 326 { 326 const unsigned iShw2 = (off + pgmPoolDisasWriteSize(pCpu)- 1) / sizeof(X86PTEPAE);327 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE); 327 328 AssertReturnVoid(iShw2 < ELEMENTS(uShw.pPTPae->a)); 328 329 … … 352 353 else if ( pCpu 353 354 && (off & 3) 354 && (off & 3) + pgmPoolDisasWriteSize(pCpu)> sizeof(X86PTE))355 && (off & 3) + cbWrite > sizeof(X86PTE)) 355 356 { 356 const unsigned iShw2 = (off + pgmPoolDisasWriteSize(pCpu)- 1) / sizeof(X86PTE);357 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE); 357 358 if ( iShw2 != iShw 358 359 && iShw2 < ELEMENTS(uShw.pPD->a) … … 393 394 else if ( pCpu 394 395 && (off & 3) 395 && (off & 3) + pgmPoolDisasWriteSize(pCpu)> 4)396 && (off & 3) + cbWrite > 4) 396 397 { 397 398 const unsigned iShw2 = iShw + 2; … … 451 452 if ( pCpu 452 453 && (off & 7) 453 && (off & 7) + pgmPoolDisasWriteSize(pCpu)> sizeof(X86PDEPAE))454 && (off & 7) + cbWrite > sizeof(X86PDEPAE)) 454 455 { 455 const unsigned iShw2 = (off + pgmPoolDisasWriteSize(pCpu)- 1) / sizeof(X86PDEPAE);456 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE); 456 457 AssertReturnVoid(iShw2 < ELEMENTS(uShw.pPDPae->a)); 457 458 … … 498 499 else if ( pCpu 499 500 && (off & 7) 500 && (off & 7) + pgmPoolDisasWriteSize(pCpu)> sizeof(X86PDPE))501 && (off & 7) + cbWrite > sizeof(X86PDPE)) 501 502 { 502 const unsigned iShw2 = (off + pgmPoolDisasWriteSize(pCpu)- 1) / sizeof(X86PDPE);503 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE); 503 504 if ( iShw2 != iShw 504 505 && iShw2 < X86_PG_PAE_PDPE_ENTRIES … … 541 542 if ( pCpu 542 543 && (off & 7) 543 && (off & 7) + pgmPoolDisasWriteSize(pCpu)> sizeof(X86PDEPAE))544 && (off & 7) + cbWrite > sizeof(X86PDEPAE)) 544 545 { 545 const unsigned iShw2 = (off + pgmPoolDisasWriteSize(pCpu)- 1) / sizeof(X86PDEPAE);546 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE); 546 547 AssertReturnVoid(iShw2 < ELEMENTS(uShw.pPDPae->a)); 547 548 … … 584 585 if ( pCpu 585 586 && (off & 7) 586 && (off & 7) + pgmPoolDisasWriteSize(pCpu)> sizeof(X86PDPE))587 && (off & 7) + cbWrite > sizeof(X86PDPE)) 587 588 { 588 const unsigned iShw2 = (off + pgmPoolDisasWriteSize(pCpu)- 1) / sizeof(X86PDPE);589 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE); 589 590 if (uShw.pPDPT->a[iShw2].n.u1Present) 590 591 { … … 615 616 if ( pCpu 616 617 && (off & 7) 617 && (off & 7) + pgmPoolDisasWriteSize(pCpu)> sizeof(X86PDPE))618 && (off & 7) + cbWrite > sizeof(X86PDPE)) 618 619 { 619 const unsigned iShw2 = (off + pgmPoolDisasWriteSize(pCpu)- 1) / sizeof(X86PML4E);620 const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E); 620 621 if (uShw.pPML4->a[iShw2].n.u1Present) 621 622 {
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