Changeset 103645 in vbox for trunk/src/VBox/VMM/VMMAll/target-x86

Timestamp:

Mar 2, 2024 2:08:22 AM (14 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162005

Message:

VMM/IEM: Implemented iemNativeEmit_and_r_r_efl and enabled it for AMD64 hosts. bugref:10376

File:

• trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

@@ -128 +128 @@
                           uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
 {
-    RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
-    AssertFailed();
-    return iemNativeEmitBrk(pReNative, off, 0x666);
+    /*
+     * The AND instruction will clear OF, CF and AF (latter is off undefined),
+     * so we don't need the initial destination value.
+     *
+     * On AMD64 we must use the correctly sized AND instructions to get the
+     * right EFLAGS.SF value, while the rest will just lump 16-bit and 8-bit
+     * in the 32-bit ones.
+     */
+    /** @todo we could use ANDS on ARM64 and get the ZF for free for all
+     *        variants, and SF for 32-bit and 64-bit.  */
+    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
+    uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/);
+    //off = iemNativeEmitBrk(pReNative, off, 0x2222);
+    switch (cOpBits)
+    {
+        case 32:
+#ifndef RT_ARCH_AMD64
+        case 16:
+        case 8:
+#endif
+            off = iemNativeEmitAndGpr32ByGpr32(pReNative, off, idxRegDst, idxRegSrc);
+            break;
+
+        default: AssertFailed(); RT_FALL_THRU();
+        case 64:
+            off = iemNativeEmitAndGprByGpr(pReNative, off, idxRegDst, idxRegSrc);
+            break;
+
+#ifdef RT_ARCH_AMD64
+        case 16:
+        {
+            PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
+            pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+            off = iemNativeEmitAndGpr32ByGpr32(pReNative, off, idxRegDst, idxRegSrc);
+            break;
+        }
+
+        case 8:
+        {
+            PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 3);
+            if (idxRegDst >= 8 || idxRegSrc >= 8)
+                pCodeBuf[off++] = (idxRegDst >= 8 ? X86_OP_REX_R : 0) | (idxRegSrc >= 8 ? X86_OP_REX_B : 0);
+            else if (idxRegDst >= 4 || idxRegSrc >= 4)
+                pCodeBuf[off++] = X86_OP_REX;
+            pCodeBuf[off++] = 0x22;
+            pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxRegDst & 7, idxRegSrc & 7);
+            IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+            break;
+        }
+#endif
+    }
+    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
+
+    off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
+    iemNativeVarRegisterRelease(pReNative, idxVarDst);
+    return off;
 }