Changeset 103675 in vbox for trunk/src/VBox/VMM/VMMAll/target-x86

Timestamp:

Mar 5, 2024 2:10:37 AM (11 months ago)

Author:

vboxsync

Message:

VMM/IEM: Implemented iemNativeEmit_sub_r_r_efl and enabled it for both hosts. bugref:10376

File:

• trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h (modified) (3 diffs)

trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

@@ -33 +33 @@
 
 
+#ifdef RT_ARCH_AMD64
+DECL_FORCE_INLINE(uint32_t)
+iemNativeEmitAmd64ModRmInstrRREx(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t bOpcode8, uint8_t bOpcodeOther,
+                                 uint8_t cOpBits, uint8_t idxRegReg, uint8_t idxRegRm)
+{
+    Assert(idxRegReg < 16); Assert(idxRegRm < 16);
+    switch (cOpBits)
+    {
+        case 16:
+            pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+            RT_FALL_THRU();
+        case 32:
+            if (idxRegReg >= 8 || idxRegRm >= 8)
+                pCodeBuf[off++] = (idxRegReg >= 8 ? X86_OP_REX_R : 0) | (idxRegRm >= 8 ? X86_OP_REX_B : 0);
+            pCodeBuf[off++] = bOpcodeOther;
+            break;
+
+        default: AssertFailed(); RT_FALL_THRU();
+        case 64:
+            pCodeBuf[off++] = X86_OP_REX_W | (idxRegReg >= 8 ? X86_OP_REX_R : 0) | (idxRegRm >= 8 ? X86_OP_REX_B : 0);
+            pCodeBuf[off++] = bOpcodeOther;
+            break;
+
+        case 8:
+            if (idxRegReg >= 8 || idxRegRm >= 8)
+                pCodeBuf[off++] = (idxRegReg >= 8 ? X86_OP_REX_R : 0) | (idxRegRm >= 8 ? X86_OP_REX_B : 0);
+            else if (idxRegReg >= 4 || idxRegRm >= 4)
+                pCodeBuf[off++] = X86_OP_REX;
+            pCodeBuf[off++] = bOpcode8;
+            break;
+    }
+    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxRegReg & 7, idxRegRm & 7);
+    return off;
+}
+#endif /* RT_ARCH_AMD64 */
+
+
 /**
- * This is an implementation of IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL
- * and friends.
+ * This is an implementation of IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL.
  *
  * It takes liveness stuff into account.
@@ -121 +157 @@
     }
     return off;
+}
+
+
+/**
+ * This is an implementation of IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC.
+ *
+ * It takes liveness stuff into account.
+ */
+DECL_FORCE_INLINE_THROW(uint32_t)
+iemNativeEmitEFlagsForArithmetic(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarEfl
+#ifndef RT_ARCH_AMD64
+                                 , uint8_t cOpBits, uint8_t idxRegResult, uint8_t idxRegDstIn, uint8_t idxRegSrc, bool fNativeFlags
+#endif
+                                 )
+{
+#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
+    if (1) /** @todo check if all bits are clobbered. */
+#endif
+    {
+#ifdef RT_ARCH_AMD64
+        /*
+         * Collect flags and merge them with eflags.
+         */
+        PIEMNATIVEINSTR pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
+        /* pushf - do this before any reg allocations as they may emit instructions too. */
+        pCodeBuf[off++] = 0x9c;
+
+        uint8_t const idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /*fInitialized*/);
+        uint8_t const idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
+        pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2 + 7 + 7 + 3);
+        /* pop   tmp */
+        if (idxTmpReg >= 8)
+            pCodeBuf[off++] = X86_OP_REX_B;
+        pCodeBuf[off++] = 0x58 + (idxTmpReg & 7);
+        /* Isolate the flags we want. */
+        off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxTmpReg, X86_EFL_STATUS_BITS);
+        /* Clear the status bits in EFLs. */
+        off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegEfl, ~X86_EFL_STATUS_BITS);
+        /* OR in the flags we collected. */
+        off = iemNativeEmitOrGpr32ByGprEx(pCodeBuf, off, idxRegEfl, idxTmpReg);
+        iemNativeVarRegisterRelease(pReNative, idxVarEfl);
+        iemNativeRegFreeTmp(pReNative, idxTmpReg);
+
+#elif defined(RT_ARCH_ARM64)
+        /*
+         * Calculate flags.
+         */
+        uint8_t const         idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /*fInitialized*/);
+        uint8_t const         idxTmpReg = iemNativeRegAllocTmp(pReNative, &off);
+        PIEMNATIVEINSTR const pCodeBuf  = iemNativeInstrBufEnsure(pReNative, off, 18);
+
+        if (fNativeFlags && cOpBits >= 32)
+        {
+            /* Invert CF (stored inved on ARM) and load the flags into the temporary register. */
+            pCodeBuf[off++] = ARMV8_A64_INSTR_CFINV;
+            pCodeBuf[off++] = Armv8A64MkInstrMrs(idxTmpReg, ARMV8_AARCH64_SYSREG_NZCV); /* Bits: 31=N; 30=Z; 29=C; 28=V; */
+
+            /* V -> OF */
+            pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, 28);
+            pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_OF_BIT, 1, false /*f64Bit*/);
+
+            /* C -> CF */
+            pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, 1);
+            pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_CF_BIT, 1, false /*f64Bit*/);
+
+            /* N,Z -> SF,ZF */
+            pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, 1);
+            pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_ZF_BIT, 2, false /*f64Bit*/);
+        }
+        else
+        {
+#if 0
+            pCodeBuf[off++] = Armv8A64MkInstrSetF8SetF16(idxRegResult, cOpBits > 8);
+            pCodeBuf[off++] = Armv8A64MkInstrMrs(idxTmpReg, ARMV8_AARCH64_SYSREG_NZCV); /* Bits: 31=N; 30=Z; 29=C; 28=V; */
+
+            /* V -> OF */
+            pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, 28);
+            pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_OF_BIT, 1, false /*f64Bit*/);
+
+            /* N,Z -> SF,ZF */
+            pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, 2);
+            pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_ZF_BIT, 2, false /*f64Bit*/);
+#else
+            pCodeBuf[off++] = Armv8A64MkInstrBrk(0x1010);
+#endif
+        }
+
+        /* Calculate 8-bit parity of the result. */
+        pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxRegResult, idxRegResult, false /*f64Bit*/,
+                                             4 /*offShift6*/, kArmv8A64InstrShift_Lsr);
+        pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg,    idxTmpReg,    false /*f64Bit*/,
+                                             2 /*offShift6*/, kArmv8A64InstrShift_Lsr);
+        pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg,    idxTmpReg,    false /*f64Bit*/,
+                                             1 /*offShift6*/, kArmv8A64InstrShift_Lsr);
+        Assert(Armv8A64ConvertImmRImmS2Mask32(0, 0) == 1);
+        pCodeBuf[off++] = Armv8A64MkInstrEorImm(idxTmpReg, idxTmpReg, 0, 0, false /*f64Bit*/);
+        pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_PF_BIT, 1,  false /*f64Bit*/);
+
+        /* Calculate auxilary carry/borrow.  This is related to 8-bit BCD.*/
+        pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxRegDstIn, idxRegSrc, false /*f64Bit*/);
+        pCodeBuf[off++] = Armv8A64MkInstrEor(idxTmpReg, idxTmpReg, idxRegResult, false /*f64Bit*/);
+        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxTmpReg, idxTmpReg, X86_EFL_AF_BIT, false /*f64Bit*/);
+        pCodeBuf[off++] = Armv8A64MkInstrBfi(idxRegEfl, idxTmpReg, X86_EFL_AF_BIT, 1,  false /*f64Bit*/);
+
+        iemNativeVarRegisterRelease(pReNative, idxVarEfl);
+        iemNativeRegFreeTmp(pReNative, idxTmpReg);
+#else
+# error "port me"
+#endif
+        IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+    }
+    return off;
+
 }
 
@@ -405 +554 @@
                           uint8_t idxVarDst, uint8_t idxVarSrc, uint8_t idxVarEfl, uint8_t cOpBits)
 {
-    RT_NOREF(idxVarDst, idxVarSrc, idxVarEfl, cOpBits);
-    AssertFailed();
-    return iemNativeEmitBrk(pReNative, off, 0x666);
+    /*
+     * The SUB instruction will set all flags.
+     */
+    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
+    uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/);
+
+#ifdef RT_ARCH_ARM64
+    /* On ARM64 we'll need the two input operands as well as the result in order
+       to calculate the right flags, even if we use SUBS and translates NZCV into
+       OF, CF, ZF and SF. */
+
+    /* Copy idxRegDst. */
+    uint8_t const idxRegDstIn = iemNativeRegAllocTmp(pReNative, &off);
+    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 4);
+
+    /* Do the SUB setting flags. */
+    if (cOpBits >= 32)
+    {
+        off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, idxRegDstIn, idxRegDst);
+        pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegDst, idxRegDst, idxRegSrc, cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
+    }
+    else
+    {
+        /* Shift the operands up so we can perform a 32-bit operation and get all four flags. */
+        uint32_t const cShift = 32 - cOpBits;
+        pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegDstIn, ARMV8_A64_REG_XZR, idxRegDst, false /*f64Bit*/, cShift);
+        pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegDst, idxRegDstIn, idxRegSrc, cOpBits > 32 /*f64Bit*/,
+                                                true /*fSetFlags*/, cShift);
+        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDstIn, idxRegDstIn, cShift, false /*f64Bit*/);
+        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDst, idxRegDst, cShift, false /*f64Bit*/);
+    }
+
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, RT_MAX(cOpBits, 32), idxRegDst,
+                                           idxRegDstIn, idxRegSrc, true /*fNativeFlags*/);
+
+    iemNativeRegFreeTmp(pReNative, idxRegDstIn);
+    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
+    iemNativeVarRegisterRelease(pReNative, idxVarDst);
+
+#elif defined(RT_ARCH_AMD64)
+    /* On AMD64 we must use the correctly sized AND instructions to get the
+       right EFLAGS.SF value, while the rest will just lump 16-bit and 8-bit
+       in the 32-bit ones. */
+    off = iemNativeEmitAmd64ModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
+                                           0x2a, 0x2b, cOpBits, idxRegDst, idxRegSrc);
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
+    iemNativeVarRegisterRelease(pReNative, idxVarDst);
+
+    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl);
+
+#else
+# error "port me"
+#endif
+    return off;
 }