Changeset 103697 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Mar 6, 2024 7:17:34 AM (12 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162064

Message:

ValidationKit/bootsectors: Implement testcases for [v]pmaddwd instructions, bugref:9898

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-instr-3-template.mac (modified) (1 diff)
• bs3-cpu-instr-3.c32 (modified) (2 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

@@ -2655 +2655 @@
 EMIT_INSTR_PLUS_ICEBP_C64   vpermilpd, YMM8, FSxBX, 091h
 
+;
+; [V]PMADDUBSW
+;
+EMIT_INSTR_PLUS_ICEBP_MMX      pmaddwd
+EMIT_INSTR_PLUS_ICEBP_XMM      pmaddwd
+EMIT_INSTR_PLUS_ICEBP_XMM_123  vpmaddwd
+EMIT_INSTR_PLUS_ICEBP_YMM_123  vpmaddwd
+EMIT_INSTR_PLUS_ICEBP_XMM_89   pmaddwd
+EMIT_INSTR_PLUS_ICEBP_XMM_890  vpmaddwd
+EMIT_INSTR_PLUS_ICEBP_YMM_890  vpmaddwd
+
 %endif ; BS3_INSTANTIATING_CMN
 

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

@@ -12527 +12527 @@
 
 
-
+/*
+ * [V]PMADDWD  - Multiply and add packed signed word integers.
+ */
+BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaddwd(uint8_t bMode)
+{
+    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
+        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
+            /* => */ RTUINT256_INIT_C(                 1,                  2,                  3, 0x3c0b6394364ffde4) },
+        {   /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
+            /* => */ RTUINT256_INIT_C(                 5,                  6,                  7, 0xebcf52b41ad4c573) },
+    };
+    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
+        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
+            /* => */ RTUINT256_INIT_C(                 9,                 10, 0x26a0ce5421e769a4, 0x3c0b6394364ffde4) },
+        {   /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
+            /* => */ RTUINT256_INIT_C(                13,                 14, 0x1f5960b8c391d7d2, 0xebcf52b41ad4c573) },
+    };
+    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
+        {   /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788),
+            /* => */ RTUINT256_INIT_C(0x07e3afd4052e4d24, 0x153e3d141186d964, 0x26a0ce5421e769a4, 0x3c0b6394364ffde4) },
+        {   /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c880008000, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec80008000, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
+            /* => */ RTUINT256_INIT_C(0x0b692cfd1ae06638, 0xf3dcd01080000000, 0x1f5960b8c391d7d2, 0xebcf52b41ad4c573) },
+    };
+
+    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
+    {
+        {  bs3CpuInstr3_pmaddwd_MM1_MM2_icebp_c16,          255,         RM_REG, T_MMX,       1, 1,   2, RT_ELEMENTS(s_aValues64W),   s_aValues64W  },
+        {  bs3CpuInstr3_pmaddwd_MM1_FSxBX_icebp_c16,        255,         RM_MEM, T_MMX,       1, 1, 255, RT_ELEMENTS(s_aValues64W),   s_aValues64W  },
+        {  bs3CpuInstr3_pmaddwd_XMM1_XMM2_icebp_c16,        255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_pmaddwd_XMM1_FSxBX_icebp_c16,       255,         RM_MEM, T_SSE2,      1, 1, 255, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_XMM1_XMM2_XMM3_icebp_c16,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_YMM1_YMM2_YMM3_icebp_c16,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues256W),  s_aValues256W },
+        {  bs3CpuInstr3_vpmaddwd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues256W),  s_aValues256W },
+    };
+    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
+    {
+        {  bs3CpuInstr3_pmaddwd_MM1_MM2_icebp_c32,          255,         RM_REG, T_MMX,       1, 1,   2, RT_ELEMENTS(s_aValues64W),   s_aValues64W },
+        {  bs3CpuInstr3_pmaddwd_MM1_FSxBX_icebp_c32,        255,         RM_MEM, T_MMX,       1, 1, 255, RT_ELEMENTS(s_aValues64W),   s_aValues64W },
+        {  bs3CpuInstr3_pmaddwd_XMM1_XMM2_icebp_c32,        255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_pmaddwd_XMM1_FSxBX_icebp_c32,       255,         RM_MEM, T_SSE2,      1, 1, 255, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_XMM1_XMM2_XMM3_icebp_c32,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_YMM1_YMM2_YMM3_icebp_c32,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues256W),  s_aValues256W },
+        {  bs3CpuInstr3_vpmaddwd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues256W),  s_aValues256W },
+    };
+    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
+    {
+        {  bs3CpuInstr3_pmaddwd_MM1_MM2_icebp_c64,          255,         RM_REG, T_MMX,       1, 1,   2, RT_ELEMENTS(s_aValues64W),   s_aValues64W },
+        {  bs3CpuInstr3_pmaddwd_MM1_FSxBX_icebp_c64,        255,         RM_MEM, T_MMX,       1, 1, 255, RT_ELEMENTS(s_aValues64W),   s_aValues64W },
+        {  bs3CpuInstr3_pmaddwd_XMM1_XMM2_icebp_c64,        255,         RM_REG, T_SSE2,      1, 1,   2, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_pmaddwd_XMM1_FSxBX_icebp_c64,       255,         RM_MEM, T_SSE2,      1, 1, 255, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_pmaddwd_XMM8_XMM9_icebp_c64,        255,         RM_REG, T_SSE2,      8, 8,   9, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_pmaddwd_XMM8_FSxBX_icebp_c64,       255,         RM_MEM, T_SSE2,      8, 8, 255, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_XMM1_XMM2_XMM3_icebp_c64,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_XMM8_XMM9_XMM10_icebp_c64, 255,         RM_REG, T_AVX_128,   8, 9,  10, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   8, 9, 255, RT_ELEMENTS(s_aValues128W),  s_aValues128W },
+        {  bs3CpuInstr3_vpmaddwd_YMM1_YMM2_YMM3_icebp_c64,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues256W),  s_aValues256W },
+        {  bs3CpuInstr3_vpmaddwd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues256W),  s_aValues256W },
+        {  bs3CpuInstr3_vpmaddwd_YMM8_YMM9_YMM10_icebp_c64, 255,         RM_REG, T_AVX2_256,  8, 9,  10, RT_ELEMENTS(s_aValues256W),  s_aValues256W },
+        {  bs3CpuInstr3_vpmaddwd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  8, 9, 255, RT_ELEMENTS(s_aValues256W),  s_aValues256W },
+    };
+    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
+}
 
 /**
@@ -12712 +12797 @@
         { "vpermilpd",                                      bs3CpuInstr3_vpermilpd, 0 },
 #endif
+#if defined (ALL_TESTS)
+        { "[v]pmaddwd",                                     bs3CpuInstr3_v_pmaddwd, 0 },
+#endif
     };
     Bs3TestInit("bs3-cpu-instr-3");