Changeset 103735 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Mar 8, 2024 5:15:24 AM (9 months ago)

Author:

vboxsync

Message:

VMM/IEM: Implement vpsrlv[dq], vpsravd, vpsllv[dq] instruction dispatch & emulation, bugref:9898

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAllAImpl.asm (modified) (1 diff)
• IEMAllAImplC.cpp (modified) (1 diff)
• IEMAllInstVexMap2.cpp.h (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -4429 +4429 @@
 IEMIMPL_MEDIA_OPT_F3 vpermilpd
 IEMIMPL_MEDIA_OPT_F3 vpmaddwd
+IEMIMPL_MEDIA_OPT_F3 vpsrlvd
+IEMIMPL_MEDIA_OPT_F3 vpsrlvq
+IEMIMPL_MEDIA_OPT_F3 vpsravd
+IEMIMPL_MEDIA_OPT_F3 vpsllvd
+IEMIMPL_MEDIA_OPT_F3 vpsllvq
 
 ;;

trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

@@ -11222 +11222 @@
 
 /*
+ * VPSRLVD
+ */
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlvd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2))
+{
+    for (uint8_t uU32 = 0; uU32 < RT_ELEMENTS(puDst->au32); ++uU32)
+    {
+        puDst->au32[uU32] = (puSrc2->au32[uU32] > 31) ? 0 : puSrc1->au32[uU32] >> puSrc2->au8[uU32 << 2];
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlvd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2))
+{
+    for (uint8_t uU32 = 0; uU32 < RT_ELEMENTS(puDst->au32); ++uU32)
+    {
+        puDst->au32[uU32] = (puSrc2->au32[uU32] > 31) ? 0 : puSrc1->au32[uU32] >> puSrc2->au8[uU32 << 2];
+    }
+}
+
+
+/*
+ * VPSRAVD
+ */
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsravd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2))
+{
+    for (uint8_t uI32 = 0; uI32 < RT_ELEMENTS(puDst->ai32); ++uI32)
+    {
+        puDst->ai32[uI32] = (puSrc2->au32[uI32] > 31) ? 0 : puSrc1->ai32[uI32] >> puSrc2->au8[uI32 << 2];
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsravd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2))
+{
+    for (uint8_t uI32 = 0; uI32 < RT_ELEMENTS(puDst->ai32); ++uI32)
+    {
+        puDst->ai32[uI32] = (puSrc2->au32[uI32] > 31) ? 0 : puSrc1->ai32[uI32] >> puSrc2->au8[uI32 << 2];
+    }
+}
+
+
+/*
+ * VPSLLVD
+ */
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsllvd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2))
+{
+    for (uint8_t uU32 = 0; uU32 < RT_ELEMENTS(puDst->au32); ++uU32)
+    {
+        puDst->au32[uU32] = (puSrc2->au32[uU32] > 31) ? 0 : puSrc1->au32[uU32] << puSrc2->au8[uU32 << 2];
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsllvd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2))
+{
+    for (uint8_t uU32 = 0; uU32 < RT_ELEMENTS(puDst->au32); ++uU32)
+    {
+        puDst->au32[uU32] = (puSrc2->au32[uU32] > 31) ? 0 : puSrc1->au32[uU32] << puSrc2->au8[uU32 << 2];
+    }
+}
+
+
+/*
+ * VPSRLVQ
+ */
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlvq_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2))
+{
+    for (uint8_t uU64 = 0; uU64 < RT_ELEMENTS(puDst->au64); ++uU64)
+    {
+        puDst->au64[uU64] = (puSrc2->au64[uU64] > 63) ? 0 : puSrc1->au64[uU64] >> puSrc2->au8[uU64 << 3];
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsrlvq_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2))
+{
+    for (uint8_t uU64 = 0; uU64 < RT_ELEMENTS(puDst->au64); ++uU64)
+    {
+        puDst->au64[uU64] = (puSrc2->au64[uU64] > 63) ? 0 : puSrc1->au64[uU64] >> puSrc2->au8[uU64 << 3];
+    }
+}
+
+
+/*
+ * VPSLLVQ
+ */
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsllvq_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2))
+{
+    for (uint8_t uU64 = 0; uU64 < RT_ELEMENTS(puDst->au64); ++uU64)
+    {
+        puDst->au64[uU64] = (puSrc2->au64[uU64] > 63) ? 0 : puSrc1->au64[uU64] << puSrc2->au8[uU64 << 3];
+    }
+}
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vpsllvq_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2))
+{
+    for (uint8_t uU64 = 0; uU64 < RT_ELEMENTS(puDst->au64); ++uU64)
+    {
+        puDst->au64[uU64] = (puSrc2->au64[uU64] > 63) ? 0 : puSrc1->au64[uU64] << puSrc2->au8[uU64 << 3];
+    }
+}
+
+
+/*
  * PMADDWD / VPMADDWD
  */

trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap2.cpp.h

@@ -1038 +1038 @@
 /*  Opcode VEX.66.0F38 0x43 - invalid. */
 /*  Opcode VEX.66.0F38 0x44 - invalid. */
+
+
 /** Opcode VEX.66.0F38 0x45. */
-FNIEMOP_STUB(iemOp_vpsrlvd_q_Vx_Hx_Wx);
+FNIEMOP_DEF(iemOp_vpsrlvd_q_Vx_Hx_Wx)
+{
+    IEMOP_MNEMONIC3(VEX_RVM, VPSRLVD, vpsrlvd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
+
+    if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
+    {
+        IEMOPMEDIAOPTF3_INIT_VARS(vpsrlvq);
+        return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
+    }
+    else
+    {
+        IEMOPMEDIAOPTF3_INIT_VARS(vpsrlvd);
+        return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
+    }
+}
+
+
 /** Opcode VEX.66.0F38 0x46. */
-FNIEMOP_STUB(iemOp_vsravd_Vx_Hx_Wx);
+FNIEMOP_DEF(iemOp_vpsravd_Vx_Hx_Wx)
+{
+    IEMOP_MNEMONIC3(VEX_RVM, VPSRAVD, vpsravd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
+    IEMOPMEDIAOPTF3_INIT_VARS(vpsravd);
+    return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
+}
+
+
 /** Opcode VEX.66.0F38 0x47. */
-FNIEMOP_STUB(iemOp_vpsllvd_q_Vx_Hx_Wx);
+FNIEMOP_DEF(iemOp_vpsllvd_q_Vx_Hx_Wx)
+{
+    IEMOP_MNEMONIC3(VEX_RVM, VPSLLVD, vpsllvd, Vx, Hx, Wx, DISOPTYPE_HARMLESS, 0);
+
+    if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
+    {
+        IEMOPMEDIAOPTF3_INIT_VARS(vpsllvq);
+        return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
+    }
+    else
+    {
+        IEMOPMEDIAOPTF3_INIT_VARS(vpsllvd);
+        return FNIEMOP_CALL_1(iemOpCommonAvxAvx2_Vx_Hx_Wx_Opt, IEM_SELECT_HOST_OR_FALLBACK(fAvx2, &s_Host, &s_Fallback));
+    }
+}
+
+
 /*  Opcode VEX.66.0F38 0x48 - invalid. */
 /*  Opcode VEX.66.0F38 0x49 - invalid. */
@@ -2506 +2547 @@
     /* 0x44 */  IEMOP_X4(iemOp_InvalidNeedRM),
     /* 0x45 */  iemOp_InvalidNeedRM,        iemOp_vpsrlvd_q_Vx_Hx_Wx,   iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,
-    /* 0x46 */  iemOp_InvalidNeedRM,        iemOp_vsravd_Vx_Hx_Wx,      iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,
+    /* 0x46 */  iemOp_InvalidNeedRM,        iemOp_vpsravd_Vx_Hx_Wx,     iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,
     /* 0x47 */  iemOp_InvalidNeedRM,        iemOp_vpsllvd_q_Vx_Hx_Wx,   iemOp_InvalidNeedRM,        iemOp_InvalidNeedRM,
     /* 0x48 */  IEMOP_X4(iemOp_InvalidNeedRM),