VirtualBox

Changeset 103736 in vbox


Ignore:
Timestamp:
Mar 8, 2024 5:15:45 AM (13 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
162105
Message:

ValidationKit/bootsectors: Implement testcases for vpsrlv[dq], vpsravd, vpsllv[dq] instructions, bugref:9898

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

    r103701 r103736  
    25612561EMIT_INSTR_PLUS_ICEBP_C64   vpsrlq, YMM8, YMM9, 001h
    25622562EMIT_INSTR_PLUS_ICEBP_C64   vpsrlq, YMM8, YMM9, 012h
     2563
     2564;
     2565; VPSRLVD
     2566;
     2567EMIT_INSTR_PLUS_ICEBP_XMM_123  vpsrlvd
     2568EMIT_INSTR_PLUS_ICEBP_YMM_123  vpsrlvd
     2569EMIT_INSTR_PLUS_ICEBP_XMM_890  vpsrlvd
     2570EMIT_INSTR_PLUS_ICEBP_YMM_890  vpsrlvd
     2571
     2572;
     2573; VPSRLVQ
     2574;
     2575EMIT_INSTR_PLUS_ICEBP_XMM_123  vpsrlvq
     2576EMIT_INSTR_PLUS_ICEBP_YMM_123  vpsrlvq
     2577EMIT_INSTR_PLUS_ICEBP_XMM_890  vpsrlvq
     2578EMIT_INSTR_PLUS_ICEBP_YMM_890  vpsrlvq
     2579
     2580;
     2581; VPSRAVD
     2582;
     2583EMIT_INSTR_PLUS_ICEBP_XMM_123  vpsravd
     2584EMIT_INSTR_PLUS_ICEBP_YMM_123  vpsravd
     2585EMIT_INSTR_PLUS_ICEBP_XMM_890  vpsravd
     2586EMIT_INSTR_PLUS_ICEBP_YMM_890  vpsravd
     2587
     2588;
     2589; VPSLLVD
     2590;
     2591EMIT_INSTR_PLUS_ICEBP_XMM_123  vpsllvd
     2592EMIT_INSTR_PLUS_ICEBP_YMM_123  vpsllvd
     2593EMIT_INSTR_PLUS_ICEBP_XMM_890  vpsllvd
     2594EMIT_INSTR_PLUS_ICEBP_YMM_890  vpsllvd
     2595
     2596;
     2597; VPSLLVQ
     2598;
     2599EMIT_INSTR_PLUS_ICEBP_XMM_123  vpsllvq
     2600EMIT_INSTR_PLUS_ICEBP_YMM_123  vpsllvq
     2601EMIT_INSTR_PLUS_ICEBP_XMM_890  vpsllvq
     2602EMIT_INSTR_PLUS_ICEBP_YMM_890  vpsllvq
    25632603
    25642604;

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

    r103701 r103736  
    81368136        {  bs3CpuInstr3_vpsrlq_YMM8_YMM9_001h_icebp_c64,   255,         RM_REG, T_AVX2_256,  8, 9,   1, RT_ELEMENTS(s_aValues64_01), s_aValues64_01  },
    81378137        {  bs3CpuInstr3_vpsrlq_YMM8_YMM9_012h_icebp_c64,   255,         RM_REG, T_AVX2_256,  8, 9,   1, RT_ELEMENTS(s_aValues64_12), s_aValues64_12  },
     8138    };
     8139    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     8140    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     8141    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     8142                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
     8143}
     8144
     8145
     8146/*
     8147 * VPSLLVD/VPSLLVQ  - Variable bit shift left logical
     8148 */
     8149BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vpsllvd_vpsllvq(uint8_t bMode)
     8150{
     8151    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] =
     8152    {
     8153        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8154            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8155            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
     8156        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000),
     8157            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8158            /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) },  /* sll 0-by-32 */
     8159        {   /*src2*/ RTUINT256_INIT_C(0x0000000100000001, 0x0000000100000001, 0x0000000100000001, 0x0000000100000001),
     8160            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8161            /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b67f32c586, 0x87a79b40470933fa) },  /* sll 1-by-32 */
     8162        {   /*src2*/ RTUINT256_INIT_C(0x0000000600000006, 0x0000000600000006, 0x0000000600000006, 0x0000000600000006),
     8163            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8164            /* => */ RTUINT256_INIT_C(0xb7776b0058cca500, 0x5723bb001c958cc0, 0x003a56c0e658b0c0, 0xf4f36800e1267f40) },  /* sll 6-by-32 */
     8165        {   /*src2*/ RTUINT256_INIT_C(0x0000000300000000, 0x000000160000001F, 0x0000000600000001, 0x0000300100000006),
     8166            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8167            /* => */ RTUINT256_INIT_C(0xf6eeed6009633294, 0xbb00000080000000, 0x003a56c07f32c586, 0x00000000e1267f40) },  /* sll v-by-32 */
     8168    };
     8169    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
     8170    {
     8171        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8172            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8173            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
     8174        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000),
     8175            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8176            /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) },  /* sll 0-by-64 */
     8177        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000001, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001),
     8178            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8179            /* => */ RTUINT256_INIT_C(0x3dbbbb5812c66528, 0xf2b91dd880e4ac66, 0x1001d2b77f32c586, 0x87a79b40470933fa) },  /* sll 1-by-64 */
     8180        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000006, 0x0000000000000006, 0x0000000000000006, 0x0000000000000006),
     8181            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8182            /* => */ RTUINT256_INIT_C(0xb7776b0258cca500, 0x5723bb101c958cc0, 0x003a56efe658b0c0, 0xf4f36808e1267f40) },  /* sll 6-by-64 */
     8183        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x000000000000001F, 0x0000000000000001, 0xfedcba9876543210),
     8184            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8185            /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x20392B1980000000, 0x1001d2b77f32c586, 0x0000000000000000) },  /* sll v-by-64 */
     8186    };
     8187    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
     8188    {
     8189        {  bs3CpuInstr3_vpsllvd_XMM1_XMM2_XMM3_icebp_c16,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8190        {  bs3CpuInstr3_vpsllvd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8191        {  bs3CpuInstr3_vpsllvd_YMM1_YMM2_YMM3_icebp_c16,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8192        {  bs3CpuInstr3_vpsllvd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8193
     8194        {  bs3CpuInstr3_vpsllvq_XMM1_XMM2_XMM3_icebp_c16,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8195        {  bs3CpuInstr3_vpsllvq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8196        {  bs3CpuInstr3_vpsllvq_YMM1_YMM2_YMM3_icebp_c16,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8197        {  bs3CpuInstr3_vpsllvq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8198    };
     8199    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
     8200    {
     8201        {  bs3CpuInstr3_vpsllvd_XMM1_XMM2_XMM3_icebp_c32,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8202        {  bs3CpuInstr3_vpsllvd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8203        {  bs3CpuInstr3_vpsllvd_YMM1_YMM2_YMM3_icebp_c32,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8204        {  bs3CpuInstr3_vpsllvd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8205
     8206        {  bs3CpuInstr3_vpsllvq_XMM1_XMM2_XMM3_icebp_c32,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8207        {  bs3CpuInstr3_vpsllvq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8208        {  bs3CpuInstr3_vpsllvq_YMM1_YMM2_YMM3_icebp_c32,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8209        {  bs3CpuInstr3_vpsllvq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8210    };
     8211    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
     8212    {
     8213        {  bs3CpuInstr3_vpsllvd_XMM1_XMM2_XMM3_icebp_c64,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8214        {  bs3CpuInstr3_vpsllvd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8215        {  bs3CpuInstr3_vpsllvd_YMM1_YMM2_YMM3_icebp_c64,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8216        {  bs3CpuInstr3_vpsllvd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8217        {  bs3CpuInstr3_vpsllvd_XMM8_XMM9_XMM10_icebp_c64, 255,         RM_REG, T_AVX_128,   8, 9,  10, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8218        {  bs3CpuInstr3_vpsllvd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8219        {  bs3CpuInstr3_vpsllvd_YMM8_YMM9_YMM10_icebp_c64, 255,         RM_REG, T_AVX2_256,  8, 9,  10, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8220        {  bs3CpuInstr3_vpsllvd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8221
     8222        {  bs3CpuInstr3_vpsllvq_XMM1_XMM2_XMM3_icebp_c64,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8223        {  bs3CpuInstr3_vpsllvq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8224        {  bs3CpuInstr3_vpsllvq_YMM1_YMM2_YMM3_icebp_c64,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8225        {  bs3CpuInstr3_vpsllvq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8226        {  bs3CpuInstr3_vpsllvq_XMM8_XMM9_XMM10_icebp_c64, 255,         RM_REG, T_AVX_128,   8, 9,  10, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8227        {  bs3CpuInstr3_vpsllvq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8228        {  bs3CpuInstr3_vpsllvq_YMM8_YMM9_YMM10_icebp_c64, 255,         RM_REG, T_AVX2_256,  8, 9,  10, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8229        {  bs3CpuInstr3_vpsllvq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8230    };
     8231    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     8232    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     8233    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     8234                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
     8235}
     8236
     8237
     8238/*
     8239 * VPSRAVD  - Variable bit shift right arithmetic
     8240 */
     8241BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vpsravd(uint8_t bMode)
     8242{
     8243    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] =
     8244    {
     8245        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8246            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8247            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
     8248        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000),
     8249            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8250            /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) },  /* sra 0-by-32 */
     8251        {   /*src2*/ RTUINT256_INIT_C(0x0000000100000001, 0x0000000100000001, 0x0000000100000001, 0x0000000100000001),
     8252            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8253            /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0xfcae477620392b19, 0xc40074addfccb161, 0x21e9e6d011c24cfe) },  /* sra 1-by-32 */
     8254        {   /*src2*/ RTUINT256_INIT_C(0x0000000600000006, 0x0000000600000006, 0x0000000600000006, 0x0000000600000006),
     8255            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8256            /* => */ RTUINT256_INIT_C(0x007b777600258cca, 0xffe5723b0101c958, 0xfe2003a5fefe658b, 0x010f4f36008e1267) },  /* sra 6-by-32 */
     8257        {   /*src2*/ RTUINT256_INIT_C(0x0000000300000000, 0x000000160000001F, 0x0000000600000001, 0x0000300100000006),
     8258            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8259            /* => */ RTUINT256_INIT_C(0x03dbbbb509633294, 0xffffffe500000000, 0xfe2003a5dfccb161, 0x00000000008e1267) },  /* sra v-by-32 */
     8260    };
     8261    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
     8262    {
     8263        {  bs3CpuInstr3_vpsravd_XMM1_XMM2_XMM3_icebp_c16,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8264        {  bs3CpuInstr3_vpsravd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8265        {  bs3CpuInstr3_vpsravd_YMM1_YMM2_YMM3_icebp_c16,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8266        {  bs3CpuInstr3_vpsravd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8267    };
     8268    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
     8269    {
     8270        {  bs3CpuInstr3_vpsravd_XMM1_XMM2_XMM3_icebp_c32,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8271        {  bs3CpuInstr3_vpsravd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8272        {  bs3CpuInstr3_vpsravd_YMM1_YMM2_YMM3_icebp_c32,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8273        {  bs3CpuInstr3_vpsravd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8274    };
     8275    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
     8276    {
     8277        {  bs3CpuInstr3_vpsravd_XMM1_XMM2_XMM3_icebp_c64,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8278        {  bs3CpuInstr3_vpsravd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8279        {  bs3CpuInstr3_vpsravd_YMM1_YMM2_YMM3_icebp_c64,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8280        {  bs3CpuInstr3_vpsravd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8281        {  bs3CpuInstr3_vpsravd_XMM8_XMM9_XMM10_icebp_c64, 255,         RM_REG, T_AVX_128,   8, 9,  10, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8282        {  bs3CpuInstr3_vpsravd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8283        {  bs3CpuInstr3_vpsravd_YMM8_YMM9_YMM10_icebp_c64, 255,         RM_REG, T_AVX2_256,  8, 9,  10, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8284        {  bs3CpuInstr3_vpsravd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8285    };
     8286    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     8287    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     8288    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     8289                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
     8290}
     8291
     8292
     8293/*
     8294 * VPSRLVD/VPSRLVQ  - Variable bit shift right logical
     8295 */
     8296BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vpsrlvd_vpsrlvq(uint8_t bMode)
     8297{
     8298    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues32[] =
     8299    {
     8300        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8301            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8302            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
     8303        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000),
     8304            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8305            /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) },  /* srl 0-by-32 */
     8306        {   /*src2*/ RTUINT256_INIT_C(0x0000000100000001, 0x0000000100000001, 0x0000000100000001, 0x0000000100000001),
     8307            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8308            /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074ad5fccb161, 0x21e9e6d011c24cfe) },  /* srl 1-by-32 */
     8309        {   /*src2*/ RTUINT256_INIT_C(0x0000000600000006, 0x0000000600000006, 0x0000000600000006, 0x0000000600000006),
     8310            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8311            /* => */ RTUINT256_INIT_C(0x007b777600258cca, 0x03e5723b0101c958, 0x022003a502fe658b, 0x010f4f36008e1267) },  /* srl 6-by-32 */
     8312        {   /*src2*/ RTUINT256_INIT_C(0x0000000300000000, 0x000000160000001F, 0x0000000600000001, 0x0000300100000006),
     8313            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8314            /* => */ RTUINT256_INIT_C(0x03dbbbb509633294, 0x000003e500000000, 0x022003a55fccb161, 0x00000000008e1267) },  /* srl v-by-32 */
     8315    };
     8316    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] =
     8317    {
     8318        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8319            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8320            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
     8321        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000),
     8322            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8323            /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) },  /* srl 0-by-64 */
     8324        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000001, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001),
     8325            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8326            /* => */ RTUINT256_INIT_C(0x0f6eeed604b1994a, 0x7cae477620392b19, 0x440074addfccb161, 0x21e9e6d011c24cfe) },  /* srl 1-by-64 */
     8327        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000006, 0x0000000000000006, 0x0000000000000006, 0x0000000000000006),
     8328            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8329            /* => */ RTUINT256_INIT_C(0x007b7776b0258cca, 0x03e5723bb101c958, 0x022003a56efe658b, 0x010f4f36808e1267) },  /* srl 6-by-64 */
     8330        {   /*src2*/ RTUINT256_INIT_C(0x0000000000000000, 0x000000000000001F, 0x0000000000000001, 0xfedcba9876543210),
     8331            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8332            /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x00000001f2b91dd8, 0x440074addfccb161, 0x0000000000000000) },  /* srl v-by-64 */
     8333    };
     8334    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
     8335    {
     8336        {  bs3CpuInstr3_vpsrlvd_XMM1_XMM2_XMM3_icebp_c16,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8337        {  bs3CpuInstr3_vpsrlvd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8338        {  bs3CpuInstr3_vpsrlvd_YMM1_YMM2_YMM3_icebp_c16,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8339        {  bs3CpuInstr3_vpsrlvd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8340
     8341        {  bs3CpuInstr3_vpsrlvq_XMM1_XMM2_XMM3_icebp_c16,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8342        {  bs3CpuInstr3_vpsrlvq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8343        {  bs3CpuInstr3_vpsrlvq_YMM1_YMM2_YMM3_icebp_c16,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8344        {  bs3CpuInstr3_vpsrlvq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8345    };
     8346    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
     8347    {
     8348        {  bs3CpuInstr3_vpsrlvd_XMM1_XMM2_XMM3_icebp_c32,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8349        {  bs3CpuInstr3_vpsrlvd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8350        {  bs3CpuInstr3_vpsrlvd_YMM1_YMM2_YMM3_icebp_c32,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8351        {  bs3CpuInstr3_vpsrlvd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8352
     8353        {  bs3CpuInstr3_vpsrlvq_XMM1_XMM2_XMM3_icebp_c32,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8354        {  bs3CpuInstr3_vpsrlvq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8355        {  bs3CpuInstr3_vpsrlvq_YMM1_YMM2_YMM3_icebp_c32,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8356        {  bs3CpuInstr3_vpsrlvq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8357    };
     8358    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
     8359    {
     8360        {  bs3CpuInstr3_vpsrlvd_XMM1_XMM2_XMM3_icebp_c64,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8361        {  bs3CpuInstr3_vpsrlvd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8362        {  bs3CpuInstr3_vpsrlvd_YMM1_YMM2_YMM3_icebp_c64,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8363        {  bs3CpuInstr3_vpsrlvd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8364        {  bs3CpuInstr3_vpsrlvd_XMM8_XMM9_XMM10_icebp_c64, 255,         RM_REG, T_AVX_128,   8, 9,  10, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8365        {  bs3CpuInstr3_vpsrlvd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8366        {  bs3CpuInstr3_vpsrlvd_YMM8_YMM9_YMM10_icebp_c64, 255,         RM_REG, T_AVX2_256,  8, 9,  10, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8367        {  bs3CpuInstr3_vpsrlvd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  8, 9, 255, RT_ELEMENTS(s_aValues32), s_aValues32  },
     8368
     8369        {  bs3CpuInstr3_vpsrlvq_XMM1_XMM2_XMM3_icebp_c64,  255,         RM_REG, T_AVX_128,   1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8370        {  bs3CpuInstr3_vpsrlvq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8371        {  bs3CpuInstr3_vpsrlvq_YMM1_YMM2_YMM3_icebp_c64,  255,         RM_REG, T_AVX2_256,  1, 2,   3, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8372        {  bs3CpuInstr3_vpsrlvq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  1, 2, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8373        {  bs3CpuInstr3_vpsrlvq_XMM8_XMM9_XMM10_icebp_c64, 255,         RM_REG, T_AVX_128,   8, 9,  10, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8374        {  bs3CpuInstr3_vpsrlvq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,   8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8375        {  bs3CpuInstr3_vpsrlvq_YMM8_YMM9_YMM10_icebp_c64, 255,         RM_REG, T_AVX2_256,  8, 9,  10, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8376        {  bs3CpuInstr3_vpsrlvq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
    81388377    };
    81398378    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
    … …  
    1302513264#endif
    1302613265#if defined (ALL_TESTS)
     13266        { "vpsllvd/vpsllvq",                                bs3CpuInstr3_vpsllvd_vpsllvq, 0 },
     13267        { "vpsravd",                                        bs3CpuInstr3_vpsravd, 0 },
     13268        { "vpsrlvd/vpsrlvq",                                bs3CpuInstr3_vpsrlvd_vpsrlvq, 0 },
     13269#endif
     13270#if defined (ALL_TESTS)
    1302713271        { "vperm2i128/vperm2f128",                          bs3CpuInstr3_vperm2i128_vperm2f128, 0 },
    1302813272#endif
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