Changeset 103740 in vbox

Timestamp:

Mar 9, 2024 1:42:20 AM (9 months ago)

Author:

vboxsync

Message:

VMM/IEM: Implemented iemNativeEmit_sub_r_i_efl and enabled it for both hosts. bugref:10376

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAllInstOneByte.cpp.h (modified) (4 diffs)
• target-x86/IEMAllN8veEmit-x86.h (modified) (3 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h

@@ -1724 +1724 @@
 {
     IEMOP_MNEMONIC2(FIXED, SUB, sub, AL, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
-    IEMOP_BODY_BINARY_AL_Ib(sub, 0);
+    IEMOP_BODY_BINARY_AL_Ib(sub, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 
@@ -1736 +1736 @@
 {
     IEMOP_MNEMONIC2(FIXED, SUB, sub, rAX, Iz, DISOPTYPE_HARMLESS, 0);
-    IEMOP_BODY_BINARY_rAX_Iz_RW(sub, 0);
+    IEMOP_BODY_BINARY_rAX_Iz_RW(sub, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 
@@ -4440 +4440 @@
 {
     IEMOP_MNEMONIC(sub_Eb_Ib, "sub Eb,Ib");
-    IEMOP_BODY_BINARY_Eb_Ib_RW(sub, 0, 0);
+    IEMOP_BODY_BINARY_Eb_Ib_RW(sub, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, 0);
 }
 
@@ -5013 +5013 @@
 {
     IEMOP_MNEMONIC(sub_Ev_Iz, "sub Ev,Iz");
-    IEMOP_BODY_BINARY_Ev_Iz_RW(sub, 0, 0);
+    IEMOP_BODY_BINARY_Ev_Iz_RW(sub, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, 0);
 }
 

trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

@@ -732 +732 @@
         else
         {
-            uint8_t const idxTmpImmReg = iemNativeRegAllocTmpImm(pReNative, &off, uImmOp);
+            uint8_t const idxRegTmpImm = iemNativeRegAllocTmpImm(pReNative, &off, uImmOp);
             pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
-            pCodeBuf[off++] = Armv8A64MkInstrAddReg(idxRegDst, idxRegDst, idxTmpImmReg, cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
-            iemNativeRegFreeTmpImm(pReNative, idxTmpImmReg);
+            pCodeBuf[off++] = Armv8A64MkInstrAddReg(idxRegDst, idxRegDst, idxRegTmpImm, cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
+            iemNativeRegFreeTmpImm(pReNative, idxRegTmpImm);
         }
     }
@@ -742 +742 @@
         /* Shift the operands up so we can perform a 32-bit operation and get all four flags. */
         uint32_t const cShift = 32 - cOpBits;
-        uint8_t const idxTmpImmReg = iemNativeRegAllocTmpImm(pReNative, &off, uImmOp << cShift);
+        uint8_t const idxRegTmpImm = iemNativeRegAllocTmpImm(pReNative, &off, uImmOp << cShift);
         pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 2);
-        pCodeBuf[off++] = Armv8A64MkInstrAddReg(idxRegDst, idxTmpImmReg, idxRegDstIn, false /*f64Bit*/, true /*fSetFlags*/, cShift);
+        pCodeBuf[off++] = Armv8A64MkInstrAddReg(idxRegDst, idxRegTmpImm, idxRegDstIn, false /*f64Bit*/, true /*fSetFlags*/, cShift);
         pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDst, idxRegDst, cShift, false /*f64Bit*/);
         cOpBits = 32;
-        iemNativeRegFreeTmpImm(pReNative, idxTmpImmReg);
+        iemNativeRegFreeTmpImm(pReNative, idxRegTmpImm);
     }
     IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
@@ -908 +908 @@
                           uint8_t idxVarDst, uint64_t uImmOp, uint8_t idxVarEfl, uint8_t cOpBits, uint8_t cImmBits)
 {
-    RT_NOREF(pReNative, off, idxVarDst, uImmOp, idxVarEfl, cOpBits, cImmBits);
+    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
+
+#ifdef RT_ARCH_AMD64
+    /* On AMD64 we just use the correctly sized SUB instruction to get the right EFLAGS.SF value. */
+    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
+    off = iemNativeEmitAmd64OneByteModRmInstrRIEx(pCodeBuf, off, 0x80, 0x83, 0x81, cOpBits, cImmBits, 5, idxRegDst, uImmOp);
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+    iemNativeVarRegisterRelease(pReNative, idxVarDst);
+
+    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, UINT8_MAX);
+
+#elif defined(RT_ARCH_ARM64)
+    /* On ARM64 we'll need the two input operands as well as the result in order
+       to calculate the right flags, even if we use SUBS and translates NZCV into
+       OF, CF, ZF and SF. */
+    uint8_t const   idxRegDstIn  = iemNativeRegAllocTmp(pReNative, &off);
+    PIEMNATIVEINSTR pCodeBuf     = iemNativeInstrBufEnsure(pReNative, off, 8);
+    off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, idxRegDstIn, idxRegDst);
+    if (cOpBits >= 32)
+    {
+        if (uImmOp <= 0xfffU)
+            pCodeBuf[off++] = Armv8A64MkInstrSubUImm12(idxRegDst, idxRegDst, uImmOp, cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
+        else if (uImmOp <= 0xfff000U && !(uImmOp & 0xfff))
+            pCodeBuf[off++] = Armv8A64MkInstrSubUImm12(idxRegDst, idxRegDst, uImmOp, cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/,
+                                                       true /*fShift12*/);
+        else
+        {
+            uint8_t const idxRegTmpImm = iemNativeRegAllocTmpImm(pReNative, &off, uImmOp);
+            pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
+            pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegDst, idxRegDst, idxRegTmpImm, cOpBits > 32 /*f64Bit*/, true /*fSetFlags*/);
+            iemNativeRegFreeTmpImm(pReNative, idxRegTmpImm);
+        }
+    }
+    else
+    {
+        /* Shift the operands up so we can perform a 32-bit operation and get all four flags. */
+        uint32_t const cShift       = 32 - cOpBits;
+        uint8_t const  idxRegTmpImm = iemNativeRegAllocTmpImm(pReNative, &off, uImmOp);
+        pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 4);
+        pCodeBuf[off++] = Armv8A64MkInstrLslImm(idxRegDstIn, idxRegDstIn, cShift, false /*f64Bit*/);
+        pCodeBuf[off++] = Armv8A64MkInstrSubReg(idxRegDst,   idxRegDstIn, idxRegTmpImm, false /*f64Bit*/, true /*fSetFlags*/, cShift);
+        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDstIn, idxRegDstIn, cShift, false /*f64Bit*/);
+        pCodeBuf[off++] = Armv8A64MkInstrLsrImm(idxRegDst,   idxRegDst,   cShift, false /*f64Bit*/);
+        cOpBits = 32;
+        iemNativeRegFreeTmpImm(pReNative, idxRegTmpImm);
+    }
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, idxVarEfl, UINT8_MAX, cOpBits, idxRegDst,
+                                           idxRegDstIn, UINT8_MAX, true /*fInvertCarry*/, uImmOp);
+
+    iemNativeRegFreeTmp(pReNative, idxRegDstIn);
+    iemNativeVarRegisterRelease(pReNative, idxVarDst);
+    RT_NOREF(cImmBits);
+
+#else
+# error "port me"
+#endif
     return off;
 }