Changeset 103744 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Mar 9, 2024 2:52:46 AM (9 months ago)

Author:

vboxsync

Message:

VMM/IEM: Implemented iemNativeEmit_adc_r_i_efl and enabled it for both hosts. bugref:10376

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAllInstOneByte.cpp.h (modified) (4 diffs)
• target-x86/IEMAllN8veEmit-x86.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h

@@ -1386 +1386 @@
 {
     IEMOP_MNEMONIC2(FIXED, ADC, adc, AL, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
-    IEMOP_BODY_BINARY_AL_Ib(adc, 0);
+    IEMOP_BODY_BINARY_AL_Ib(adc, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 
@@ -1399 +1399 @@
 {
     IEMOP_MNEMONIC2(FIXED, ADC, adc, rAX, Iz, DISOPTYPE_HARMLESS, 0);
-    IEMOP_BODY_BINARY_rAX_Iz_RW(adc, 0);
+    IEMOP_BODY_BINARY_rAX_Iz_RW(adc, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 
@@ -4404 +4404 @@
 {
     IEMOP_MNEMONIC(adc_Eb_Ib, "adc Eb,Ib");
-    IEMOP_BODY_BINARY_Eb_Ib_RW(adc, 0, 0);
+    IEMOP_BODY_BINARY_Eb_Ib_RW(adc, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, 0);
 }
 
@@ -4977 +4977 @@
 {
     IEMOP_MNEMONIC(adc_Ev_Iz, "adc Ev,Iz");
-    IEMOP_BODY_BINARY_Ev_Iz_RW(adc, 0, 0);
+    IEMOP_BODY_BINARY_Ev_Iz_RW(adc, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, 0);
 }
 

trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

@@ -851 +851 @@
                           uint8_t idxVarDst, uint64_t uImmOp, uint8_t idxVarEfl, uint8_t cOpBits, uint8_t cImmBits)
 {
-    RT_NOREF(pReNative, off, idxVarDst, uImmOp, idxVarEfl, cOpBits, cImmBits);
+    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
+    uint8_t const idxRegEfl = iemNativeVarRegisterAcquire(pReNative, idxVarEfl, &off, true /*fInitialized*/);
+
+#ifdef RT_ARCH_AMD64
+    /* On AMD64 we use BT to set EFLAGS.CF and then issue an ADC instruction
+       with matching size to get the correct flags. */
+    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 12);
+
+    off = iemNativeEmitAmd64TwoByteModRmInstrRREx(pCodeBuf, off, 0x0f, 0x0b, 0xba, 32 /*cOpBits*/, 4, idxRegEfl);
+    pCodeBuf[off++] = X86_EFL_CF_BIT;
+
+    off = iemNativeEmitAmd64OneByteModRmInstrRIEx(pCodeBuf, off, 0x80, 0x83, 0x81, cOpBits, cImmBits, 2, idxRegDst, uImmOp);
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+    iemNativeVarRegisterRelease(pReNative, idxVarDst);
+
+    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, UINT8_MAX, idxRegEfl);
+
+#elif defined(RT_ARCH_ARM64)
+    /* On ARM64 we use the RMIF instructions to load PSTATE.CF from idxRegEfl
+       and then ADCS for the calculation.  We need all inputs and result for
+       the two flags (AF,PF) that can't be directly derived from PSTATE.NZCV. */
+    uint8_t const         idxRegDstIn = iemNativeRegAllocTmp(pReNative, &off);
+    uint8_t const         idxRegImm   = iemNativeRegAllocTmpImm(pReNative, &off, uImmOp);
+    PIEMNATIVEINSTR const pCodeBuf    = iemNativeInstrBufEnsure(pReNative, off, 4);
+
+    pCodeBuf[off++] = Armv8A64MkInstrRmif(idxRegEfl, (X86_EFL_CF_BIT - 1) & 63, RT_BIT_32(1) /*fMask=C*/);
+    off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, idxRegDstIn, idxRegDst);
+    if (cOpBits >= 32)
+        pCodeBuf[off++] = Armv8A64MkInstrAdcs(idxRegDst, idxRegDst, idxRegImm, cOpBits > 32 /*f64Bit*/);
+    else
+    {
+        /* Since we're also adding in the carry flag here, shifting operands up
+           doesn't work. So, we have to calculate carry & overflow manually. */
+        pCodeBuf[off++] = Armv8A64MkInstrAdc(idxRegDst, idxRegDst, idxRegImm, false /*f64Bit*/);
+        pCodeBuf[off++] = Armv8A64MkInstrSetF8SetF16(idxRegDst, cOpBits > 8); /* NZ are okay, CV aren't.*/
+    }
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+    iemNativeRegFreeTmp(pReNative, idxRegImm);
+
+    off = iemNativeEmitEFlagsForArithmetic(pReNative, off, UINT8_MAX, idxRegEfl, cOpBits, idxRegDst,
+                                           idxRegDstIn, UINT8_MAX, false /*fInvertCarry*/, uImmOp);
+
+    iemNativeRegFreeTmp(pReNative, idxRegDstIn);
+    if (cOpBits < 32)
+        off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegDst, RT_BIT_32(cOpBits) - 1U);
+    iemNativeVarRegisterRelease(pReNative, idxVarDst);
+    RT_NOREF(cImmBits);
+
+#else
+# error "port me"
+#endif
+    iemNativeVarRegisterRelease(pReNative, idxVarEfl);
     return off;
 }