Index: /trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp	(revision 103749)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp	(revision 103750)
@@ -5745,8 +5745,11 @@
             case kIemNativeGstSimdRegLdStSz_256:
                 off = iemNativeEmitSimdLoadVecRegFromVecRegU256(pReNative, off, idxHstSimdRegDst, idxHstSimdRegSrc);
+                break;
             case kIemNativeGstSimdRegLdStSz_Low128:
                 off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, idxHstSimdRegDst, idxHstSimdRegSrc);
+                break;
             case kIemNativeGstSimdRegLdStSz_High128:
                 off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, idxHstSimdRegDst + 1, idxHstSimdRegSrc + 1);
+                break;
             default:
                 AssertFailedStmt(IEMNATIVE_DO_LONGJMP(pReNative, VERR_IPE_NOT_REACHED_DEFAULT_CASE));
@@ -5977,5 +5980,18 @@
 
 #ifdef RT_ARCH_AMD64
-# error "Port me"
+    if (IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_LO_U128(pReNative, idxGstSimdReg))
+    {
+        Assert(   pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_256
+               || pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_Low128);
+        off = iemNativeEmitSimdStoreVecRegToVCpuU128(pReNative, off, idxHstSimdReg, g_aGstSimdShadowInfo[idxGstSimdReg].offXmm);
+    }
+
+    if (IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_HI_U128(pReNative, idxGstSimdReg))
+    {
+        Assert(   pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_256
+               || pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_High128);
+        AssertReleaseFailed();
+        //off = iemNativeEmitSimdStoreVecRegToVCpuU128(pReNative, off, idxHstSimdReg, g_aGstSimdShadowInfo[idxGstSimdReg].offYmm);
+    }
 #elif defined(RT_ARCH_ARM64)
     /* ASSUMING there are two consecutive host registers to store the potential 256-bit guest register. */
@@ -5991,5 +6007,5 @@
     {
         Assert(   pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_256
-               || pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_Low128);
+               || pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded == kIemNativeGstSimdRegLdStSz_High128);
         off = iemNativeEmitSimdStoreVecRegToVCpuU128(pReNative, off, idxHstSimdReg + 1, g_aGstSimdShadowInfo[idxGstSimdReg].offYmm);
     }
@@ -6394,5 +6410,74 @@
 {
 #  ifdef RT_ARCH_AMD64
-#   error "Port me!"
+    Assert(enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128); /** @todo 256-bit variant. */
+
+    /* movdqa vectmp0, idxSimdReg */
+    off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, IEMNATIVE_SIMD_REG_FIXED_TMP0, idxSimdReg);
+
+    uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 44);
+
+    /* pcmpeqq vectmp0, [gstreg] (ASSUMES SSE4.1) */
+    pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    if (idxSimdReg >= 8)
+        pbCodeBuf[off++] = X86_OP_REX_R;
+    pbCodeBuf[off++] = 0x0f;
+    pbCodeBuf[off++] = 0x38;
+    pbCodeBuf[off++] = 0x29;
+    off = iemNativeEmitGprByVCpuDisp(pbCodeBuf, off, idxSimdReg, g_aGstSimdShadowInfo[enmGstSimdReg].offXmm);
+
+    /* pextrq tmp0, vectmp0, #0 (ASSUMES SSE4.1). */
+    pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    pbCodeBuf[off++] =   X86_OP_REX_W
+                       | (IEMNATIVE_SIMD_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_R)
+                       | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
+    pbCodeBuf[off++] = 0x0f;
+    pbCodeBuf[off++] = 0x3a;
+    pbCodeBuf[off++] = 0x16;
+    pbCodeBuf[off++] = 0xeb;
+    pbCodeBuf[off++] = 0x00;
+
+    /* test tmp0, 0xffffffff. */
+    pbCodeBuf[off++] = X86_OP_REX_W | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
+    pbCodeBuf[off++] = 0xf7;
+    pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, IEMNATIVE_REG_FIXED_TMP0 & 7);
+    pbCodeBuf[off++] = 0xff;
+    pbCodeBuf[off++] = 0xff;
+    pbCodeBuf[off++] = 0xff;
+    pbCodeBuf[off++] = 0xff;
+
+    /* je/jz +1 */
+    pbCodeBuf[off++] = 0x74;
+    pbCodeBuf[off++] = 0x01;
+
+    /* int3 */
+    pbCodeBuf[off++] = 0xcc;
+
+    /* pextrq tmp0, vectmp0, #1 (ASSUMES SSE4.1). */
+    pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    pbCodeBuf[off++] =   X86_OP_REX_W
+                       | (IEMNATIVE_SIMD_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_R)
+                       | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
+    pbCodeBuf[off++] = 0x0f;
+    pbCodeBuf[off++] = 0x3a;
+    pbCodeBuf[off++] = 0x16;
+    pbCodeBuf[off++] = 0xeb;
+    pbCodeBuf[off++] = 0x01;
+
+    /* test tmp0, 0xffffffff. */
+    pbCodeBuf[off++] = X86_OP_REX_W | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
+    pbCodeBuf[off++] = 0xf7;
+    pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, IEMNATIVE_REG_FIXED_TMP0 & 7);
+    pbCodeBuf[off++] = 0xff;
+    pbCodeBuf[off++] = 0xff;
+    pbCodeBuf[off++] = 0xff;
+    pbCodeBuf[off++] = 0xff;
+
+    /* je/jz +1 */
+    pbCodeBuf[off++] = 0x74;
+    pbCodeBuf[off++] = 0x01;
+
+    /* int3 */
+    pbCodeBuf[off++] = 0xcc;
+
 #  elif defined(RT_ARCH_ARM64)
     /* mov vectmp0, [gstreg] */
@@ -6413,5 +6498,4 @@
         /* brk #0x1000+enmGstReg */
         pu32CodeBuf[off++] = Armv8A64MkInstrBrk((uint32_t)enmGstSimdReg | UINT32_C(0x1000));
-        IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     }
 
@@ -6430,5 +6514,4 @@
         /* brk #0x1000+enmGstReg */
         pu32CodeBuf[off++] = Armv8A64MkInstrBrk((uint32_t)enmGstSimdReg | UINT32_C(0x1000));
-        IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     }
 
@@ -6436,4 +6519,6 @@
 #   error "Port me!"
 #  endif
+
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     return off;
 }
@@ -8169,8 +8254,4 @@
     uint8_t const idxLabelRaiseNm = iemNativeLabelCreate(pReNative, kIemNativeLabelType_RaiseNm);
     uint8_t const idxLabelRaiseUd = iemNativeLabelCreate(pReNative, kIemNativeLabelType_RaiseUd);
-
-#if 1
-    off = iemNativeEmitBrk(pReNative, off, 0x4223); /** @todo Test this when AVX gets actually available. */
-#endif
 
     /** @todo r=aeichner Optimize this more later to have less compares and branches,
Index: /trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
===================================================================
--- /trunk/src/VBox/VMM/include/IEMN8veRecompiler.h	(revision 103749)
+++ /trunk/src/VBox/VMM/include/IEMN8veRecompiler.h	(revision 103750)
@@ -173,4 +173,5 @@
 
 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
+#  define IEMNATIVE_SIMD_REG_FIXED_TMP0    5 /* xmm5/ymm5 */
 #  if defined(IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS) || !defined(_MSC_VER)
 #   define IEMNATIVE_SIMD_REG_FIXED_MASK   0
Index: /trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h
===================================================================
--- /trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h	(revision 103749)
+++ /trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h	(revision 103750)
@@ -6831,5 +6831,11 @@
 {
 #ifdef RT_ARCH_AMD64
-    AssertReleaseFailed();
+    /* movdqa mem128, reg128 */ /* ASSUMING an aligned location here. */
+    pCodeBuf[off++] = 0x66;
+    if (iVecReg >= 8)
+        pCodeBuf[off++] = X86_OP_REX_R;
+    pCodeBuf[off++] = 0x0f;
+    pCodeBuf[off++] = 0x7f;
+    off = iemNativeEmitGprByVCpuDisp(pCodeBuf, off, iVecReg, offVCpu);
 #elif defined(RT_ARCH_ARM64)
     off = iemNativeEmitGprByVCpuLdStEx(pCodeBuf, off, iVecReg, offVCpu, kArmv8A64InstrLdStType_St_Vr_128, sizeof(RTUINT128U));
@@ -6849,5 +6855,5 @@
 {
 #ifdef RT_ARCH_AMD64
-    off = iemNativeEmitSimdStoreVecRegToVCpuU128Ex(iemNativeInstrBufEnsure(pReNative, off, 3), off, iVecReg, offVCpu);
+    off = iemNativeEmitSimdStoreVecRegToVCpuU128Ex(iemNativeInstrBufEnsure(pReNative, off, 9), off, iVecReg, offVCpu);
 #elif defined(RT_ARCH_ARM64)
     off = iemNativeEmitSimdStoreVecRegToVCpuU128Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecReg, offVCpu);
@@ -6867,5 +6873,11 @@
 {
 #ifdef RT_ARCH_AMD64
-    AssertReleaseFailed();
+    /* movdqa reg128, mem128 */ /* ASSUMING an aligned location here. */
+    pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    if (iVecReg >= 8)
+        pCodeBuf[off++] = X86_OP_REX_R;
+    pCodeBuf[off++] = 0x0f;
+    pCodeBuf[off++] = 0x6f;
+    off = iemNativeEmitGprByVCpuDisp(pCodeBuf, off, iVecReg, offVCpu);
 #elif defined(RT_ARCH_ARM64)
     off = iemNativeEmitGprByVCpuLdStEx(pCodeBuf, off, iVecReg, offVCpu, kArmv8A64InstrLdStType_Ld_Vr_128, sizeof(RTUINT128U));
@@ -6885,5 +6897,5 @@
 {
 #ifdef RT_ARCH_AMD64
-    off = iemNativeEmitSimdLoadVecRegFromVCpuU128Ex(iemNativeInstrBufEnsure(pReNative, off, 3), off, iVecReg, offVCpu);
+    off = iemNativeEmitSimdLoadVecRegFromVCpuU128Ex(iemNativeInstrBufEnsure(pReNative, off, 9), off, iVecReg, offVCpu);
 #elif defined(RT_ARCH_ARM64)
     off = iemNativeEmitSimdLoadVecRegFromVCpuU128Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecReg, offVCpu);
@@ -6896,4 +6908,5 @@
 
 
+#if 0 /* unused */
 /**
  * Emits a 256-bit vector register store to a VCpu value.
@@ -6914,4 +6927,5 @@
     return off;
 }
+#endif
 
 
@@ -6924,4 +6938,5 @@
 #ifdef RT_ARCH_AMD64
     AssertReleaseFailed();
+    RT_NOREF(pReNative, off, iVecReg, offVCpuLow, offVCpuHigh);
 #elif defined(RT_ARCH_ARM64)
     /* ASSUMES that there are two adjacent 128-bit registers available for the 256-bit value. */
@@ -6972,5 +6987,5 @@
 {
 #ifdef RT_ARCH_AMD64
-    off = iemNativeEmitSimdLoadVecRegFromVecRegU128Ex(iemNativeInstrBufEnsure(pReNative, off, 3), off, iVecRegDst, iVecRegSrc);
+    off = iemNativeEmitSimdLoadVecRegFromVecRegU128Ex(iemNativeInstrBufEnsure(pReNative, off, 5), off, iVecRegDst, iVecRegSrc);
 #elif defined(RT_ARCH_ARM64)
     off = iemNativeEmitSimdLoadVecRegFromVecRegU128Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecRegDst, iVecRegSrc);
@@ -6984,5 +6999,5 @@
 
 /**
- * Emits a gprdst = gprsrc load, 256-bit.
+ * Emits a vecdst = vecsrc load, 256-bit.
  */
 DECL_INLINE_THROW(uint32_t)
@@ -6990,5 +7005,23 @@
 {
 #ifdef RT_ARCH_AMD64
-    AssertReleaseFailed();
+    /* vmovdqa ymm, ymm */
+    uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 5);
+    if (iVecRegDst >= 8 && iVecRegSrc >= 8)
+    {
+        pbCodeBuf[off++] = 0xc4;
+        pbCodeBuf[off++] = 0x41;
+        pbCodeBuf[off++] = 0x7d;
+        pbCodeBuf[off++] = 0x6f;
+        pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iVecRegSrc & 7);
+    }
+    else
+    {
+        pbCodeBuf[off++] = 0xc5;                                               /* Two byte VEX prefix */
+        pbCodeBuf[off++] = (iVecRegSrc >= 8 || iVecRegDst >= 8) ? 0x7d : 0xfd;
+        pbCodeBuf[off++] = iVecRegSrc >= 8 ? 0x7f : 0x6f;
+        pbCodeBuf[off++] =   iVecRegSrc >= 8
+                           ? X86_MODRM_MAKE(X86_MOD_REG, iVecRegSrc & 7, iVecRegDst & 7)
+                           : X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iVecRegSrc & 7);
+    }
 #elif defined(RT_ARCH_ARM64)
     /* ASSUMES that there are two adjacent 128-bit registers available for the 256-bit value. */
