Changeset 103761 in vbox

Timestamp:

Mar 11, 2024 12:07:32 PM (12 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162130

Message:

VMM/IEM: Implement native emitter for IEM_MC_FETCH_XREG_U64(), bugref:10614

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllInstPython.py (modified) (1 diff)
• VMMAll/IEMAllN8veRecompiler.cpp (modified) (2 diffs)
• include/IEMN8veRecompilerEmit.h (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py ¶

@@ -3087 +3087 @@
     'IEM_MC_FETCH_XREG_U16':                                     (McBlock.parseMcGeneric,           False, False, False, ),
     'IEM_MC_FETCH_XREG_U32':                                     (McBlock.parseMcGeneric,           False, False, False, ),
-    'IEM_MC_FETCH_XREG_U64':                                     (McBlock.parseMcGeneric,           False, False, False, ),
+    'IEM_MC_FETCH_XREG_U64':                                     (McBlock.parseMcGeneric,           False, False, True,  ),
     'IEM_MC_FETCH_XREG_U8':                                      (McBlock.parseMcGeneric,           False, False, False, ),
     'IEM_MC_FETCH_XREG_XMM':                                     (McBlock.parseMcGeneric,           False, False, False, ),

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp ¶

@@ -15131 +15131 @@
     off = iemNativeEmitSimdCopyXregU128(pReNative, off, a_iXRegDst, a_iXRegSrc)
 
-/** Emits code for IEM_MC_FETCH_FSW. */
+/** Emits code for IEM_MC_COPY_XREG_U128. */
 DECL_INLINE_THROW(uint32_t)
 iemNativeEmitSimdCopyXregU128(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iXRegDst, uint8_t iXRegSrc)
@@ -15151 +15151 @@
     return off;
 }
-#endif
+
+
+#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
+    off = iemNativeEmitSimdFetchXregU64(pReNative, off, a_u64Value, a_iXReg, a_iQWord)
+
+/** Emits code for IEM_MC_FETCH_XREG_U64. */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmitSimdFetchXregU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iXReg, uint8_t iQWord)
+{
+    IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
+    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxDstVar, sizeof(uint64_t));
+
+    uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg),
+                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly);
+
+    iemNativeVarSetKindToStack(pReNative, idxDstVar);
+    uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
+
+    off = iemNativeEmitSimdLoadGprFromVecRegU64(pReNative, off, idxVarReg, idxSimdRegSrc, iQWord);
+
+    /* Free but don't flush the source register. */
+    iemNativeSimdRegFreeTmp(pReNative, idxSimdRegSrc);
+    iemNativeVarRegisterRelease(pReNative, idxDstVar);
+
+    return off;
+}
+
+
+#endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
 
 

trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h ¶

@@ -7030 +7030 @@
 
 /**
- * Emits a gprdst = gprsrc load, 128-bit.
+ * Emits a vecdst = vecsrc load, 128-bit.
  */
 DECL_INLINE_THROW(uint32_t)
@@ -7085 +7085 @@
 }
 
+
+/**
+ * Emits a gprdst = vecsrc[x] load, 64-bit.
+ */
+DECL_FORCE_INLINE(uint32_t)
+iemNativeEmitSimdLoadGprFromVecRegU64Ex(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iGprDst, uint8_t iVecRegSrc, uint8_t iQWord)
+{
+#ifdef RT_ARCH_AMD64
+    /* pextrq gpr, vecsrc, #iQWord (ASSUMES SSE4.1). */
+    pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    pCodeBuf[off++] =   X86_OP_REX_W
+                      | (iVecRegSrc < 8 ? 0 : X86_OP_REX_R)
+                      | (iGprDst < 8 ? 0 : X86_OP_REX_B);
+    pCodeBuf[off++] = 0x0f;
+    pCodeBuf[off++] = 0x3a;
+    pCodeBuf[off++] = 0x16;
+    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegSrc & 7, iGprDst & 7);
+    pCodeBuf[off++] = iQWord;
+#elif defined(RT_ARCH_ARM64)
+    /* umov gprdst, vecsrc[iQWord] */
+    pCodeBuf[off++] = Armv8A64MkVecInstrUmov(iGprDst, iVecRegSrc, iQWord, kArmv8InstrUmovSz_U64);
+#else
+# error "port me"
+#endif
+    return off;
+}
+
+
+/**
+ * Emits a gprdst = vecsrc[x] load, 64-bit.
+ */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmitSimdLoadGprFromVecRegU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGprDst, uint8_t iVecRegSrc, uint8_t iQWord)
+{
+    Assert(iQWord <= 1);
+
+#ifdef RT_ARCH_AMD64
+    off = iemNativeEmitSimdLoadGprFromVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 7), off, iGprDst, iVecRegSrc, iQWord);
+#elif defined(RT_ARCH_ARM64)
+    off = iemNativeEmitSimdLoadGprFromVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iGprDst, iVecRegSrc, iQWord);
+#else
+# error "port me"
+#endif
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+    return off;
+}
+
 #endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */