Changeset 103782 in vbox

Timestamp:

Mar 11, 2024 5:25:09 PM (12 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162151

Message:

VMM/IEM: Implement emitter for IEM_MC_FETCH_YREG_U64(), bugref:10614

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllInstPython.py (modified) (1 diff)
• VMMAll/IEMAllN8veRecompiler.cpp (modified) (1 diff)
• include/IEMN8veRecompilerEmit.h (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py

@@ -3098 +3098 @@
     'IEM_MC_FETCH_YREG_U256':                                    (McBlock.parseMcGeneric,           False, False, False, ),
     'IEM_MC_FETCH_YREG_U32':                                     (McBlock.parseMcGeneric,           False, False, False, ),
-    'IEM_MC_FETCH_YREG_U64':                                     (McBlock.parseMcGeneric,           False, False, False, ),
+    'IEM_MC_FETCH_YREG_U64':                                     (McBlock.parseMcGeneric,           False, False, True,  ),
     'IEM_MC_FLIP_EFL_BIT':                                       (McBlock.parseMcGeneric,           True,  True,  False, ),
     'IEM_MC_FPU_FROM_MMX_MODE':                                  (McBlock.parseMcGeneric,           True,  True,  False, ),

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp

@@ -15293 +15293 @@
     /* Free but don't flush the source register. */
     iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst);
+    iemNativeVarRegisterRelease(pReNative, idxDstVar);
+
+    return off;
+}
+
+
+#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
+    off = iemNativeEmitSimdFetchYregU64(pReNative, off, a_u64Dst, a_iYRegSrc, 0)
+
+/** Emits code for IEM_MC_FETCH_YREG_U64. */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmitSimdFetchYregU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxDstVar, uint8_t iYReg, uint8_t iQWord)
+{
+    IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
+    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxDstVar, sizeof(uint64_t));
+
+    uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg),
+                                                                            iQWord >= 2
+                                                                          ? kIemNativeGstSimdRegLdStSz_High128
+                                                                          : kIemNativeGstSimdRegLdStSz_Low128,
+                                                                          kIemNativeGstRegUse_ReadOnly);
+
+    iemNativeVarSetKindToStack(pReNative, idxDstVar);
+    uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
+
+    off = iemNativeEmitSimdLoadGprFromVecRegU64(pReNative, off, idxVarReg, idxSimdRegSrc, iQWord);
+
+    /* Free but don't flush the source register. */
+    iemNativeSimdRegFreeTmp(pReNative, idxSimdRegSrc);
     iemNativeVarRegisterRelease(pReNative, idxDstVar);
 

trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h

@@ -7093 +7093 @@
 {
 #ifdef RT_ARCH_AMD64
-    /* pextrq gpr, vecsrc, #iQWord (ASSUMES SSE4.1). */
-    pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
-    pCodeBuf[off++] =   X86_OP_REX_W
-                      | (iVecRegSrc < 8 ? 0 : X86_OP_REX_R)
-                      | (iGprDst < 8 ? 0 : X86_OP_REX_B);
-    pCodeBuf[off++] = 0x0f;
-    pCodeBuf[off++] = 0x3a;
-    pCodeBuf[off++] = 0x16;
-    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegSrc & 7, iGprDst & 7);
-    pCodeBuf[off++] = iQWord;
+    if (iQWord >= 2)
+    {
+        /** @todo Currently not used. */
+        AssertReleaseFailed();
+    }
+    else
+    {
+        /* pextrq gpr, vecsrc, #iQWord (ASSUMES SSE4.1). */
+        pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+        pCodeBuf[off++] =   X86_OP_REX_W
+                          | (iVecRegSrc < 8 ? 0 : X86_OP_REX_R)
+                          | (iGprDst < 8 ? 0 : X86_OP_REX_B);
+        pCodeBuf[off++] = 0x0f;
+        pCodeBuf[off++] = 0x3a;
+        pCodeBuf[off++] = 0x16;
+        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegSrc & 7, iGprDst & 7);
+        pCodeBuf[off++] = iQWord;
+    }
 #elif defined(RT_ARCH_ARM64)
     /* umov gprdst, vecsrc[iQWord] */
@@ -7119 +7127 @@
 iemNativeEmitSimdLoadGprFromVecRegU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGprDst, uint8_t iVecRegSrc, uint8_t iQWord)
 {
-    Assert(iQWord <= 1);
+    Assert(iQWord <= 3);
 
 #ifdef RT_ARCH_AMD64
     off = iemNativeEmitSimdLoadGprFromVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 7), off, iGprDst, iVecRegSrc, iQWord);
 #elif defined(RT_ARCH_ARM64)
-    off = iemNativeEmitSimdLoadGprFromVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iGprDst, iVecRegSrc, iQWord);
+    /* ASSUMES that there are two adjacent 128-bit registers available for the 256-bit value. */
+    Assert(!(iVecRegSrc & 0x1));
+    /* Need to access the "high" 128-bit vector register. */
+    if (iQWord >= 2)
+        off = iemNativeEmitSimdLoadGprFromVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iGprDst, iVecRegSrc + 1, iQWord - 2);
+    else
+        off = iemNativeEmitSimdLoadGprFromVecRegU64Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iGprDst, iVecRegSrc,     iQWord);
 #else
 # error "port me"