Changeset 103800 in vbox

Timestamp:

Mar 11, 2024 10:31:33 PM (9 months ago)

Author:

vboxsync

Message:

VMM/IEM: Implemented iemNativeEmit_or_r_i_efl and enabled it for both hosts. bugref:10376

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAllInstOneByte.cpp.h (modified) (5 diffs)
• target-x86/IEMAllN8veEmit-x86.h (modified) (3 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h

@@ -1230 +1230 @@
     IEMOP_MNEMONIC2(FIXED, OR, or, AL, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
-    IEMOP_BODY_BINARY_AL_Ib(or, 0);
+    IEMOP_BODY_BINARY_AL_Ib(or, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 
@@ -1250 +1250 @@
     IEMOP_MNEMONIC2(FIXED, OR, or, rAX, Iz, DISOPTYPE_HARMLESS, 0);
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
-    IEMOP_BODY_BINARY_rAX_Iz_RW(or, 0);
+    IEMOP_BODY_BINARY_rAX_Iz_RW(or, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 
@@ -4392 +4392 @@
 {
     IEMOP_MNEMONIC(or_Eb_Ib, "or Eb,Ib");
-    IEMOP_BODY_BINARY_Eb_Ib_RW(or, 0, 0);
+    IEMOP_BODY_BINARY_Eb_Ib_RW(or, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, 0);
 }
 
@@ -4965 +4965 @@
 {
     IEMOP_MNEMONIC(or_Ev_Iz, "or Ev,Iz");
-    IEMOP_BODY_BINARY_Ev_Iz_RW(or, 0, 0);
+    IEMOP_BODY_BINARY_Ev_Iz_RW(or, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, 0);
 }
 
@@ -5523 +5523 @@
 {
     IEMOP_MNEMONIC(or_Ev_Ib, "or Ev,Ib");
-    IEMOP_BODY_BINARY_Ev_Ib_RW(or, 0, 0);
+    IEMOP_BODY_BINARY_Ev_Ib_RW(or, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, 0);
 }
 

trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

@@ -508 +508 @@
 
 #elif defined(RT_ARCH_ARM64)
-    /* On ARM64 we use 32-bit AND for the 8-bit and 16-bit bit ones. */
+    /* On ARM64 we use 32-bit AND for the 8-bit and 16-bit bit ones, and of
+       course the immediate variant when possible to save a register load. */
     uint32_t uImmSizeLen, uImmRotations;
     if (  cOpBits > 32
@@ -606 +607 @@
 
 #elif defined(RT_ARCH_ARM64)
-    /* On ARM64 we use 32-bit AND for the 8-bit and 16-bit bit ones.  We also
-       need to keep the result in order to calculate the flags. */
+    /* On ARM64 we use 32-bit AND for the 8-bit and 16-bit bit ones, and of
+       course the immediate variant when possible to save a register load.
+       We also need to keep the result in order to calculate the flags. */
     uint8_t const         idxRegResult = iemNativeRegAllocTmp(pReNative, &off);
     uint32_t uImmSizeLen, uImmRotations;
@@ -688 +690 @@
                           uint8_t idxVarDst, uint64_t uImmOp, uint8_t idxVarEfl, uint8_t cOpBits, uint8_t cImmBits)
 {
-    RT_NOREF(pReNative, off, idxVarDst, uImmOp, idxVarEfl, cOpBits, cImmBits);
+    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
+#ifdef RT_ARCH_AMD64
+    /* On AMD64 we just use the correctly size OR instruction harvest the EFLAGS. */
+    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
+    off = iemNativeEmitAmd64OneByteModRmInstrRIEx(pCodeBuf, off, 0x80, 0x83, 0x81, cOpBits, cImmBits, 1, idxRegDst, uImmOp);
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+    off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl);
+
+#elif defined(RT_ARCH_ARM64)
+    /* On ARM64 we use 32-bit OR for the 8-bit and 16-bit bit ones, and of
+       course the immediate variant when possible to save a register load.  */
+    uint32_t uImmSizeLen, uImmRotations;
+    if (  cOpBits > 32
+        ? Armv8A64ConvertMask64ToImmRImmS(uImmOp, &uImmSizeLen, &uImmRotations)
+        : Armv8A64ConvertMask32ToImmRImmS(uImmOp, &uImmSizeLen, &uImmRotations))
+    {
+        PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
+        pCodeBuf[off++] = Armv8A64MkInstrOrrImm(idxRegDst, idxRegDst, uImmSizeLen, uImmRotations, cOpBits > 32 /*f64Bit*/);
+    }
+    else
+    {
+        uint8_t const idxRegTmpImm = iemNativeRegAllocTmpImm(pReNative, &off, uImmOp);
+        PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
+        pCodeBuf[off++] = Armv8A64MkInstrOrr(idxRegDst, idxRegDst, idxRegTmpImm, cOpBits > 32 /*f64Bit*/);
+        iemNativeRegFreeTmpImm(pReNative, idxRegTmpImm);
+    }
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+    off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
+    RT_NOREF_PV(cImmBits)
+
+#else
+# error "Port me"
+#endif
+    iemNativeVarRegisterRelease(pReNative, idxVarDst);
     return off;
 }