Changeset 103801 in vbox

Timestamp:

Mar 11, 2024 10:36:07 PM (12 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162170

Message:

VMM/IEM: Implemented iemNativeEmit_xor_r_i_efl and enabled it for both hosts. bugref:10376

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAllInstOneByte.cpp.h (modified) (5 diffs)
• target-x86/IEMAllN8veEmit-x86.h (modified) (8 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h

@@ -1846 +1846 @@
     IEMOP_MNEMONIC2(FIXED, XOR, xor, AL, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
-    IEMOP_BODY_BINARY_AL_Ib(xor, 0);
+    IEMOP_BODY_BINARY_AL_Ib(xor, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 
@@ -1859 +1859 @@
     IEMOP_MNEMONIC2(FIXED, XOR, xor, rAX, Iz, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZES);
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);
-    IEMOP_BODY_BINARY_rAX_Iz_RW(xor, 0);
+    IEMOP_BODY_BINARY_rAX_Iz_RW(xor, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 
@@ -4452 +4452 @@
 {
     IEMOP_MNEMONIC(xor_Eb_Ib, "xor Eb,Ib");
-    IEMOP_BODY_BINARY_Eb_Ib_RW(xor, 0, 0);
+    IEMOP_BODY_BINARY_Eb_Ib_RW(xor, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, 0);
 }
 
@@ -5025 +5025 @@
 {
     IEMOP_MNEMONIC(xor_Ev_Iz, "xor Ev,Iz");
-    IEMOP_BODY_BINARY_Ev_Iz_RW(xor, 0, 0);
+    IEMOP_BODY_BINARY_Ev_Iz_RW(xor, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, 0);
 }
 
@@ -5583 +5583 @@
 {
     IEMOP_MNEMONIC(xor_Ev_Ib, "xor Ev,Ib");
-    IEMOP_BODY_BINARY_Ev_Ib_RW(xor, 0, 0);
+    IEMOP_BODY_BINARY_Ev_Ib_RW(xor, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64, 0);
 }
 

trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

@@ -467 +467 @@
     uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/);
 #ifdef RT_ARCH_AMD64
-    /* On AMD64 we just use the correctly size AND instruction harvest the EFLAGS. */
+    /* On AMD64 we just use the correctly sized AND instruction harvest the EFLAGS. */
     off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
                                                   0x22, 0x23, cOpBits, idxRegDst, idxRegSrc);
@@ -500 +500 @@
     uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
 #ifdef RT_ARCH_AMD64
-    /* On AMD64 we just use the correctly size AND instruction harvest the EFLAGS. */
+    /* On AMD64 we just use the correctly sized AND instruction harvest the EFLAGS. */
     PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
     off = iemNativeEmitAmd64OneByteModRmInstrRIEx(pCodeBuf, off, 0x80, 0x83, 0x81, cOpBits, cImmBits, 4, idxRegDst, uImmOp);
@@ -556 +556 @@
                                        : iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/);
 #ifdef RT_ARCH_AMD64
-    /* On AMD64 we just use the correctly size TEST instruction harvest the EFLAGS. */
+    /* On AMD64 we just use the correctly sized TEST instruction harvest the EFLAGS. */
     off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
                                                   0x84, 0x85, cOpBits, idxRegSrc, idxRegDst);
@@ -598 +598 @@
     uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
 #ifdef RT_ARCH_AMD64
-    /* On AMD64 we just use the correctly size AND instruction harvest the EFLAGS. */
+    /* On AMD64 we just use the correctly sized AND instruction harvest the EFLAGS. */
     PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
     off = iemNativeEmitAmd64OneByteModRmInstrRIEx(pCodeBuf, off, 0xf6, 0xcc, 0xf7, cOpBits, cImmBits, 0, idxRegDst, uImmOp);
@@ -658 +658 @@
     uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/);
 #ifdef RT_ARCH_AMD64
-    /* On AMD64 we just use the correctly size OR instruction harvest the EFLAGS. */
+    /* On AMD64 we just use the correctly sized OR instruction harvest the EFLAGS. */
     off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
                                                   0x0a, 0x0b, cOpBits, idxRegDst, idxRegSrc);
@@ -692 +692 @@
     uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
 #ifdef RT_ARCH_AMD64
-    /* On AMD64 we just use the correctly size OR instruction harvest the EFLAGS. */
+    /* On AMD64 we just use the correctly sized OR instruction harvest the EFLAGS. */
     PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
     off = iemNativeEmitAmd64OneByteModRmInstrRIEx(pCodeBuf, off, 0x80, 0x83, 0x81, cOpBits, cImmBits, 1, idxRegDst, uImmOp);
@@ -741 +741 @@
     uint8_t const idxRegSrc = iemNativeVarRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/);
 #ifdef RT_ARCH_AMD64
-    /* On AMD64 we just use the correctly size OR instruction harvest the EFLAGS. */
+    /* On AMD64 we just use the correctly sized OR instruction harvest the EFLAGS. */
     off = iemNativeEmitAmd64OneByteModRmInstrRREx(iemNativeInstrBufEnsure(pReNative, off, 4), off,
                                                   0x32, 0x33, cOpBits, idxRegDst, idxRegSrc);
@@ -773 +773 @@
                           uint8_t idxVarDst, uint64_t uImmOp, uint8_t idxVarEfl, uint8_t cOpBits, uint8_t cImmBits)
 {
-    RT_NOREF(pReNative, off, idxVarDst, uImmOp, idxVarEfl, cOpBits, cImmBits);
+    uint8_t const idxRegDst = iemNativeVarRegisterAcquire(pReNative, idxVarDst, &off, true /*fInitialized*/);
+#ifdef RT_ARCH_AMD64
+    /* On AMD64 we just use the correctly sized XOR instruction harvest the EFLAGS. */
+    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 8);
+    off = iemNativeEmitAmd64OneByteModRmInstrRIEx(pCodeBuf, off, 0x80, 0x83, 0x81, cOpBits, cImmBits, 6, idxRegDst, uImmOp);
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+    off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl);
+
+#elif defined(RT_ARCH_ARM64)
+    /* On ARM64 we use 32-bit OR for the 8-bit and 16-bit bit ones, and of
+       course the immediate variant when possible to save a register load.  */
+    uint32_t uImmSizeLen, uImmRotations;
+    if (  cOpBits > 32
+        ? Armv8A64ConvertMask64ToImmRImmS(uImmOp, &uImmSizeLen, &uImmRotations)
+        : Armv8A64ConvertMask32ToImmRImmS(uImmOp, &uImmSizeLen, &uImmRotations))
+    {
+        PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
+        pCodeBuf[off++] = Armv8A64MkInstrEorImm(idxRegDst, idxRegDst, uImmSizeLen, uImmRotations, cOpBits > 32 /*f64Bit*/);
+    }
+    else
+    {
+        uint8_t const idxRegTmpImm = iemNativeRegAllocTmpImm(pReNative, &off, uImmOp);
+        PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
+        pCodeBuf[off++] = Armv8A64MkInstrEor(idxRegDst, idxRegDst, idxRegTmpImm, cOpBits > 32 /*f64Bit*/);
+        iemNativeRegFreeTmpImm(pReNative, idxRegTmpImm);
+    }
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+
+    off = iemNativeEmitEFlagsForLogical(pReNative, off, idxVarEfl, cOpBits, idxRegDst);
+    RT_NOREF_PV(cImmBits)
+
+#else
+# error "Port me"
+#endif
+    iemNativeVarRegisterRelease(pReNative, idxVarDst);
     return off;
 }