Index: /trunk/include/iprt/x86.h
===================================================================
--- /trunk/include/iprt/x86.h	(revision 103820)
+++ /trunk/include/iprt/x86.h	(revision 103821)
@@ -5190,19 +5190,26 @@
 #define X86_OP_VEX3_BYTE1_R             RT_BIT(7)
 
-#define X86_OP_VEX3_BYTE3_P_MASK        0x3
-# define X86_OP_VEX3_BYTE3_P_NO_PRF     0
-# define X86_OP_VEX3_BYTE3_P_066H       1
-# define X86_OP_VEX3_BYTE3_P_0F3H       2
-# define X86_OP_VEX3_BYTE3_P_0F2H       3
-#define X86_OP_VEX3_BYTE3_L             RT_BIT(2)
-#define X86_OP_VEX3_BYTE3_VVVV_MASK     0x78
-#define X86_OP_VEX3_BYTE3_VVVV_SHIFT    3
-#define X86_OP_VEX3_BYTE3_W             RT_BIT(7)
-
-#define X86_OP_VEX3_BYTE3_MAKE(a_f64BitOpSz, a_iSrcReg, a_f256BitAvx, a_fPrf) \
-    (  ((a_f64BitOpSz) ? X86_OP_VEX3_BYTE3_W : 0) \
-     | (~((uint8_t)(a_iSrcReg) & 0xf)) \
-     | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE3_L : 0) \
-     | ((a_fPrf) & X86_OP_VEX3_BYTE3_P_MASK))
+#define X86_OP_VEX3_BYTE2_P_MASK        0x3
+# define X86_OP_VEX3_BYTE2_P_NO_PRF     0
+# define X86_OP_VEX3_BYTE2_P_066H       1
+# define X86_OP_VEX3_BYTE2_P_0F3H       2
+# define X86_OP_VEX3_BYTE2_P_0F2H       3
+#define X86_OP_VEX3_BYTE2_L             RT_BIT(2)
+#define X86_OP_VEX3_BYTE2_VVVV_MASK     0x78
+#define X86_OP_VEX3_BYTE2_VVVV_SHIFT    3
+#define X86_OP_VEX3_BYTE2_VVVV_NONE     15
+#define X86_OP_VEX3_BYTE2_W             RT_BIT(7)
+
+#define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSz, a_iSrcReg, a_f256BitAvx, a_fPrf) \
+    (  ((a_f64BitOpSz) ? X86_OP_VEX3_BYTE2_W : 0) \
+     | (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
+     | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
+     | ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
+
+#define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSz, a_f256BitAvx, a_fPrf) \
+    (  ((a_f64BitOpSz) ? X86_OP_VEX3_BYTE2_W : 0) \
+     | (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
+     | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
+     | ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
 /** @} */
 
Index: /trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h
===================================================================
--- /trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h	(revision 103820)
+++ /trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h	(revision 103821)
@@ -6967,5 +6967,5 @@
     else
         pCodeBuf[off++] = 0xe3;
-    pCodeBuf[off++] = X86_OP_VEX3_BYTE3_MAKE(false, iVecReg, true, X86_OP_VEX3_BYTE3_P_066H);
+    pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE(false, iVecReg, true, X86_OP_VEX3_BYTE2_P_066H);
     pCodeBuf[off++] = 0x38;
     off = iemNativeEmitGprByVCpuDisp(pCodeBuf, off, iVecReg, offVCpu);
@@ -7418,53 +7418,14 @@
     pCodeBuf[off++] = 0x00;
 
-    if (f256Bit)
-    {
-        /* When broadcasting the entire ymm register we can use vbroadcastss now. */
-        /* vbroadcastss ymm, xmm (ASSUMES AVX2). */
-        pCodeBuf[off++] = X86_OP_VEX3;
-        pCodeBuf[off++] =   X86_OP_VEX3_BYTE1_X
-                          | 0x02                 /* opcode map. */
-                          | (  iVecRegDst >= 8
-                             ? 0
-                             : X86_OP_VEX3_BYTE1_B | X86_OP_VEX3_BYTE1_R);
-        pCodeBuf[off++] = 0x7d;
-        pCodeBuf[off++] = 0x18;
-        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iVecRegDst & 7);
-    }
-    else
-    {
-        /* pinsrd vecdst, gpr, #1 (ASSUMES SSE4.1). */
-        pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
-        if (iVecRegDst >= 8 || iGprSrc >= 8)
-            pCodeBuf[off++] =   (iVecRegDst < 8 ? 0 : X86_OP_REX_R)
-                              | (iGprSrc < 8 ? 0 : X86_OP_REX_B);
-        pCodeBuf[off++] = 0x0f;
-        pCodeBuf[off++] = 0x3a;
-        pCodeBuf[off++] = 0x22;
-        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iGprSrc & 7);
-        pCodeBuf[off++] = 0x01;
-
-        /* pinsrd vecdst, gpr, #2 (ASSUMES SSE4.1). */
-        pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
-        if (iVecRegDst >= 8 || iGprSrc >= 8)
-            pCodeBuf[off++] =   (iVecRegDst < 8 ? 0 : X86_OP_REX_R)
-                              | (iGprSrc < 8 ? 0 : X86_OP_REX_B);
-        pCodeBuf[off++] = 0x0f;
-        pCodeBuf[off++] = 0x3a;
-        pCodeBuf[off++] = 0x22;
-        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iGprSrc & 7);
-        pCodeBuf[off++] = 0x02;
-
-        /* pinsrd vecdst, gpr, #3 (ASSUMES SSE4.1). */
-        pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
-        if (iVecRegDst >= 8 || iGprSrc >= 8)
-            pCodeBuf[off++] =   (iVecRegDst < 8 ? 0 : X86_OP_REX_R)
-                              | (iGprSrc < 8 ? 0 : X86_OP_REX_B);
-        pCodeBuf[off++] = 0x0f;
-        pCodeBuf[off++] = 0x3a;
-        pCodeBuf[off++] = 0x22;
-        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iGprSrc & 7);
-        pCodeBuf[off++] = 0x03;
-    }
+    /* vpbroadcastd {y,x}mm, xmm (ASSUMES AVX2). */
+    pCodeBuf[off++] = X86_OP_VEX3;
+    pCodeBuf[off++] =   X86_OP_VEX3_BYTE1_X
+                      | 0x02                 /* opcode map. */
+                      | (  iVecRegDst >= 8
+                         ? 0
+                         : X86_OP_VEX3_BYTE1_B | X86_OP_VEX3_BYTE1_R);
+    pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(false, f256Bit, X86_OP_VEX3_BYTE2_P_066H);
+    pCodeBuf[off++] = 0x58;
+    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iVecRegDst & 7);
 #elif defined(RT_ARCH_ARM64)
     /* ASSUMES that there are two adjacent 128-bit registers available for the 256-bit value. */
@@ -7489,5 +7450,5 @@
 {
 #ifdef RT_ARCH_AMD64
-    off = iemNativeEmitSimdBroadcastGprToVecRegU32Ex(iemNativeInstrBufEnsure(pReNative, off, f256Bit ? 12 : 28), off, iVecRegDst, iGprSrc, f256Bit);
+    off = iemNativeEmitSimdBroadcastGprToVecRegU32Ex(iemNativeInstrBufEnsure(pReNative, off, 12), off, iVecRegDst, iGprSrc, f256Bit);
 #elif defined(RT_ARCH_ARM64)
     off = iemNativeEmitSimdBroadcastGprToVecRegU32Ex(iemNativeInstrBufEnsure(pReNative, off, f256Bit ? 2 : 1), off, iVecRegDst, iGprSrc, f256Bit);
@@ -7521,31 +7482,14 @@
     pCodeBuf[off++] = 0x00;
 
-    if (f256Bit)
-    {
-        /* When broadcasting the entire ymm register we can use vbroadcastsd now. */
-        /* vbroadcastsd ymm, xmm (ASSUMES AVX2). */
-        pCodeBuf[off++] = X86_OP_VEX3;
-        pCodeBuf[off++] =   X86_OP_VEX3_BYTE1_X
-                          | 0x02                 /* opcode map. */
-                          | (  iVecRegDst >= 8
-                             ? 0
-                             : X86_OP_VEX3_BYTE1_B | X86_OP_VEX3_BYTE1_R);
-        pCodeBuf[off++] = 0x7d;
-        pCodeBuf[off++] = 0x19;
-        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iVecRegDst & 7);
-    }
-    else
-    {
-        /* pinsrq vecdst, gpr, #1 (ASSUMES SSE4.1). */
-        pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
-        pCodeBuf[off++] =   X86_OP_REX_W
-                          | (iVecRegDst < 8 ? 0 : X86_OP_REX_R)
-                          | (iGprSrc < 8 ? 0 : X86_OP_REX_B);
-        pCodeBuf[off++] = 0x0f;
-        pCodeBuf[off++] = 0x3a;
-        pCodeBuf[off++] = 0x22;
-        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iGprSrc & 7);
-        pCodeBuf[off++] = 0x01;
-    }
+    /* vpbroadcastq {y,x}mm, xmm (ASSUMES AVX2). */
+    pCodeBuf[off++] = X86_OP_VEX3;
+    pCodeBuf[off++] =   X86_OP_VEX3_BYTE1_X
+                      | 0x02                 /* opcode map. */
+                      | (  iVecRegDst >= 8
+                         ? 0
+                         : X86_OP_VEX3_BYTE1_B | X86_OP_VEX3_BYTE1_R);
+    pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(false, f256Bit, X86_OP_VEX3_BYTE2_P_066H);
+    pCodeBuf[off++] = 0x59;
+    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iVecRegDst & 7);
 #elif defined(RT_ARCH_ARM64)
     /* ASSUMES that there are two adjacent 128-bit registers available for the 256-bit value. */
