Changeset 103822 in vbox

Timestamp:

Mar 13, 2024 11:32:12 AM (12 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162191

Message:

VMM/IEM: Implement native emitter for IEM_MC_STORE_YREG_U32_ZX_VLMAX(), bugref:10614

Location:

trunk

Files:

• include/iprt/x86.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/IEMAllInstPython.py (modified) (1 diff)
• src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h (modified) (1 diff)
• src/VBox/VMM/include/IEMN8veRecompilerEmit.h (modified) (1 diff)

trunk/include/iprt/x86.h

@@ -5183 +5183 @@
 /** @} */
 
+/** @name X86_OP_VEX2_XXX - 2-byte VEX prefix helpers.
+ * @{ */
+#define X86_OP_VEX2_BYTE1_P_MASK        0x3
+# define X86_OP_VEX2_BYTE1_P_NO_PRF     0
+# define X86_OP_VEX2_BYTE1_P_066H       1
+# define X86_OP_VEX2_BYTE1_P_0F3H       2
+# define X86_OP_VEX2_BYTE1_P_0F2H       3
+#define X86_OP_VEX2_BYTE1_L             RT_BIT(2)
+#define X86_OP_VEX2_BYTE1_VVVV_MASK     0x78
+#define X86_OP_VEX2_BYTE1_VVVV_SHIFT    3
+#define X86_OP_VEX2_BYTE1_VVVV_NONE     15
+#define X86_OP_VEX2_BYTE1_R             RT_BIT(7)
+
+#define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \
+    (  ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
+     | (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
+     | ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
+     | ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
+/** @} */
+
 /** @name X86_OP_VEX3_XXX - 3-byte VEX prefix helpers.
  * @{ */

trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py

@@ -3343 +3343 @@
     'IEM_MC_STORE_YREG_U128_ZX_VLMAX':                           (McBlock.parseMcGeneric,           True,  True,  False, ),
     'IEM_MC_STORE_YREG_U256_ZX_VLMAX':                           (McBlock.parseMcGeneric,           True,  True,  False, ),
-    'IEM_MC_STORE_YREG_U32_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True,  True,  False, ),
+    'IEM_MC_STORE_YREG_U32_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
     'IEM_MC_STORE_YREG_U64_ZX_VLMAX':                            (McBlock.parseMcGeneric,           True,  True,  False, ),
     'IEM_MC_SUB_GREG_U16':                                       (McBlock.parseMcGeneric,           True,  True,  True,  ),

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h

@@ -6941 +6941 @@
 }
 
+
+#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
+    off = iemNativeEmitSimdStoreYregU32ZxVlmax(pReNative, off, a_iYRegDst, a_u32Src)
+
+/** Emits code for IEM_MC_STORE_YREG_U32_ZX_VLMAX. */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmitSimdStoreYregU32ZxVlmax(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iYReg, uint8_t idxSrcVar)
+{
+    IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxSrcVar);
+    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxSrcVar, sizeof(uint32_t));
+
+    uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYReg),
+                                                                          kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite);
+
+    uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxSrcVar, &off);
+
+    off = iemNativeEmitSimdZeroVecRegU256(pReNative, off, idxSimdRegDst);
+    off = iemNativeEmitSimdStoreGprToVecRegU32(pReNative, off, idxSimdRegDst, idxVarReg, 0 /*iDWord*/);
+    IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_LO_U128(pReNative, iYReg);
+    IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_HI_U128(pReNative, iYReg);
+
+    /* Free but don't flush the source register. */
+    iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst);
+    iemNativeVarRegisterRelease(pReNative, idxSrcVar);
+
+    return off;
+}
+
 #endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
 

trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h

@@ -7398 +7398 @@
 
 /**
+ * Emits a vecdst[0:255] = 0 store.
+ */
+DECL_FORCE_INLINE(uint32_t)
+iemNativeEmitSimdZeroVecRegU256Ex(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iVecReg)
+{
+#ifdef RT_ARCH_AMD64
+    /* vpxor ymm, ymm, ymm */
+    if (iVecReg < 8)
+    {
+        pCodeBuf[off++] = X86_OP_VEX2;
+        pCodeBuf[off++] = X86_OP_VEX2_BYTE1_MAKE(false, iVecReg, true, X86_OP_VEX3_BYTE2_P_066H);
+    }
+    else
+    {
+        pCodeBuf[off++] = X86_OP_VEX3;
+        pCodeBuf[off++] = X86_OP_VEX3_BYTE1_X | 0x01;
+        pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE(false, iVecReg, true, X86_OP_VEX3_BYTE2_P_066H);
+    }
+    pCodeBuf[off++] = 0xef;
+    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecReg & 7, iVecReg & 7);
+#elif defined(RT_ARCH_ARM64)
+    /* ASSUMES that there are two adjacent 128-bit registers available for the 256-bit value. */
+    Assert(!(iVecReg & 0x1));
+    /* eor vecreg, vecreg, vecreg */
+    pCodeBuf[off++] = Armv8A64MkVecInstrEor(iVecReg,     iVecReg,     iVecReg);
+    pCodeBuf[off++] = Armv8A64MkVecInstrEor(iVecReg + 1, iVecReg + 1, iVecReg + 1);
+#else
+# error "port me"
+#endif
+    return off;
+}
+
+
+/**
+ * Emits a vecdst[0:255] = 0 store.
+ */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmitSimdZeroVecRegU256(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iVecReg)
+{
+#ifdef RT_ARCH_AMD64
+    off = iemNativeEmitSimdZeroVecRegU256Ex(iemNativeInstrBufEnsure(pReNative, off, 5), off, iVecReg);
+#elif defined(RT_ARCH_ARM64)
+    off = iemNativeEmitSimdZeroVecRegU256Ex(iemNativeInstrBufEnsure(pReNative, off, 2), off, iVecReg);
+#else
+# error "port me"
+#endif
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+    return off;
+}
+
+
+/**
  * Emits a vecdst = gprsrc broadcast, 32-bit.
  */