Changeset 103834 in vbox

Timestamp:

Mar 13, 2024 3:32:59 PM (13 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162204

Message:

VMM/IEM: Implement native emitter for IEM_MC_CLEAR_XREG_U32_MASK(), bugref:10614

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllInstPython.py (modified) (1 diff)
• VMMAll/IEMAllN8veRecompFuncs.h (modified) (1 diff)
• include/IEMN8veRecompilerEmit.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py

@@ -2997 +2997 @@
     'IEM_MC_CLEAR_FSW_EX':                                       (McBlock.parseMcGeneric,           True,  True,  False, ),
     'IEM_MC_CLEAR_HIGH_GREG_U64':                                (McBlock.parseMcGeneric,           True,  True,  True,  ),
-    'IEM_MC_CLEAR_XREG_U32_MASK':                                (McBlock.parseMcGeneric,           True,  True,  False, ),
+    'IEM_MC_CLEAR_XREG_U32_MASK':                                (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
     'IEM_MC_CLEAR_YREG_128_UP':                                  (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
     'IEM_MC_COMMIT_EFLAGS':                                      (McBlock.parseMcGeneric,           True,  True,  True,  ),

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h

@@ -7105 +7105 @@
 }
 
+
+#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
+    off = iemNativeEmitSimdClearXregU32Mask(pReNative, off, a_iXReg, a_bMask)
+
+
+/** Emits code for IEM_MC_CLEAR_XREG_U32_MASK. */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmitSimdClearXregU32Mask(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iXReg, uint8_t bImm8Mask)
+{
+    uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg),
+                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate);
+
+    /** @todo r=aeichner For certain bit combinations we could reduce the number of emitted instructions. */
+    if (bImm8Mask & RT_BIT(0))
+        off = iemNativeEmitSimdZeroVecRegElemU32(pReNative, off, idxSimdRegDst, 0 /*iDWord*/);
+    if (bImm8Mask & RT_BIT(1))
+        off = iemNativeEmitSimdZeroVecRegElemU32(pReNative, off, idxSimdRegDst, 1 /*iDWord*/);
+    if (bImm8Mask & RT_BIT(2))
+        off = iemNativeEmitSimdZeroVecRegElemU32(pReNative, off, idxSimdRegDst, 2 /*iDWord*/);
+    if (bImm8Mask & RT_BIT(3))
+        off = iemNativeEmitSimdZeroVecRegElemU32(pReNative, off, idxSimdRegDst, 3 /*iDWord*/);
+    IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_LO_U128(pReNative, iXReg);
+
+    /* Free but don't flush the destination register. */
+    iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst);
+
+    return off;
+}
+
 #endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
 

trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h

@@ -7538 +7538 @@
 
 /**
+ * Emits a vecdst.au32[iDWord] = 0 store.
+ */
+DECL_FORCE_INLINE(uint32_t)
+iemNativeEmitSimdZeroVecRegElemU32Ex(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iVecReg, uint8_t iDWord)
+{
+    Assert(iDWord <= 7);
+
+#ifdef RT_ARCH_AMD64
+    /*
+     * xor tmp0, tmp0
+     * pinsrd xmm, tmp0, iDword
+     */
+    if (IEMNATIVE_REG_FIXED_TMP0 >= 8)
+        pCodeBuf[off++] = X86_OP_REX_R | X86_OP_REX_B;
+    pCodeBuf[off++] = 0x33;
+    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, IEMNATIVE_REG_FIXED_TMP0 & 7, IEMNATIVE_REG_FIXED_TMP0 & 7);
+    off = iemNativeEmitSimdStoreGprToVecRegU32Ex(&pCodeBuf[off], off, iVecReg, IEMNATIVE_REG_FIXED_TMP0, iDWord);
+#elif defined(RT_ARCH_ARM64)
+    /* ASSUMES that there are two adjacent 128-bit registers available for the 256-bit value. */
+    Assert(!(iVecReg & 0x1));
+    /* ins vecsrc[iDWord], wzr */
+    if (iDWord >= 4)
+        pCodeBuf[off++] = Armv8A64MkVecInstrIns(iVecReg + 1, ARMV8_A64_REG_WZR, iDWord - 4, kArmv8InstrUmovInsSz_U32);
+    else
+        pCodeBuf[off++] = Armv8A64MkVecInstrIns(iVecReg, ARMV8_A64_REG_WZR, iDWord, kArmv8InstrUmovInsSz_U32);
+#else
+# error "port me"
+#endif
+    return off;
+}
+
+
+/**
+ * Emits a vecdst.au32[iDWord] = 0 store.
+ */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmitSimdZeroVecRegElemU32(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iVecReg, uint8_t iDWord)
+{
+
+#ifdef RT_ARCH_AMD64
+    off = iemNativeEmitSimdZeroVecRegElemU32Ex(iemNativeInstrBufEnsure(pReNative, off, 10), off, iVecReg, iDWord);
+#elif defined(RT_ARCH_ARM64)
+    off = iemNativeEmitSimdZeroVecRegElemU32Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecReg, iDWord);
+#else
+# error "port me"
+#endif
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+    return off;
+}
+
+
+/**
  * Emits a vecdst[0:127] = 0 store.
  */