Changeset 103913 in vbox

Timestamp:

Mar 19, 2024 11:47:09 AM (10 months ago)

Author:

vboxsync

Message:

VMM/IEM: Implement support for checking the high 128-bit register against the value stored in CPUMCTX for amd64, bugref:10614

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp

@@ -6116 +6116 @@
 
 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
+#  ifdef RT_ARCH_AMD64
+/**
+ * Helper for AMD64 to emit code which checks the low 128-bits of the given SIMD register against the given vCPU offset.
+ */
+DECL_FORCE_INLINE_THROW(uint32_t) iemNativeEmitGuestSimdRegValueCheckVCpuU128(uint8_t * const pbCodeBuf, uint32_t off, uint8_t idxSimdReg, uint32_t offVCpu)
+{
+    /* pcmpeqq vectmp0, [gstreg] (ASSUMES SSE4.1) */
+    pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    if (idxSimdReg >= 8)
+        pbCodeBuf[off++] = X86_OP_REX_R;
+    pbCodeBuf[off++] = 0x0f;
+    pbCodeBuf[off++] = 0x38;
+    pbCodeBuf[off++] = 0x29;
+    off = iemNativeEmitGprByVCpuDisp(pbCodeBuf, off, idxSimdReg, offVCpu);
+
+    /* pextrq tmp0, vectmp0, #0 (ASSUMES SSE4.1). */
+    pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    pbCodeBuf[off++] =   X86_OP_REX_W
+                       | (idxSimdReg < 8 ? 0 : X86_OP_REX_R)
+                       | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
+    pbCodeBuf[off++] = 0x0f;
+    pbCodeBuf[off++] = 0x3a;
+    pbCodeBuf[off++] = 0x16;
+    pbCodeBuf[off++] = 0xeb;
+    pbCodeBuf[off++] = 0x00;
+
+    /* cmp tmp0, 0xffffffffffffffff. */
+    pbCodeBuf[off++] = X86_OP_REX_W | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
+    pbCodeBuf[off++] = 0x83;
+    pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, IEMNATIVE_REG_FIXED_TMP0 & 7);
+    pbCodeBuf[off++] = 0xff;
+
+    /* je/jz +1 */
+    pbCodeBuf[off++] = 0x74;
+    pbCodeBuf[off++] = 0x01;
+
+    /* int3 */
+    pbCodeBuf[off++] = 0xcc;
+
+    /* pextrq tmp0, vectmp0, #1 (ASSUMES SSE4.1). */
+    pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    pbCodeBuf[off++] =   X86_OP_REX_W
+                       | (idxSimdReg < 8 ? 0 : X86_OP_REX_R)
+                       | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
+    pbCodeBuf[off++] = 0x0f;
+    pbCodeBuf[off++] = 0x3a;
+    pbCodeBuf[off++] = 0x16;
+    pbCodeBuf[off++] = 0xeb;
+    pbCodeBuf[off++] = 0x01;
+
+    /* cmp tmp0, 0xffffffffffffffff. */
+    pbCodeBuf[off++] = X86_OP_REX_W | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
+    pbCodeBuf[off++] = 0x83;
+    pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, IEMNATIVE_REG_FIXED_TMP0 & 7);
+    pbCodeBuf[off++] = 0xff;
+
+    /* je/jz +1 */
+    pbCodeBuf[off++] = 0x74;
+    pbCodeBuf[off++] = 0x01;
+
+    /* int3 */
+    pbCodeBuf[off++] = 0xcc;
+
+    return off;
+}
+#  endif
+
+
 /**
  * Emitting code that checks that the content of SIMD register @a idxSimdReg is the same
@@ -6139 +6207 @@
 
 #  ifdef RT_ARCH_AMD64
-    Assert(enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128); /** @todo 256-bit variant. */
-
-    /* movdqa vectmp0, idxSimdReg */
-    off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, IEMNATIVE_SIMD_REG_FIXED_TMP0, idxSimdReg);
-
-    uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 44);
-
-    /* pcmpeqq vectmp0, [gstreg] (ASSUMES SSE4.1) */
-    pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
-    if (IEMNATIVE_SIMD_REG_FIXED_TMP0 >= 8)
-        pbCodeBuf[off++] = X86_OP_REX_R;
-    pbCodeBuf[off++] = 0x0f;
-    pbCodeBuf[off++] = 0x38;
-    pbCodeBuf[off++] = 0x29;
-    off = iemNativeEmitGprByVCpuDisp(pbCodeBuf, off, IEMNATIVE_SIMD_REG_FIXED_TMP0, g_aGstSimdShadowInfo[enmGstSimdReg].offXmm);
-
-    /* pextrq tmp0, vectmp0, #0 (ASSUMES SSE4.1). */
-    pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
-    pbCodeBuf[off++] =   X86_OP_REX_W
-                       | (IEMNATIVE_SIMD_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_R)
-                       | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
-    pbCodeBuf[off++] = 0x0f;
-    pbCodeBuf[off++] = 0x3a;
-    pbCodeBuf[off++] = 0x16;
-    pbCodeBuf[off++] = 0xeb;
-    pbCodeBuf[off++] = 0x00;
-
-    /* cmp tmp0, 0xffffffffffffffff. */
-    pbCodeBuf[off++] = X86_OP_REX_W | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
-    pbCodeBuf[off++] = 0x83;
-    pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, IEMNATIVE_REG_FIXED_TMP0 & 7);
-    pbCodeBuf[off++] = 0xff;
-
-    /* je/jz +1 */
-    pbCodeBuf[off++] = 0x74;
-    pbCodeBuf[off++] = 0x01;
-
-    /* int3 */
-    pbCodeBuf[off++] = 0xcc;
-
-    /* pextrq tmp0, vectmp0, #1 (ASSUMES SSE4.1). */
-    pbCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
-    pbCodeBuf[off++] =   X86_OP_REX_W
-                       | (IEMNATIVE_SIMD_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_R)
-                       | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
-    pbCodeBuf[off++] = 0x0f;
-    pbCodeBuf[off++] = 0x3a;
-    pbCodeBuf[off++] = 0x16;
-    pbCodeBuf[off++] = 0xeb;
-    pbCodeBuf[off++] = 0x01;
-
-    /* cmp tmp0, 0xffffffffffffffff. */
-    pbCodeBuf[off++] = X86_OP_REX_W | (IEMNATIVE_REG_FIXED_TMP0 < 8 ? 0 : X86_OP_REX_B);
-    pbCodeBuf[off++] = 0x83;
-    pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, IEMNATIVE_REG_FIXED_TMP0 & 7);
-    pbCodeBuf[off++] = 0xff;
-
-    /* je/jz +1 */
-    pbCodeBuf[off++] = 0x74;
-    pbCodeBuf[off++] = 0x01;
-
-    /* int3 */
-    pbCodeBuf[off++] = 0xcc;
-
+    if (enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128 || enmLoadSz == kIemNativeGstSimdRegLdStSz_256)
+    {
+        /* movdqa vectmp0, idxSimdReg */
+        off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, IEMNATIVE_SIMD_REG_FIXED_TMP0, idxSimdReg);
+
+        uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 44);
+
+        off = iemNativeEmitGuestSimdRegValueCheckVCpuU128(pbCodeBuf, off, IEMNATIVE_SIMD_REG_FIXED_TMP0,
+                                                          g_aGstSimdShadowInfo[enmGstSimdReg].offXmm);
+    }
+
+    if (enmLoadSz == kIemNativeGstSimdRegLdStSz_High128 || enmLoadSz == kIemNativeGstSimdRegLdStSz_256)
+    {
+        /* Due to the fact that CPUMCTX stores the high 128-bit separately we need to do this all over again for the high part. */
+        uint8_t * const pbCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 50);
+
+        /* vextracti128 vectmp0, idxSimdReg, 1 */
+        pbCodeBuf[off++] = X86_OP_VEX3;
+        pbCodeBuf[off++] =   (idxSimdReg < 8 ? X86_OP_VEX3_BYTE1_R : 0)
+                           | X86_OP_VEX3_BYTE1_X
+                           | (IEMNATIVE_SIMD_REG_FIXED_TMP0 < 8 ? X86_OP_VEX3_BYTE1_B : 0)
+                           | 0x03; /* Opcode map */
+        pbCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(false /*f64BitOpSz*/, true /*f256BitAvx*/, X86_OP_VEX3_BYTE2_P_066H);
+        pbCodeBuf[off++] = 0x39;
+        pbCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxSimdReg & 7, IEMNATIVE_SIMD_REG_FIXED_TMP0 & 7);
+        pbCodeBuf[off++] = 0x01;
+
+        off = iemNativeEmitGuestSimdRegValueCheckVCpuU128(pbCodeBuf, off, IEMNATIVE_SIMD_REG_FIXED_TMP0,
+                                                          g_aGstSimdShadowInfo[enmGstSimdReg].offYmm);
+    }
 #  elif defined(RT_ARCH_ARM64)
     /* mov vectmp0, [gstreg] */