Changeset 103931 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Mar 19, 2024 11:47:19 PM (12 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162305

Message:

VMM/IEM,bs3-cpu-instr-3: Some vpextrb disas and special+illegal encoding test. bugref:9898

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-instr-3-template.mac (modified) (1 diff)
• bs3-cpu-instr-3.c32 (modified) (4 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

@@ -2182 +2182 @@
 EMIT_INSTR_PLUS_ICEBP_C64  vpextrb, FSxBX, XMM8, 0FFh
 EMIT_INSTR_PLUS_ICEBP_C64  vpextrb, FSxBX, XMM8, 000h
+
+%ifnmacro vpextrb_w1b_edx_xmm1 1
+ ; special encoding to prove that VEX.W is effectively ignored everywhere and that VEX.B only matter in 64-bit code.
+ %macro vpextrb_w1b_edx_xmm1 1
+        db      X86_OP_VEX3, 3 | X86_OP_VEX3_BYTE1_X | X86_OP_VEX3_BYTE1_R
+        db      X86_OP_VEX3_BYTE2_P_066H | (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) | X86_OP_VEX3_BYTE2_W
+        db      14h, X86_MODRM_MAKE(X86_MOD_REG, 1, X86_GREG_xDX), %1
+ %endmacro
+
+ ; invalid coding where VEX.L=1.
+ %macro vpextrb_l1_edx_xmm1 1
+        db      X86_OP_VEX3, 3 | X86_OP_VEX3_BYTE1_X | X86_OP_VEX3_BYTE1_R | X86_OP_VEX3_BYTE1_B
+        db      X86_OP_VEX3_BYTE2_P_066H | (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) | X86_OP_VEX3_BYTE2_L
+        db      14h, X86_MODRM_MAKE(X86_MOD_REG, 1, X86_GREG_xDX), %1
+ %endmacro
+%endif
+EMIT_INSTR_PLUS_ICEBP      vpextrb_w1b_edx_xmm1, 0FFh
+EMIT_INSTR_PLUS_ICEBP      vpextrb_l1_edx_xmm1, 0FFh
 
 ;

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

@@ -9763 +9763 @@
         {  bs3CpuInstr3_vpextrb_FSxBX_XMM1_0FFh_icebp_c16,   X86_XCPT_DB, RM_MEM8,  T_AVX_128, 1,  8, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_b),    s_aValuesFF_b },
         {  bs3CpuInstr3_vpextrb_FSxBX_XMM1_000h_icebp_c16,   X86_XCPT_DB, RM_MEM8,  T_AVX_128, 1,  8, false, true, 255, 1, RT_ELEMENTS(s_aValues00_b),    s_aValues00_b },
+        {  bs3CpuInstr3_vpextrb_w1b_edx_xmm1_0FFh_icebp_c16, 255,         RM_REG,   T_AVX_128, 4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF_b),    s_aValuesFF_b },
+        {  bs3CpuInstr3_vpextrb_l1_edx_xmm1_0FFh_icebp_c16,  255,         RM_REG,   T_AVX_128, 4, 32, true,  true, 2,   1, RT_ELEMENTS(s_aValuesFF_b),    s_aValuesFF_b },
 
         {  bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c16,       255,         RM_REG,   T_MMX_SSE, 4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00_w),    s_aValues00_w },
@@ -9799 +9801 @@
         {  bs3CpuInstr3_vpextrb_FSxBX_XMM1_0FFh_icebp_c32,   X86_XCPT_DB, RM_MEM8,  T_AVX_128, 1,  8, false, true, 255, 1, RT_ELEMENTS(s_aValuesFF_b),    s_aValuesFF_b },
         {  bs3CpuInstr3_vpextrb_FSxBX_XMM1_000h_icebp_c32,   X86_XCPT_DB, RM_MEM8,  T_AVX_128, 1,  8, false, true, 255, 1, RT_ELEMENTS(s_aValues00_b),    s_aValues00_b },
+        {  bs3CpuInstr3_vpextrb_w1b_edx_xmm1_0FFh_icebp_c32, 255,         RM_REG,   T_AVX_128, 4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF_b),    s_aValuesFF_b },
+        {  bs3CpuInstr3_vpextrb_l1_edx_xmm1_0FFh_icebp_c32,  255,         RM_REG,   T_AVX_128, 4, 32, true,  true, 2,   1, RT_ELEMENTS(s_aValuesFF_b),    s_aValuesFF_b },
 
         {  bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c32,       255,         RM_REG,   T_MMX_SSE, 4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00_w),    s_aValues00_w },
@@ -9843 +9847 @@
         {  bs3CpuInstr3_vpextrb_FSxBX_XMM8_0FFh_icebp_c64,   X86_XCPT_DB, RM_MEM8,  T_AVX_128, 1,  8, false, true, 255, 8, RT_ELEMENTS(s_aValuesFF_b),    s_aValuesFF_b },
         {  bs3CpuInstr3_vpextrb_FSxBX_XMM8_000h_icebp_c64,   X86_XCPT_DB, RM_MEM8,  T_AVX_128, 1,  8, false, true, 255, 8, RT_ELEMENTS(s_aValues00_b),    s_aValues00_b },
+        {  bs3CpuInstr3_vpextrb_w1b_edx_xmm1_0FFh_icebp_c64, 255,         RM_REG,   T_AVX_128, 4, 32, false, true, 10,  1, RT_ELEMENTS(s_aValuesFF_b),    s_aValuesFF_b }, /* manually setting VEX.B=1 */
+        {  bs3CpuInstr3_vpextrb_l1_edx_xmm1_0FFh_icebp_c64,  255,         RM_REG,   T_AVX_128, 4, 32, true,  true, 2,   1, RT_ELEMENTS(s_aValuesFF_b),    s_aValuesFF_b },
 
         {  bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c64,       255,         RM_REG,   T_MMX_SSE, 4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00_w),    s_aValues00_w },
@@ -9916 +9922 @@
     static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
-    return  bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+    return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
 }