VirtualBox

Changeset 103942 in vbox


Ignore:
Timestamp:
Mar 20, 2024 10:22:38 AM (11 months ago)
Author:
vboxsync
Message:

VMM/IEM: Implement memory stores from SIMD registers and implement native emitters for IEM_MC_STORE_MEM_U128_ALIGN_SSE()/IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE(), bugref:10614

Location:
trunk/src/VBox/VMM
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py

    r103937 r103942  
    33393339    'IEM_MC_STORE_MEM_U128':                                     (McBlock.parseMcGeneric,           True,  True,  False, ),
    33403340    'IEM_MC_STORE_MEM_U128_NO_AC':                               (McBlock.parseMcGeneric,           True,  True,  False, ),
    3341     'IEM_MC_STORE_MEM_U128_ALIGN_SSE':                           (McBlock.parseMcGeneric,           True,  True,  False, ),
     3341    'IEM_MC_STORE_MEM_U128_ALIGN_SSE':                           (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
    33423342    'IEM_MC_STORE_MEM_U16':                                      (McBlock.parseMcGeneric,           True,  True,  True,  ),
    33433343    'IEM_MC_STORE_MEM_U16_CONST':                                (McBlock.parseMcGeneric,           True,  True,  True,  ),

  • trunk/src/VBox/VMM/VMMAll/IEMAllN8vePython.py

    r103934 r103942  
    195195    'IEM_MC_STORE_MEM_FLAT_U128':                                        (None, True,  True,  False, ),
    196196    'IEM_MC_STORE_MEM_FLAT_U128_NO_AC':                                  (None, True,  True,  False, ),
    197     'IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE':                              (None, True,  True,  False, ),
     197    'IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE':                              (None, True,  True,  g_fNativeSimd),
    198198    'IEM_MC_STORE_MEM_FLAT_U16':                                         (None, True,  True,  True,  ),
    199199    'IEM_MC_STORE_MEM_FLAT_U16_CONST':                                   (None, True,  True,  True,  ),

  • trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h

    r103939 r103942  
    47084708#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    47094709            case sizeof(RTUINT128U):
    4710                 Assert(enmOp == kIemNativeEmitMemOp_Store || enmOp == kIemNativeEmitMemOp_Fetch);
    47114710                Assert(   (   enmOp == kIemNativeEmitMemOp_Fetch
    47124711                           && (   pfnFunction == (uintptr_t)iemNativeHlpMemFlatFetchDataU128
    … …  
    47144713                               || pfnFunction == (uintptr_t)iemNativeHlpMemFlatFetchDataU128NoAc))
    47154714                       || (   enmOp == kIemNativeEmitMemOp_Store
    4716                            && (pfnFunction == UINT64_C(0xc000b000a0009000))));
     4715                           && (pfnFunction == (uintptr_t)iemNativeHlpMemFlatStoreDataU128AlignedSse)));
    47174716                break;
    47184717            case sizeof(RTUINT256U):
    4719                 Assert(enmOp == kIemNativeEmitMemOp_Store || enmOp == kIemNativeEmitMemOp_Fetch);
    47204718                Assert(   (   enmOp == kIemNativeEmitMemOp_Fetch
    47214719                           && (pfnFunction == (uintptr_t)iemNativeHlpMemFlatFetchDataU256NoAc))
    … …  
    47694767#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
    47704768            case sizeof(RTUINT128U):
    4771                 Assert(enmOp == kIemNativeEmitMemOp_Store || enmOp == kIemNativeEmitMemOp_Fetch);
    47724769                Assert(   (   enmOp == kIemNativeEmitMemOp_Fetch
    47734770                           && (   pfnFunction == (uintptr_t)iemNativeHlpMemFetchDataU128
    … …  
    47754772                               || pfnFunction == (uintptr_t)iemNativeHlpMemFetchDataU128NoAc))
    47764773                       || (   enmOp == kIemNativeEmitMemOp_Store
    4777                            && (pfnFunction == UINT64_C(0xc000b000a0009000))));
     4774                           && (pfnFunction == (uintptr_t)iemNativeHlpMemStoreDataU128AlignedSse)));
    47784775                break;
    47794776            case sizeof(RTUINT256U):
    4780                 Assert(enmOp == kIemNativeEmitMemOp_Store || enmOp == kIemNativeEmitMemOp_Fetch);
    47814777                Assert(   (   enmOp == kIemNativeEmitMemOp_Fetch
    47824778                           && (pfnFunction == (uintptr_t)iemNativeHlpMemFetchDataU256NoAc))
    … …  
    48424838#endif
    48434839    IEMNATIVEEMITTLBSTATE const TlbState(pReNative, &off, idxVarGCPtrMem, iSegReg, cbMem, offDisp);
     4840
     4841#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     4842    uint8_t  idxRegValueStore = UINT8_MAX;
     4843
     4844    if (cbMem == sizeof(RTUINT128U) || cbMem == sizeof(RTUINT256U))
     4845        idxRegValueStore =     !TlbState.fSkip
     4846                            && enmOp == kIemNativeEmitMemOp_Store
     4847                            && pVarValue->enmKind != kIemNativeVarKind_Immediate
     4848                          ? iemNativeVarSimdRegisterAcquire(pReNative, idxVarValue, &off, true /*fInitialized*/)
     4849                          : UINT8_MAX;
     4850    else
     4851        idxRegValueStore  =    !TlbState.fSkip
     4852                            && enmOp == kIemNativeEmitMemOp_Store
     4853                            && pVarValue->enmKind != kIemNativeVarKind_Immediate
     4854                          ? iemNativeVarRegisterAcquire(pReNative, idxVarValue, &off, true /*fInitialized*/)
     4855                          : UINT8_MAX;
     4856
     4857#else
    48444858    uint8_t  const idxRegValueStore  =    !TlbState.fSkip
    48454859                                       && enmOp == kIemNativeEmitMemOp_Store
    … …  
    48474861                                     ? iemNativeVarRegisterAcquire(pReNative, idxVarValue, &off, true /*fInitialized*/)
    48484862                                     : UINT8_MAX;
     4863#endif
    48494864    uint32_t const idxRegMemResult   = !TlbState.fSkip ? iemNativeRegAllocTmp(pReNative, &off) : UINT8_MAX;
    48504865    uint32_t const idxLabelTlbLookup = !TlbState.fSkip
    … …  
    50475062                            off = iemNativeEmitStoreGpr64ByGprEx(pCodeBuf, off, idxRegValueStore, idxRegMemResult);
    50485063                            break;
     5064#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     5065                        case sizeof(RTUINT128U):
     5066                            off = iemNativeEmitStoreVecRegByGprU128Ex(pCodeBuf, off, idxRegValueStore, idxRegMemResult);
     5067                            break;
     5068                        case sizeof(RTUINT256U):
     5069                            off = iemNativeEmitStoreVecRegByGprU256Ex(pCodeBuf, off, idxRegValueStore, idxRegMemResult);
     5070                            break;
     5071#endif
    50495072                        default:
    50505073                            AssertFailed();
    … …  
    55155538    return off;
    55165539}
     5540
     5541
     5542#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     5543# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
     5544    off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u128Value, a_iSeg, a_GCPtrMem, \
     5545                                               sizeof(RTUINT128U), sizeof(RTUINT128U) - 1, kIemNativeEmitMemOp_Store, \
     5546                                               (uintptr_t)iemNativeHlpMemStoreDataU128AlignedSse, pCallEntry->idxInstr)
     5547
     5548# define IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE(a_GCPtrMem, a_u128Value) \
     5549    off = iemNativeEmitMemFetchStoreDataCommon(pReNative, off, a_u128Value, UINT8_MAX, a_GCPtrMem, \
     5550                                               sizeof(RTUINT128U), sizeof(RTUINT128U) - 1, kIemNativeEmitMemOp_Store, \
     5551                                               (uintptr_t)iemNativeHlpMemFlatStoreDataU128AlignedSse, pCallEntry->idxInstr)
     5552#endif
    55175553
    55185554

  • trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp

    r103934 r103942  
    19771977
    19781978
     1979#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     1980/**
     1981 * Used by TB code to store unsigned 128-bit data w/ segmentation.
     1982 */
     1983IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT128U pu128Src))
     1984{
     1985#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
     1986    iemMemStoreDataU128AlignedSseSafeJmp(pVCpu, iSegReg, GCPtrMem, pu128Src);
     1987#else
     1988    iemMemStoreDataU128AlignedSseJmp(pVCpu, iSegReg, GCPtrMem, pu128Src);
     1989#endif
     1990}
     1991
     1992
     1993/**
     1994 * Used by TB code to store unsigned 128-bit data w/ segmentation.
     1995 */
     1996IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemStoreDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT128U pu128Src))
     1997{
     1998#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
     1999    iemMemStoreDataU128NoAcSafeJmp(pVCpu, iSegReg, GCPtrMem, pu128Src);
     2000#else
     2001    iemMemStoreDataU128NoAcJmp(pVCpu, iSegReg, GCPtrMem, pu128Src);
     2002#endif
     2003}
     2004#endif
     2005
     2006
    19792007
    19802008/**
    … …  
    23242352#endif
    23252353}
     2354
     2355
     2356#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     2357/**
     2358 * Used by TB code to store unsigned 128-bit data w/ flat address.
     2359 */
     2360IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT128U pu128Src))
     2361{
     2362#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
     2363    iemMemStoreDataU128AlignedSseSafeJmp(pVCpu, UINT8_MAX, GCPtrMem, pu128Src);
     2364#else
     2365    iemMemFlatStoreDataU128AlignedSseJmp(pVCpu, GCPtrMem, pu128Src);
     2366#endif
     2367}
     2368
     2369
     2370/**
     2371 * Used by TB code to store unsigned 128-bit data w/ flat address.
     2372 */
     2373IEM_DECL_NATIVE_HLP_DEF(void, iemNativeHlpMemFlatStoreDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT128U pu128Src))
     2374{
     2375#ifdef IEMNATIVE_WITH_TLB_LOOKUP_STORE
     2376    iemMemStoreDataU128NoAcSafeJmp(pVCpu, UINT8_MAX, GCPtrMem, pu128Src);
     2377#else
     2378    iemMemFlatStoreDataU128NoAcJmp(pVCpu, GCPtrMem, pu128Src);
     2379#endif
     2380}
     2381#endif
    23262382
    23272383

  • trunk/src/VBox/VMM/include/IEMN8veRecompiler.h

    r103934 r103942  
    16551655IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint32_t u32Value));
    16561656IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint64_t u64Value));
     1657#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     1658IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT128U pu128Src));
     1659IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemStoreDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT128U pu128Src));
     1660#endif
    16571661IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpStackStoreU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value));
    16581662IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpStackStoreU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));
    … …  
    16831687IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));
    16841688IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value));
     1689#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     1690IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT128U pu128Src));
     1691IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpMemFlatStoreDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT128U pu128Src));
     1692#endif
    16851693IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpStackFlatStoreU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value));
    16861694IEM_DECL_NATIVE_HLP_PROTO(void,     iemNativeHlpStackFlatStoreU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));

  • trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h

    r103916 r103942  
    25022502# endif
    25032503
     2504
     2505/**
     2506 * Common bit of iemNativeEmitLoadVecRegByGprU128 and friends.
     2507 */
     2508DECL_FORCE_INLINE_THROW(uint32_t)
     2509iemNativeEmitVecRegByGprLdSt(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iVecReg,
     2510                             uint8_t iGprBase, int32_t offDisp, ARMV8A64INSTRLDSTTYPE enmOperation, unsigned cbData)
     2511{
     2512    /*
     2513     * There are a couple of ldr variants that takes an immediate offset, so
     2514     * try use those if we can, otherwise we have to use the temporary register
     2515     * help with the addressing.
     2516     */
     2517    if ((uint32_t)offDisp < _4K * cbData && !((uint32_t)offDisp & (cbData - 1)))
     2518    {
     2519        /* Use the unsigned variant of ldr Wt, [<Xn|SP>, #off]. */
     2520        uint32_t *pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
     2521        pu32CodeBuf[off++] = Armv8A64MkInstrStLdRUOff(enmOperation, iVecReg, iGprBase, (uint32_t)offDisp / cbData);
     2522    }
     2523    else
     2524    {
     2525        /* The offset is too large, so we must load it into a register and use
     2526           ldr Wt, [<Xn|SP>, (<Wm>|<Xm>)]. */
     2527        /** @todo reduce by offVCpu by >> 3 or >> 2? if it saves instructions? */
     2528        uint8_t const idxTmpReg = iemNativeRegAllocTmpImm(pReNative, &off, (int64_t)offDisp);
     2529
     2530        uint32_t *pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
     2531        pu32CodeBuf[off++] = Armv8A64MkInstrStLdRegIdx(enmOperation, iVecReg, iGprBase, idxTmpReg);
     2532
     2533        iemNativeRegFreeTmpImm(pReNative, idxTmpReg);
     2534    }
     2535    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     2536    return off;
     2537}
    25042538#endif /* RT_ARCH_ARM64 */
    25052539
    … …  
    29372971
    29382972#elif defined(RT_ARCH_ARM64)
    2939     off = iemNativeEmitGprByGprLdSt(pReNative, off, iVecRegDst, iGprBase, offDisp, kArmv8A64InstrLdStType_Ld_Vr_128, sizeof(RTUINT128U));
     2973    off = iemNativeEmitVecRegByGprLdSt(pReNative, off, iVecRegDst, iGprBase, offDisp, kArmv8A64InstrLdStType_Ld_Vr_128, sizeof(RTUINT128U));
    29402974
    29412975#else
    … …  
    29953029#elif defined(RT_ARCH_ARM64)
    29963030    Assert(!(iVecRegDst & 0x1));
    2997     off = iemNativeEmitGprByGprLdSt(pReNative, off, iVecRegDst, iGprBase, offDisp,
    2998                                     kArmv8A64InstrLdStType_Ld_Vr_128, sizeof(RTUINT128U));
    2999     off = iemNativeEmitGprByGprLdSt(pReNative, off, iVecRegDst + 1, iGprBase, offDisp + sizeof(RTUINT128U),
    3000                                     kArmv8A64InstrLdStType_Ld_Vr_128, sizeof(RTUINT128U));
     3031    off = iemNativeEmitVecRegByGprLdSt(pReNative, off, iVecRegDst, iGprBase, offDisp,
     3032                                       kArmv8A64InstrLdStType_Ld_Vr_128, sizeof(RTUINT128U));
     3033    off = iemNativeEmitVecRegByGprLdSt(pReNative, off, iVecRegDst + 1, iGprBase, offDisp + sizeof(RTUINT128U),
     3034                                       kArmv8A64InstrLdStType_Ld_Vr_128, sizeof(RTUINT128U));
    30013035
    30023036#else
    … …  
    33193353    return off;
    33203354}
     3355
     3356
     3357#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
     3358/**
     3359 * Emits a 128-bit vector register store via a GPR base address with a displacement.
     3360 *
     3361 * @note ARM64: Misaligned @a offDisp values and values not in the
     3362 *       -0x7ff8...0x7ff8 range will require a temporary register (@a iGprTmp) if
     3363 *       @a iGprReg and @a iGprBase are the same. Will assert / throw if caller
     3364 *       does not heed this.
     3365 */
     3366DECL_FORCE_INLINE_THROW(uint32_t)
     3367iemNativeEmitStoreVecRegByGprU128Ex(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iVecRegDst, uint8_t iGprBase,
     3368                                   int32_t offDisp = 0, uint8_t iGprTmp = UINT8_MAX)
     3369{
     3370#ifdef RT_ARCH_AMD64
     3371    /* movdqu mem128, reg128 */
     3372    pCodeBuf[off++] = 0xf3;
     3373    if (iVecRegDst >= 8 || iGprBase >= 8)
     3374        pCodeBuf[off++] = (iVecRegDst < 8 ? 0 : X86_OP_REX_R) | (iGprBase < 8 ? 0 : X86_OP_REX_B);
     3375    pCodeBuf[off++] = 0x0f;
     3376    pCodeBuf[off++] = 0x7f;
     3377    off = iemNativeEmitGprByGprDisp(pCodeBuf, off, iVecRegDst, iGprBase, offDisp);
     3378    RT_NOREF(iGprTmp);
     3379
     3380#elif defined(RT_ARCH_ARM64)
     3381    off = iemNativeEmitVecRegByGprLdStEx(pCodeBuf, off, iVecRegDst, iGprBase, offDisp,
     3382                                         kArmv8A64InstrLdStType_St_Vr_128, sizeof(RTUINT128U), iGprTmp);
     3383
     3384#else
     3385# error "port me"
     3386#endif
     3387    return off;
     3388}
     3389
     3390
     3391/**
     3392 * Emits a 128-bit vector register store via a GPR base address with a displacement.
     3393 */
     3394DECL_INLINE_THROW(uint32_t)
     3395iemNativeEmitStoreVecRegByGprU128(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iVecRegDst, uint8_t iGprBase, int32_t offDisp)
     3396{
     3397#ifdef RT_ARCH_AMD64
     3398    off = iemNativeEmitStoreVecRegByGprU128Ex(iemNativeInstrBufEnsure(pReNative, off, 8), off, iVecRegDst, iGprBase, offDisp);
     3399    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     3400
     3401#elif defined(RT_ARCH_ARM64)
     3402    off = iemNativeEmitVecRegByGprLdSt(pReNative, off, iVecRegDst, iGprBase, offDisp, kArmv8A64InstrLdStType_St_Vr_128, sizeof(RTUINT128U));
     3403
     3404#else
     3405# error "port me"
     3406#endif
     3407    return off;
     3408}
     3409
     3410
     3411/**
     3412 * Emits a 256-bit vector register store via a GPR base address with a displacement.
     3413 *
     3414 * @note ARM64: Misaligned @a offDisp values and values not in the
     3415 *       -0x7ff8...0x7ff8 range will require a temporary register (@a iGprTmp) if
     3416 *       @a iGprReg and @a iGprBase are the same. Will assert / throw if caller
     3417 *       does not heed this.
     3418 */
     3419DECL_FORCE_INLINE_THROW(uint32_t)
     3420iemNativeEmitStoreVecRegByGprU256Ex(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iVecRegDst, uint8_t iGprBase,
     3421                                    int32_t offDisp = 0, uint8_t iGprTmp = UINT8_MAX)
     3422{
     3423#ifdef RT_ARCH_AMD64
     3424    /* vmovdqu reg256, mem256 */
     3425    AssertFailed();
     3426    pCodeBuf[off++] = X86_OP_VEX3;
     3427    pCodeBuf[off++] =   (iVecRegDst < 8 ? X86_OP_VEX3_BYTE1_R : 0)
     3428                      | X86_OP_VEX3_BYTE1_X
     3429                      | (iGprBase < 8 ? X86_OP_VEX3_BYTE1_B : 0)
     3430                      | UINT8_C(0x01);
     3431    pCodeBuf[off++] = X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(false /*f64BitOpSz*/, true /*f256BitAvx*/, X86_OP_VEX2_BYTE1_P_0F3H);
     3432    pCodeBuf[off++] = 0x7f;
     3433    off = iemNativeEmitGprByGprDisp(pCodeBuf, off, iVecRegDst, iGprBase, offDisp);
     3434    RT_NOREF(iGprTmp);
     3435
     3436#elif defined(RT_ARCH_ARM64)
     3437    Assert(!(iVecRegDst & 0x1));
     3438    off = iemNativeEmitVecRegByGprLdStEx(pCodeBuf, off, iVecRegDst, iGprBase, offDisp,
     3439                                         kArmv8A64InstrLdStType_Ld_Vr_128, sizeof(RTUINT128U), iGprTmp);
     3440    off = iemNativeEmitVecRegByGprLdStEx(pCodeBuf, off, iVecRegDst + 1, iGprBase, offDisp + sizeof(RTUINT128U),
     3441                                         kArmv8A64InstrLdStType_Ld_Vr_128, sizeof(RTUINT128U), iGprTmp);
     3442#else
     3443# error "port me"
     3444#endif
     3445    return off;
     3446}
     3447
     3448
     3449/**
     3450 * Emits a 256-bit GPR load via a GPR base address with a displacement.
     3451 */
     3452DECL_INLINE_THROW(uint32_t)
     3453iemNativeEmitStoreVecRegByGprU256(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iVecRegDst, uint8_t iGprBase, int32_t offDisp)
     3454{
     3455#ifdef RT_ARCH_AMD64
     3456    off = iemNativeEmitStoreVecRegByGprU256Ex(iemNativeInstrBufEnsure(pReNative, off, 8), off, iVecRegDst, iGprBase, offDisp);
     3457    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     3458
     3459#elif defined(RT_ARCH_ARM64)
     3460    Assert(!(iVecRegDst & 0x1));
     3461    off = iemNativeEmitVecRegByGprLdSt(pReNative, off, iVecRegDst, iGprBase, offDisp,
     3462                                       kArmv8A64InstrLdStType_St_Vr_128, sizeof(RTUINT128U));
     3463    off = iemNativeEmitVecRegByGprLdSt(pReNative, off, iVecRegDst + 1, iGprBase, offDisp + sizeof(RTUINT128U),
     3464                                       kArmv8A64InstrLdStType_St_Vr_128, sizeof(RTUINT128U));
     3465
     3466#else
     3467# error "port me"
     3468#endif
     3469    return off;
     3470}
     3471#endif
    33213472
    33223473
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