Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h	(revision 103986)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h	(revision 103990)
@@ -7199,9 +7199,15 @@
 iemNativeEmitSimdCopyXregU128(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iXRegDst, uint8_t iXRegSrc)
 {
-    /* Allocate destination and source register. */
+    /* 
+     * Allocate destination and source register.
+     *
+     * @note The order is important here when iXRegSrc == iXRegDst, because if iXRegDst gets allocated first for the full write
+     *       it won't load the actual value from CPUMCTX. When allocating iXRegSrc afterwards it will get duplicated from the already
+     *       allocated host register for iXRegDst containing garbage. This will be catched by the guest register value checking.
+     */
+    uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXRegSrc),
+                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly);
     uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXRegDst),
                                                                           kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite);
-    uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXRegSrc),
-                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly);
 
     off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, idxSimdRegDst, idxSimdRegSrc);
@@ -7514,9 +7520,15 @@
 iemNativeEmitSimdCopyYregU128ZxVlmax(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iYRegDst, uint8_t iYRegSrc)
 {
-    /* Allocate destination and source register. */
+    /* 
+     * Allocate destination and source register.
+     *
+     * @note The order is important here when iYRegSrc == iYRegDst, because if iYRegDst gets allocated first for the full write
+     *       it won't load the actual value from CPUMCTX. When allocating iYRegSrc afterwards it will get duplicated from the already
+     *       allocated host register for iYRegDst containing garbage. This will be catched by the guest register value checking.
+     */
+    uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegSrc),
+                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly);
     uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegDst),
                                                                           kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite);
-    uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegSrc),
-                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly);
 
     off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, idxSimdRegDst, idxSimdRegSrc);
@@ -7540,9 +7552,15 @@
 iemNativeEmitSimdCopyYregU256ZxVlmax(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iYRegDst, uint8_t iYRegSrc)
 {
-    /* Allocate destination and source register. */
+    /* 
+     * Allocate destination and source register.
+     *
+     * @note The order is important here when iYRegSrc == iYRegDst, because if iYRegDst gets allocated first for the full write
+     *       it won't load the actual value from CPUMCTX. When allocating iYRegSrc afterwards it will get duplicated from the already
+     *       allocated host register for iYRegDst containing garbage. This will be catched by the guest register value checking.
+     */
+    uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegSrc),
+                                                                          kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ReadOnly);
     uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegDst),
                                                                           kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ForFullWrite);
-    uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iYRegSrc),
-                                                                          kIemNativeGstSimdRegLdStSz_256, kIemNativeGstRegUse_ReadOnly);
 
     off = iemNativeEmitSimdLoadVecRegFromVecRegU256(pReNative, off, idxSimdRegDst, idxSimdRegSrc);
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp	(revision 103986)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp	(revision 103990)
@@ -5594,4 +5594,6 @@
         Assert(pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows == 0);
         Assert(!(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxSimdReg)));
+
+        pReNative->Core.aHstSimdRegs[idxSimdReg].enmLoaded = kIemNativeGstSimdRegLdStSz_Invalid;
         Log12(("iemNativeSimdRegAllocTmp: %s\n", g_apszIemNativeHstSimdRegNames[idxSimdReg]));
     }
@@ -5647,4 +5649,6 @@
         Assert(pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows == 0);
         Assert(!(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxSimdReg)));
+
+        pReNative->Core.aHstSimdRegs[idxSimdReg].enmLoaded = kIemNativeGstSimdRegLdStSz_Invalid;
         Log12(("iemNativeSimdRegAllocTmpEx: %s\n", g_apszIemNativeHstSimdRegNames[idxSimdReg]));
     }
@@ -6436,12 +6440,12 @@
     if (enmLoadSz == kIemNativeGstSimdRegLdStSz_Low128 || enmLoadSz == kIemNativeGstSimdRegLdStSz_256)
     {
-        uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 5);
+        uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6);
         /* eor vectmp0, vectmp0, idxSimdReg */
         pu32CodeBuf[off++] = Armv8A64MkVecInstrEor(IEMNATIVE_SIMD_REG_FIXED_TMP0, IEMNATIVE_SIMD_REG_FIXED_TMP0, idxSimdReg);
-        /* cnt vectmp0, vectmp0, #0*/
-        pu32CodeBuf[off++] = Armv8A64MkVecInstrCnt(IEMNATIVE_SIMD_REG_FIXED_TMP0, IEMNATIVE_SIMD_REG_FIXED_TMP0);
-        /* umov tmp0, vectmp0.D[0] */
+        /* uaddlv vectmp0, vectmp0.16B */
+        pu32CodeBuf[off++] = Armv8A64MkVecInstrUAddLV(IEMNATIVE_SIMD_REG_FIXED_TMP0, IEMNATIVE_SIMD_REG_FIXED_TMP0, kArmv8InstrUAddLVSz_16B);
+        /* umov tmp0, vectmp0.H[0] */
         pu32CodeBuf[off++] = Armv8A64MkVecInstrUmov(IEMNATIVE_REG_FIXED_TMP0, IEMNATIVE_SIMD_REG_FIXED_TMP0,
-                                                    0 /*idxElem*/, kArmv8InstrUmovInsSz_U64);
+                                                    0 /*idxElem*/, kArmv8InstrUmovInsSz_U16, false /*f64Bit*/);
         /* cbz tmp0, +1 */
         pu32CodeBuf[off++] = Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, 2, IEMNATIVE_REG_FIXED_TMP0);
@@ -6452,12 +6456,12 @@
     if (enmLoadSz == kIemNativeGstSimdRegLdStSz_High128 || enmLoadSz == kIemNativeGstSimdRegLdStSz_256)
     {
-        uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 5);
+        uint32_t * const pu32CodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6);
         /* eor vectmp0 + 1, vectmp0 + 1, idxSimdReg */
         pu32CodeBuf[off++] = Armv8A64MkVecInstrEor(IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1, IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1, idxSimdReg + 1);
-        /* cnt vectmp0 + 1, vectmp0 + 1, #0*/
-        pu32CodeBuf[off++] = Armv8A64MkVecInstrCnt(IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1, IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1);
-        /* umov tmp0, (vectmp0 + 1).D[0] */
+        /* uaddlv vectmp0 + 1, (vectmp0 + 1).16B */
+        pu32CodeBuf[off++] = Armv8A64MkVecInstrUAddLV(IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1, IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1, kArmv8InstrUAddLVSz_16B);
+        /* umov tmp0, (vectmp0 + 1).H[0] */
         pu32CodeBuf[off++] = Armv8A64MkVecInstrUmov(IEMNATIVE_REG_FIXED_TMP0, IEMNATIVE_SIMD_REG_FIXED_TMP0 + 1,
-                                                    0 /*idxElem*/, kArmv8InstrUmovInsSz_U64);
+                                                    0 /*idxElem*/, kArmv8InstrUmovInsSz_U16, false /*f64Bit*/);
         /* cbz tmp0, +1 */
         pu32CodeBuf[off++] = Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, 2, IEMNATIVE_REG_FIXED_TMP0);
