- Timestamp:
- Mar 21, 2024 5:59:07 PM (12 months ago)
- svn:sync-xref-src-repo-rev:
- 162380
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 4 edited
-
VMMAll/IEMAllInstPython.py (modified) (3 diffs)
-
VMMAll/IEMAllN8veRecompFuncs.h (modified) (3 diffs)
-
VMMAll/IEMAllN8veRecompiler.cpp (modified) (5 diffs)
-
include/IEMN8veRecompiler.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r103979 r103993 3193 3193 'IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT': (McBlock.parseMcGeneric, True, True, False, ), 3194 3194 'IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0': (McBlock.parseMcGeneric, True, True, False, ), 3195 'IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT': (McBlock.parseMcGeneric, True, True, False,),3195 'IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3196 3196 'IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT': (McBlock.parseMcGeneric, True, True, True, ), 3197 3197 'IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE': (McBlock.parseMcGeneric, True, True, False, ), … … 3291 3291 'IEM_MC_REF_MREG_U64_CONST': (McBlock.parseMcGeneric, False, False, False, ), 3292 3292 'IEM_MC_REF_MXCSR': (McBlock.parseMcGeneric, False, False, True, ), 3293 'IEM_MC_REF_XREG_R32_CONST': (McBlock.parseMcGeneric, False, False, False,),3294 'IEM_MC_REF_XREG_R64_CONST': (McBlock.parseMcGeneric, False, False, False,),3293 'IEM_MC_REF_XREG_R32_CONST': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), 3294 'IEM_MC_REF_XREG_R64_CONST': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), 3295 3295 'IEM_MC_REF_XREG_U128': (McBlock.parseMcGeneric, False, False, True, ), 3296 3296 'IEM_MC_REF_XREG_U128_CONST': (McBlock.parseMcGeneric, False, False, True, ), 3297 'IEM_MC_REF_XREG_U32_CONST': (McBlock.parseMcGeneric, False, False, False,),3298 'IEM_MC_REF_XREG_U64_CONST': (McBlock.parseMcGeneric, False, False, False,),3297 'IEM_MC_REF_XREG_U32_CONST': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), 3298 'IEM_MC_REF_XREG_U64_CONST': (McBlock.parseMcGeneric, False, False, g_fNativeSimd), 3299 3299 'IEM_MC_REF_XREG_XMM_CONST': (McBlock.parseMcGeneric, False, False, True, ), 3300 3300 'IEM_MC_REF_YREG_U128': (McBlock.parseMcGeneric, False, False, False, ), … … 3360 3360 'IEM_MC_STORE_SREG_BASE_U32': (McBlock.parseMcGeneric, True, True, False, ), 3361 3361 'IEM_MC_STORE_SREG_BASE_U64': (McBlock.parseMcGeneric, True, True, False, ), 3362 'IEM_MC_STORE_SSE_RESULT': (McBlock.parseMcGeneric, True, True, False,),3362 'IEM_MC_STORE_SSE_RESULT': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3363 3363 'IEM_MC_STORE_XREG_R32': (McBlock.parseMcGeneric, True, True, False, ), 3364 3364 'IEM_MC_STORE_XREG_R64': (McBlock.parseMcGeneric, True, True, False, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
r103991 r103993 1099 1099 return off; 1100 1100 } 1101 1102 1103 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR 1104 #define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \ 1105 off = iemNativeEmitSimdMaybeRaiseSseAvxSimdFpOrUdXcpt(pReNative, off) 1106 1107 /** Emits code for IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT. */ 1108 DECL_INLINE_THROW(uint32_t) 1109 iemNativeEmitSimdMaybeRaiseSseAvxSimdFpOrUdXcpt(PIEMRECOMPILERSTATE pReNative, uint32_t off) 1110 { 1111 uint8_t const idxLabelRaiseSseAvxFpRelated = iemNativeLabelCreate(pReNative, kIemNativeLabelType_RaiseSseAvxFpRelated); 1112 uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ReadOnly); 1113 uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off); 1114 1115 /* mov tmp, varmxcsr */ 1116 off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxRegTmp, idxRegMxCsr); 1117 /* tmp &= X86_MXCSR_XCPT_MASK */ 1118 off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_MASK); 1119 /* tmp >>= X86_MXCSR_XCPT_MASK_SHIFT */ 1120 off = iemNativeEmitShiftGprRight(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_MASK_SHIFT); 1121 /* tmp = ~tmp */ 1122 off = iemNativeEmitInvBitsGpr(pReNative, off, idxRegTmp, idxRegTmp, false /*f64Bit*/); 1123 /* tmp &= mxcsr */ 1124 off = iemNativeEmitAndGpr32ByGpr32(pReNative, off, idxRegTmp, idxRegMxCsr); 1125 off = iemNativeEmitTestAnyBitsInGprAndJmpToLabelIfAnySet(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_FLAGS, 1126 idxLabelRaiseSseAvxFpRelated); 1127 1128 /* Free but don't flush the MXCSR register. */ 1129 iemNativeRegFreeTmp(pReNative, idxRegMxCsr); 1130 iemNativeRegFreeTmp(pReNative, idxRegTmp); 1131 1132 return off; 1133 } 1134 #endif 1101 1135 1102 1136 … … 3914 3948 #define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \ 3915 3949 off = iemNativeEmitRefXregXxx(pReNative, off, a_pXmmDst, a_iXReg, true /*fConst*/) 3950 3951 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR 3952 /* Just being paranoid here. */ 3953 AssertCompile2MemberOffsets(CPUMCTX, XState.x87.aXMM[0], XState.x87.aXMM[0].au64[0]); 3954 AssertCompile2MemberOffsets(CPUMCTX, XState.x87.aXMM[0], XState.x87.aXMM[0].au32[0]); 3955 AssertCompile2MemberOffsets(CPUMCTX, XState.x87.aXMM[0], XState.x87.aXMM[0].ar64[0]); 3956 AssertCompile2MemberOffsets(CPUMCTX, XState.x87.aXMM[0], XState.x87.aXMM[0].ar32[0]); 3957 3958 #define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \ 3959 off = iemNativeEmitRefXregXxx(pReNative, off, a_pu32Dst, a_iXReg, true /*fConst*/) 3960 #define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \ 3961 off = iemNativeEmitRefXregXxx(pReNative, off, a_pu64Dst, a_iXReg, true /*fConst*/) 3962 #define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \ 3963 off = iemNativeEmitRefXregXxx(pReNative, off, a_pr32Dst, a_iXReg, true /*fConst*/) 3964 #define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \ 3965 off = iemNativeEmitRefXregXxx(pReNative, off, a_pr64Dst, a_iXReg, true /*fConst*/) 3966 #endif 3916 3967 3917 3968 /** Handles IEM_MC_REF_XREG_xxx[_CONST]. */ … … 8248 8299 8249 8300 8301 #define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \ 8302 off = iemNativeEmitSimdSseStoreResult(pReNative, off, a_SseData, a_iXmmReg) 8303 8304 /** Emits code for IEM_MC_STORE_SSE_RESULT. */ 8305 DECL_INLINE_THROW(uint32_t) 8306 iemNativeEmitSimdSseStoreResult(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxSseDataVar, uint8_t iXReg) 8307 { 8308 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxSseDataVar); 8309 IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxSseDataVar, sizeof(IEMSSERESULT)); 8310 8311 /** @todo r=aeichner We probably need to rework this MC statement and the users to make thing more efficient. */ 8312 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 8313 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite); 8314 uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ForUpdate); 8315 uint8_t const idxVarRegResAddr = iemNativeRegAllocTmp(pReNative, &off); 8316 uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off); 8317 8318 /* Assume the register to be always dirty for now, even if it doesn't get written when the code is executed due to unmasked exceptions. */ 8319 IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_LO_U128(pReNative, iXReg); 8320 8321 off = iemNativeEmitLoadArgGregWithVarAddr(pReNative, off, idxVarRegResAddr, idxSseDataVar, false /*fFlushShadows*/); 8322 8323 /* Update MXCSR. */ 8324 off = iemNativeEmitLoadGprByGprU32(pReNative, off, idxRegTmp, idxVarRegResAddr, RT_UOFFSETOF_DYN(IEMSSERESULT, MXCSR)); 8325 /* tmp &= X86_MXCSR_XCPT_FLAGS. */ 8326 off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_FLAGS); 8327 /* mxcsr |= tmp */ 8328 off = iemNativeEmitOrGpr32ByGpr(pReNative, off, idxRegMxCsr, idxRegTmp); 8329 8330 /* Writeback the MXCSR register value (there is no delayed writeback for such registers at the moment). */ 8331 off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxRegMxCsr, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.XState.x87.MXCSR)); 8332 8333 /* Update the value if there is no unmasked exception. */ 8334 /* tmp = mxcsr */ 8335 off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxRegTmp, idxRegMxCsr); 8336 /* tmp &= X86_MXCSR_XCPT_MASK */ 8337 off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_MASK); 8338 /* tmp >>= X86_MXCSR_XCPT_MASK_SHIFT */ 8339 off = iemNativeEmitShiftGprRight(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_MASK_SHIFT); 8340 /* tmp = ~tmp */ 8341 off = iemNativeEmitInvBitsGpr(pReNative, off, idxRegTmp, idxRegTmp, false /*f64Bit*/); 8342 /* tmp &= mxcsr */ 8343 off = iemNativeEmitAndGpr32ByGpr32(pReNative, off, idxRegTmp, idxRegMxCsr); 8344 8345 off = iemNativeEmitTestAnyBitsInGpr(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_FLAGS); 8346 uint32_t offFixup = off; 8347 off = iemNativeEmitJnzToFixed(pReNative, off, off); 8348 AssertCompileMemberSize(IEMSSERESULT, uResult, sizeof(RTFLOAT128U)); 8349 off = iemNativeEmitLoadVecRegByGprU128(pReNative, off, idxSimdRegDst, idxVarRegResAddr, RT_UOFFSETOF_DYN(IEMSSERESULT, uResult)); 8350 iemNativeFixupFixedJump(pReNative, offFixup, off); 8351 8352 /* Free but don't flush the shadowed register. */ 8353 iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); 8354 iemNativeRegFreeTmp(pReNative, idxRegMxCsr); 8355 iemNativeRegFreeTmp(pReNative, idxVarRegResAddr); 8356 iemNativeRegFreeTmp(pReNative, idxRegTmp); 8357 8358 return off; 8359 } 8360 8361 8250 8362 /********************************************************************************************************************************* 8251 8363 * Emitters for IEM_MC_CALL_SSE_AIMPL_XXX * -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
r103990 r103993 1640 1640 1641 1641 /** 1642 * Used by TB code when it wants to raise an SSE/AVX floating point exception related \#UD or \#XF. 1643 * 1644 * See IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT. 1645 */ 1646 IEM_DECL_NATIVE_HLP_DEF(int, iemNativeHlpExecRaiseSseAvxFpRelated,(PVMCPUCC pVCpu)) 1647 { 1648 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) 1649 iemRaiseSimdFpExceptionJmp(pVCpu); 1650 else 1651 iemRaiseUndefinedOpcodeJmp(pVCpu); 1652 #ifndef _MSC_VER 1653 return VINF_IEM_RAISED_XCPT; /* not reached */ 1654 #endif 1655 } 1656 1657 1658 /** 1642 1659 * Used by TB code when it wants to raise a \#NM. 1643 1660 */ … … 3245 3262 pReNative->Core.u64ArgVars = UINT64_MAX; 3246 3263 3247 AssertCompile(RT_ELEMENTS(pReNative->aidxUniqueLabels) == 1 6);3264 AssertCompile(RT_ELEMENTS(pReNative->aidxUniqueLabels) == 17); 3248 3265 pReNative->aidxUniqueLabels[0] = UINT32_MAX; 3249 3266 pReNative->aidxUniqueLabels[1] = UINT32_MAX; … … 3262 3279 pReNative->aidxUniqueLabels[14] = UINT32_MAX; 3263 3280 pReNative->aidxUniqueLabels[15] = UINT32_MAX; 3281 pReNative->aidxUniqueLabels[16] = UINT32_MAX; 3264 3282 3265 3283 /* Full host register reinit: */ … … 9243 9261 case kIemNativeLabelType_RaiseSseRelated: pszName = "RaiseSseRelated"; break; 9244 9262 case kIemNativeLabelType_RaiseAvxRelated: pszName = "RaiseAvxRelated"; break; 9263 case kIemNativeLabelType_RaiseSseAvxFpRelated: pszName = "RaiseSseAvxFpRelated"; break; 9245 9264 case kIemNativeLabelType_RaiseNm: pszName = "RaiseNm"; break; 9246 9265 case kIemNativeLabelType_RaiseGp0: pszName = "RaiseGp0"; break; … … 9855 9874 { kIemNativeLabelType_RaiseSseRelated, iemNativeHlpExecRaiseSseRelated }, 9856 9875 { kIemNativeLabelType_RaiseAvxRelated, iemNativeHlpExecRaiseAvxRelated }, 9876 { kIemNativeLabelType_RaiseSseAvxFpRelated, iemNativeHlpExecRaiseSseAvxFpRelated }, 9857 9877 { kIemNativeLabelType_RaiseNm, iemNativeHlpExecRaiseNm }, 9858 9878 { kIemNativeLabelType_RaiseGp0, iemNativeHlpExecRaiseGp0 }, -
trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
r103953 r103993 404 404 */ 405 405 /* Simple labels comes first for indexing reasons. RaiseXx is order by the exception's numerical value(s). */ 406 kIemNativeLabelType_RaiseDe, /**< Raise (throw) X86_XCPT_DE (00h). */ 407 kIemNativeLabelType_RaiseUd, /**< Raise (throw) X86_XCPT_UD (06h). */ 408 kIemNativeLabelType_RaiseSseRelated, /**< Raise (throw) X86_XCPT_UD or X86_XCPT_NM according to cr0 & cr4. */ 409 kIemNativeLabelType_RaiseAvxRelated, /**< Raise (throw) X86_XCPT_UD or X86_XCPT_NM according to xcr0, cr0 & cr4. */ 410 kIemNativeLabelType_RaiseNm, /**< Raise (throw) X86_XCPT_NM (07h). */ 411 kIemNativeLabelType_RaiseGp0, /**< Raise (throw) X86_XCPT_GP (0dh) w/ errcd=0. */ 412 kIemNativeLabelType_RaiseMf, /**< Raise (throw) X86_XCPT_MF (10h). */ 413 kIemNativeLabelType_RaiseXf, /**< Raise (throw) X86_XCPT_XF (13h). */ 406 kIemNativeLabelType_RaiseDe, /**< Raise (throw) X86_XCPT_DE (00h). */ 407 kIemNativeLabelType_RaiseUd, /**< Raise (throw) X86_XCPT_UD (06h). */ 408 kIemNativeLabelType_RaiseSseRelated, /**< Raise (throw) X86_XCPT_UD or X86_XCPT_NM according to cr0 & cr4. */ 409 kIemNativeLabelType_RaiseAvxRelated, /**< Raise (throw) X86_XCPT_UD or X86_XCPT_NM according to xcr0, cr0 & cr4. */ 410 kIemNativeLabelType_RaiseSseAvxFpRelated, /**< Raise (throw) X86_XCPT_UD or X86_XCPT_XF according to c4. */ 411 kIemNativeLabelType_RaiseNm, /**< Raise (throw) X86_XCPT_NM (07h). */ 412 kIemNativeLabelType_RaiseGp0, /**< Raise (throw) X86_XCPT_GP (0dh) w/ errcd=0. */ 413 kIemNativeLabelType_RaiseMf, /**< Raise (throw) X86_XCPT_MF (10h). */ 414 kIemNativeLabelType_RaiseXf, /**< Raise (throw) X86_XCPT_XF (13h). */ 414 415 kIemNativeLabelType_ObsoleteTb, 415 416 kIemNativeLabelType_NeedCsLimChecking,
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