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Changeset 104040 in vbox for trunk


Ignore:
Timestamp:
Mar 25, 2024 1:40:26 PM (12 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
162429
Message:

iprt/armv8.h: Data processing instructions with to register inputs. [8] bugref:10376

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/iprt/armv8.h

    r104039 r104040  
    28062806
    28072807/** A64: Encodes an SUBP instruction. */
    2808 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
     2808DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
    28092809{
    28102810    Assert(iRegResult < 32);  Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
    … …  
    28192819
    28202820/** A64: Encodes an SUBPS instruction. */
    2821 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
     2821DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
    28222822{
    28232823    Assert(iRegResult < 32);  Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
    … …  
    28332833
    28342834/** A64: Encodes an UDIV instruction. */
    2835 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
     2835DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
    28362836{
    28372837    Assert(iRegResult < 32);  Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
    … …  
    28462846
    28472847/** A64: Encodes an SDIV instruction. */
    2848 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
     2848DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
    28492849{
    28502850    Assert(iRegResult < 32);  Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
    … …  
    28592859
    28602860/** A64: Encodes an IRG instruction. */
    2861 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
     2861DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
    28622862{
    28632863    Assert(iRegResult < 32);  Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
    … …  
    28722872
    28732873/** A64: Encodes a GMI instruction. */
    2874 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
     2874DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
    28752875{
    28762876    Assert(iRegResult < 32);  Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
    … …  
    28852885
    28862886/** A64: Encodes an LSLV instruction. */
    2887 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
     2887DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
    28882888{
    28892889    Assert(iRegResult < 32);  Assert(iRegSrc < 32); Assert(iRegCount < 32);
    … …  
    28982898
    28992899/** A64: Encodes an LSRV instruction. */
    2900 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
     2900DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
    29012901{
    29022902    Assert(iRegResult < 32);  Assert(iRegSrc < 32); Assert(iRegCount < 32);
    … …  
    29112911
    29122912/** A64: Encodes an ASRV instruction. */
    2913 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
     2913DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
    29142914{
    29152915    Assert(iRegResult < 32);  Assert(iRegSrc < 32); Assert(iRegCount < 32);
    … …  
    29242924
    29252925/** A64: Encodes a RORV instruction. */
    2926 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
     2926DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
    29272927{
    29282928    Assert(iRegResult < 32);  Assert(iRegSrc < 32); Assert(iRegCount < 32);
    … …  
    29372937
    29382938/** A64: Encodes a PACGA instruction. */
    2939 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
     2939DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
    29402940{
    29412941    Assert(iRegResult < 32);  Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
    … …  
    29502950
    29512951/** A64: Encodes a CRC32* instruction. */
    2952 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
     2952DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
    29532953{
    29542954    Assert(iRegResult < 32);  Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
    … …  
    29642964
    29652965/** A64: Encodes a CRC32B instruction. */
    2966 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
    2967 {
    2968     return ArmvA64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
     2966DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
     2967{
     2968    return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
    29692969}
    29702970
    29712971
    29722972/** A64: Encodes a CRC32H instruction. */
    2973 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
    2974 {
    2975     return ArmvA64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
     2973DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
     2974{
     2975    return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
    29762976}
    29772977
    29782978
    29792979/** A64: Encodes a CRC32W instruction. */
    2980 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
    2981 {
    2982     return ArmvA64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
     2980DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
     2981{
     2982    return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
    29832983}
    29842984
    29852985
    29862986/** A64: Encodes a CRC32X instruction. */
    2987 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
    2988 {
    2989     return ArmvA64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
     2987DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
     2988{
     2989    return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
    29902990}
    29912991
    29922992
    29932993/** A64: Encodes a CRC32C* instruction. */
    2994 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
     2994DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
    29952995{
    29962996    Assert(iRegResult < 32);  Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
    … …  
    30063006
    30073007/** A64: Encodes a CRC32B instruction. */
    3008 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
    3009 {
    3010     return ArmvA64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
     3008DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
     3009{
     3010    return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
    30113011}
    30123012
    30133013
    30143014/** A64: Encodes a CRC32CH instruction. */
    3015 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
    3016 {
    3017     return ArmvA64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
     3015DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
     3016{
     3017    return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
    30183018}
    30193019
    30203020
    30213021/** A64: Encodes a CRC32CW instruction. */
    3022 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
    3023 {
    3024     return ArmvA64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
     3022DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
     3023{
     3024    return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
    30253025}
    30263026
    30273027
    30283028/** A64: Encodes a CRC32CX instruction. */
    3029 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
    3030 {
    3031     return ArmvA64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
     3029DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
     3030{
     3031    return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
    30323032}
    30333033
    30343034
    30353035/** A64: Encodes an SMAX instruction. */
    3036 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
     3036DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
    30373037{
    30383038    Assert(iRegResult < 32);  Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
    … …  
    30473047
    30483048/** A64: Encodes an UMAX instruction. */
    3049 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
     3049DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
    30503050{
    30513051    Assert(iRegResult < 32);  Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
    … …  
    30603060
    30613061/** A64: Encodes an SMIN instruction. */
    3062 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
     3062DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
    30633063{
    30643064    Assert(iRegResult < 32);  Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
    … …  
    30733073
    30743074/** A64: Encodes an UMIN instruction. */
    3075 DECL_FORCE_INLINE(uint32_t) ArmvA64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
     3075DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
    30763076{
    30773077    Assert(iRegResult < 32);  Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
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