VirtualBox

Changeset 104056 in vbox


Ignore:
Timestamp:
Mar 26, 2024 10:07:26 AM (12 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
162449
Message:

VMM/IEM: Implement native emitters for IEM_MC_LOCAL_ASSIGN(), IEM_MC_AND_ARG_U16()/IEM_MC_AND_ARG_U32()/IEM_MC_AND_ARG_U64(), IEM_MC_SHL_LOCAL_S16()/IEM_MC_SHL_LOCAL_S32()/IEM_MC_SHL_LOCAL_S64(), IEM_MC_SAR_LOCAL_S16()/IEM_MC_SAR_LOCAL_S32()/IEM_MC_SAR_LOCAL_S64() and IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR()/IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR()/IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR() (enables recompilation of bt/btr/bts instructions), bugref:10371

Location:
trunk
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/iprt/armv8.h

    r104040 r104056  
    34423442
    34433443
     3444/** A64: Encodes an ASR instruction w/ immediate shift value.
     3445 * @see Armv8A64MkInstrBitfieldImm for parameter details.  */
     3446DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
     3447{
     3448    uint32_t const cWidth = f64Bit ? 63 : 31;
     3449    Assert(cShift > 0); Assert(cShift <= cWidth);
     3450    return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
     3451}
     3452
     3453
    34443454/** A64: Encodes a BFM instruction.
    34453455 * @see Armv8A64MkInstrBitfieldImm for parameter details.  */

  • trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py

    r104053 r104056  
    29562956    'IEM_MC_ADD_GREG_U64_TO_LOCAL':                              (McBlock.parseMcGeneric,           False, False, False, ),
    29572957    'IEM_MC_ADD_GREG_U8_TO_LOCAL':                               (McBlock.parseMcGeneric,           False, False, False, ),
    2958     'IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True,  True,  False, ),
    2959     'IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True,  True,  False, ),
    2960     'IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True,  True,  False, ),
     2958    'IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True,  True,  True, ),
     2959    'IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True,  True,  True, ),
     2960    'IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR':                          (McBlock.parseMcGeneric,           True,  True,  True, ),
    29612961    'IEM_MC_ADVANCE_RIP_AND_FINISH':                             (McBlock.parseMcGeneric,           True,  True,  True,  ),
    29622962    'IEM_MC_AND_2LOCS_U32':                                      (McBlock.parseMcGeneric,           False, False, False, ),
    2963     'IEM_MC_AND_ARG_U16':                                        (McBlock.parseMcGeneric,           False, False, False, ),
    2964     'IEM_MC_AND_ARG_U32':                                        (McBlock.parseMcGeneric,           False, False, False, ),
    2965     'IEM_MC_AND_ARG_U64':                                        (McBlock.parseMcGeneric,           False, False, False, ),
     2963    'IEM_MC_AND_ARG_U16':                                        (McBlock.parseMcGeneric,           False, False, True, ),
     2964    'IEM_MC_AND_ARG_U32':                                        (McBlock.parseMcGeneric,           False, False, True, ),
     2965    'IEM_MC_AND_ARG_U64':                                        (McBlock.parseMcGeneric,           False, False, True, ),
    29662966    'IEM_MC_AND_GREG_U16':                                       (McBlock.parseMcGeneric,           True,  True,  True,  ),
    29672967    'IEM_MC_AND_GREG_U32':                                       (McBlock.parseMcGeneric,           True,  True,  True,  ),
    … …  
    32913291    'IEM_MC_REL_JMP_S8_AND_FINISH':                              (McBlock.parseMcGeneric,           True,  True,  False, ),
    32923292    'IEM_MC_RETURN_ON_FAILURE':                                  (McBlock.parseMcGeneric,           False, False, False, ),
    3293     'IEM_MC_SAR_LOCAL_S16':                                      (McBlock.parseMcGeneric,           False, False, False, ),
    3294     'IEM_MC_SAR_LOCAL_S32':                                      (McBlock.parseMcGeneric,           False, False, False, ),
    3295     'IEM_MC_SAR_LOCAL_S64':                                      (McBlock.parseMcGeneric,           False, False, False, ),
     3293    'IEM_MC_SAR_LOCAL_S16':                                      (McBlock.parseMcGeneric,           False, False, True, ),
     3294    'IEM_MC_SAR_LOCAL_S32':                                      (McBlock.parseMcGeneric,           False, False, True, ),
     3295    'IEM_MC_SAR_LOCAL_S64':                                      (McBlock.parseMcGeneric,           False, False, True, ),
    32963296    'IEM_MC_SET_EFL_BIT':                                        (McBlock.parseMcGeneric,           True,  True,  False, ),
    32973297    'IEM_MC_SET_FPU_RESULT':                                     (McBlock.parseMcGeneric,           True,  True,  False, ),
    … …  
    32993299    'IEM_MC_SET_RIP_U32_AND_FINISH':                             (McBlock.parseMcGeneric,           True,  True,  False, ),
    33003300    'IEM_MC_SET_RIP_U64_AND_FINISH':                             (McBlock.parseMcGeneric,           True,  True,  False, ),
    3301     'IEM_MC_SHL_LOCAL_S16':                                      (McBlock.parseMcGeneric,           False, False, False, ),
    3302     'IEM_MC_SHL_LOCAL_S32':                                      (McBlock.parseMcGeneric,           False, False, False, ),
    3303     'IEM_MC_SHL_LOCAL_S64':                                      (McBlock.parseMcGeneric,           False, False, False, ),
     3301    'IEM_MC_SHL_LOCAL_S16':                                      (McBlock.parseMcGeneric,           False, False, True, ),
     3302    'IEM_MC_SHL_LOCAL_S32':                                      (McBlock.parseMcGeneric,           False, False, True, ),
     3303    'IEM_MC_SHL_LOCAL_S64':                                      (McBlock.parseMcGeneric,           False, False, True, ),
    33043304    'IEM_MC_SHR_LOCAL_U8':                                       (McBlock.parseMcGeneric,           False, False, False, ),
    33053305    'IEM_MC_SSE_UPDATE_MXCSR':                                   (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),

  • trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h

    r104053 r104056  
    20682068    uint8_t const a_Name = iemNativeVarAllocConst(pReNative, sizeof(a_Type), (a_Value))
    20692069
     2070#define IEM_MC_LOCAL_ASSIGN(a_Type, a_Name, a_Value) \
     2071    uint8_t const a_Name = iemNativeVarAllocAssign(pReNative, &off, sizeof(a_Type), (a_Value))
     2072
    20702073
    20712074/**
    … …  
    35613564
    35623565/*********************************************************************************************************************************
    3563 *   Local variable manipulation (add, sub, and, or).                                                                             *
     3566*   Local/Argument variable manipulation (add, sub, and, or).                                                                             *
    35643567*********************************************************************************************************************************/
    35653568
    … …  
    35753578#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) \
    35763579    off = iemNativeEmitAndLocal(pReNative, off, a_u64Local, a_u64Mask, sizeof(uint64_t))
     3580
     3581
     3582#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) \
     3583    off = iemNativeEmitAndLocal(pReNative, off, a_u16Arg, a_u16Mask, sizeof(uint16_t))
     3584
     3585#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) \
     3586    off = iemNativeEmitAndLocal(pReNative, off, a_u32Arg, a_u32Mask, sizeof(uint32_t))
     3587
     3588#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) \
     3589    off = iemNativeEmitAndLocal(pReNative, off, a_u64Arg, a_u64Mask, sizeof(uint64_t))
    35773590
    35783591/** Emits code for AND'ing a local and a constant value.   */
    … …  
    36683681    }
    36693682
     3683    iemNativeVarRegisterRelease(pReNative, idxVar);
     3684    return off;
     3685}
     3686
     3687
     3688#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) \
     3689    off = iemNativeEmitShlLocal(pReNative, off, a_i16Local, sizeof(int16_t), a_cShift)
     3690
     3691#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) \
     3692    off = iemNativeEmitShlLocal(pReNative, off, a_i32Local, sizeof(int32_t), a_cShift)
     3693
     3694#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) \
     3695    off = iemNativeEmitShlLocal(pReNative, off, a_i64Local, sizeof(int64_t), a_cShift)
     3696
     3697/** Emits code for shifting left a local value.   */
     3698DECL_INLINE_THROW(uint32_t)
     3699iemNativeEmitShlLocal(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar, uint8_t cbLocal, uint8_t cShift)
     3700{
     3701#ifdef VBOX_STRICT
     3702    switch (cbLocal)
     3703    {
     3704        case sizeof(uint8_t):  Assert(cShift < 8); break;
     3705        case sizeof(uint16_t): Assert(cShift < 16); break;
     3706        case sizeof(uint32_t): Assert(cShift < 32); break;
     3707        case sizeof(uint64_t): Assert(cShift < 64); break;
     3708        default: AssertFailedBreak();
     3709    }
     3710#endif
     3711
     3712    uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxVar, &off, true /*fInitialized*/);
     3713    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxVar, cbLocal);
     3714
     3715    if (cbLocal <= sizeof(uint32_t))
     3716        off = iemNativeEmitShiftGpr32Left(pReNative, off, idxVarReg, cShift);
     3717    else
     3718        off = iemNativeEmitShiftGprLeft(pReNative, off, idxVarReg, cShift);
     3719
     3720    iemNativeVarRegisterRelease(pReNative, idxVar);
     3721    return off;
     3722}
     3723
     3724
     3725#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) \
     3726    off = iemNativeEmitSarLocal(pReNative, off, a_i16Local, sizeof(int16_t), a_cShift)
     3727
     3728#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) \
     3729    off = iemNativeEmitSarLocal(pReNative, off, a_i32Local, sizeof(int32_t), a_cShift)
     3730
     3731#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) \
     3732    off = iemNativeEmitSarLocal(pReNative, off, a_i64Local, sizeof(int64_t), a_cShift)
     3733
     3734/** Emits code for shifting left a local value.   */
     3735DECL_INLINE_THROW(uint32_t)
     3736iemNativeEmitSarLocal(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar, uint8_t cbLocal, uint8_t cShift)
     3737{
     3738#ifdef VBOX_STRICT
     3739    switch (cbLocal)
     3740    {
     3741        case sizeof(int8_t):  Assert(cShift < 8); break;
     3742        case sizeof(int16_t): Assert(cShift < 16); break;
     3743        case sizeof(int32_t): Assert(cShift < 32); break;
     3744        case sizeof(int64_t): Assert(cShift < 64); break;
     3745        default: AssertFailedBreak();
     3746    }
     3747#endif
     3748
     3749    uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxVar, &off, true /*fInitialized*/);
     3750    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxVar, cbLocal);
     3751
     3752    if (cbLocal <= sizeof(uint32_t))
     3753        off = iemNativeEmitArithShiftGpr32Right(pReNative, off, idxVarReg, cShift);
     3754    else
     3755        off = iemNativeEmitArithShiftGprRight(pReNative, off, idxVarReg, cShift);
     3756
     3757    iemNativeVarRegisterRelease(pReNative, idxVar);
     3758    return off;
     3759}
     3760
     3761
     3762#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) \
     3763    off = iemNativeEmitAddLocalToEffAddr(pReNative, off, a_EffAddr, a_i16, sizeof(int16_t))
     3764
     3765#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) \
     3766    off = iemNativeEmitAddLocalToEffAddr(pReNative, off, a_EffAddr, a_i32, sizeof(int32_t))
     3767
     3768#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) \
     3769    off = iemNativeEmitAddLocalToEffAddr(pReNative, off, a_EffAddr, a_i64, sizeof(int64_t))
     3770
     3771/** Emits code for IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR/IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR/IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR.   */
     3772DECL_INLINE_THROW(uint32_t)
     3773iemNativeEmitAddLocalToEffAddr(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVarEffAddr, uint8_t idxVar, uint8_t cbLocal)
     3774{
     3775    IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarEffAddr);
     3776    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxVarEffAddr, sizeof(RTGCPTR));
     3777    IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
     3778    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxVar, cbLocal); RT_NOREF(cbLocal);
     3779
     3780    uint8_t const idxVarReg        = iemNativeVarRegisterAcquire(pReNative, idxVar, &off, true /*fInitialized*/);
     3781    uint8_t const idxVarRegEffAddr = iemNativeVarRegisterAcquire(pReNative, idxVarEffAddr, &off, true /*fInitialized*/);
     3782
     3783    /* Need to sign extend the value. */
     3784    if (cbLocal <= sizeof(uint32_t))
     3785    {
     3786        uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off, idxVar);
     3787
     3788        switch (cbLocal)
     3789        {
     3790            case sizeof(int8_t):  off = iemNativeEmitLoadGprSignExtendedFromGpr8(pReNative, off, idxRegTmp, idxVarReg); break;
     3791            case sizeof(int16_t): off = iemNativeEmitLoadGprSignExtendedFromGpr16(pReNative, off, idxRegTmp, idxVarReg); break;
     3792            case sizeof(int32_t): off = iemNativeEmitLoadGprSignExtendedFromGpr32(pReNative, off, idxRegTmp, idxVarReg); break;
     3793            default: AssertFailed();
     3794        }
     3795
     3796        off = iemNativeEmitAddTwoGprs(pReNative, off, idxVarRegEffAddr, idxRegTmp);
     3797        iemNativeRegFreeTmp(pReNative, idxRegTmp);
     3798    }
     3799    else
     3800        off = iemNativeEmitAddTwoGprs(pReNative, off, idxVarRegEffAddr, idxVarReg);
     3801
     3802    iemNativeVarRegisterRelease(pReNative, idxVarEffAddr);
    36703803    iemNativeVarRegisterRelease(pReNative, idxVar);
    36713804    return off;

  • trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp

    r104049 r104056  
    81978197    }
    81988198    iemNativeVarSetKindToConst(pReNative, idxVar, uValue);
     8199    return idxVar;
     8200}
     8201
     8202
     8203DECL_HIDDEN_THROW(uint8_t)  iemNativeVarAllocAssign(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint8_t cbType, uint8_t idxVarOther)
     8204{
     8205    uint8_t const idxVar = IEMNATIVE_VAR_IDX_PACK(iemNativeVarAllocInt(pReNative, cbType));
     8206    iemNativeVarSetKindToStack(pReNative, IEMNATIVE_VAR_IDX_PACK(idxVar));
     8207
     8208    uint8_t const idxVarOtherReg = iemNativeVarRegisterAcquire(pReNative, idxVarOther, poff, true /*fInitialized*/);
     8209    uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxVar, poff);
     8210
     8211    *poff = iemNativeEmitLoadGprFromGpr(pReNative, *poff, idxVarReg, idxVarOtherReg);
     8212
     8213    /* Truncate the value to this variables size. */
     8214    switch (cbType)
     8215    {
     8216        case sizeof(uint8_t):   *poff = iemNativeEmitAndGpr32ByImm(pReNative, *poff, idxVarReg, UINT64_C(0xff)); break;
     8217        case sizeof(uint16_t):  *poff = iemNativeEmitAndGpr32ByImm(pReNative, *poff, idxVarReg, UINT64_C(0xffff)); break;
     8218        case sizeof(uint32_t):  *poff = iemNativeEmitAndGpr32ByImm(pReNative, *poff, idxVarReg, UINT64_C(0xffffffff)); break;
     8219    }
     8220
     8221    iemNativeVarRegisterRelease(pReNative, idxVarOther);
     8222    iemNativeVarRegisterRelease(pReNative, idxVar);
    81998223    return idxVar;
    82008224}

  • trunk/src/VBox/VMM/include/IEMN8veRecompiler.h

    r104047 r104056  
    16171617DECL_HIDDEN_THROW(uint8_t)  iemNativeVarAlloc(PIEMRECOMPILERSTATE pReNative, uint8_t cbType);
    16181618DECL_HIDDEN_THROW(uint8_t)  iemNativeVarAllocConst(PIEMRECOMPILERSTATE pReNative, uint8_t cbType, uint64_t uValue);
     1619DECL_HIDDEN_THROW(uint8_t)  iemNativeVarAllocAssign(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint8_t cbType, uint8_t idxVarOther);
    16191620DECL_HIDDEN_THROW(void)     iemNativeVarSetKindToStack(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
    16201621DECL_HIDDEN_THROW(void)     iemNativeVarSetKindToConst(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint64_t uValue);

  • trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h

    r104033 r104056  
    56705670
    56715671/**
     5672 * Emits code for (signed) shifting a GPR a fixed number of bits to the right.
     5673 */
     5674DECL_FORCE_INLINE(uint32_t)
     5675iemNativeEmitArithShiftGprRightEx(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iGprDst, uint8_t cShift)
     5676{
     5677    Assert(cShift > 0 && cShift < 64);
     5678
     5679#if defined(RT_ARCH_AMD64)
     5680    /* sar dst, cShift */
     5681    pCodeBuf[off++] = iGprDst < 8 ? X86_OP_REX_W : X86_OP_REX_W | X86_OP_REX_B;
     5682    if (cShift != 1)
     5683    {
     5684        pCodeBuf[off++] = 0xc1;
     5685        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, iGprDst & 7);
     5686        pCodeBuf[off++] = cShift;
     5687    }
     5688    else
     5689    {
     5690        pCodeBuf[off++] = 0xd1;
     5691        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, iGprDst & 7);
     5692    }
     5693
     5694#elif defined(RT_ARCH_ARM64)
     5695    pCodeBuf[off++] = Armv8A64MkInstrAsrImm(iGprDst, iGprDst, cShift);
     5696
     5697#else
     5698# error "Port me"
     5699#endif
     5700    return off;
     5701}
     5702
     5703
     5704/**
     5705 * Emits code for (signed) shifting a GPR a fixed number of bits to the right.
     5706 */
     5707DECL_INLINE_THROW(uint32_t)
     5708iemNativeEmitArithShiftGprRight(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGprDst, uint8_t cShift)
     5709{
     5710#if defined(RT_ARCH_AMD64)
     5711    off = iemNativeEmitArithShiftGprRightEx(iemNativeInstrBufEnsure(pReNative, off, 4), off, iGprDst, cShift);
     5712#elif defined(RT_ARCH_ARM64)
     5713    off = iemNativeEmitArithShiftGprRightEx(iemNativeInstrBufEnsure(pReNative, off, 1), off, iGprDst, cShift);
     5714#else
     5715# error "Port me"
     5716#endif
     5717    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     5718    return off;
     5719}
     5720
     5721
     5722/**
     5723 * Emits code for (signed) shifting a 32-bit GPR a fixed number of bits to the right.
     5724 */
     5725DECL_FORCE_INLINE(uint32_t)
     5726iemNativeEmitArithShiftGpr32RightEx(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iGprDst, uint8_t cShift)
     5727{
     5728    Assert(cShift > 0 && cShift < 64);
     5729
     5730#if defined(RT_ARCH_AMD64)
     5731    /* sar dst, cShift */
     5732    if (iGprDst >= 8)
     5733        pCodeBuf[off++] = X86_OP_REX_B;
     5734    if (cShift != 1)
     5735    {
     5736        pCodeBuf[off++] = 0xc1;
     5737        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, iGprDst & 7);
     5738        pCodeBuf[off++] = cShift;
     5739    }
     5740    else
     5741    {
     5742        pCodeBuf[off++] = 0xd1;
     5743        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, iGprDst & 7);
     5744    }
     5745
     5746#elif defined(RT_ARCH_ARM64)
     5747    pCodeBuf[off++] = Armv8A64MkInstrAsrImm(iGprDst, iGprDst, cShift, false /*f64Bit*/);
     5748
     5749#else
     5750# error "Port me"
     5751#endif
     5752    return off;
     5753}
     5754
     5755
     5756/**
     5757 * Emits code for (signed) shifting a GPR a fixed number of bits to the right.
     5758 */
     5759DECL_INLINE_THROW(uint32_t)
     5760iemNativeEmitArithShiftGpr32Right(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iGprDst, uint8_t cShift)
     5761{
     5762#if defined(RT_ARCH_AMD64)
     5763    off = iemNativeEmitArithShiftGpr32RightEx(iemNativeInstrBufEnsure(pReNative, off, 4), off, iGprDst, cShift);
     5764#elif defined(RT_ARCH_ARM64)
     5765    off = iemNativeEmitArithShiftGpr32RightEx(iemNativeInstrBufEnsure(pReNative, off, 1), off, iGprDst, cShift);
     5766#else
     5767# error "Port me"
     5768#endif
     5769    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
     5770    return off;
     5771}
     5772
     5773
     5774/**
    56725775 * Emits code for rotating a GPR a fixed number of bits to the left.
    56735776 */
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