Changeset 104087 in vbox

Timestamp:

Mar 27, 2024 2:23:52 PM (13 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162488

Message:

VMM/IEM: Implement native emitters for IEM_MC_STORE_XREG_U8() and IEM_MC_STORE_XREG_U16(), bugref:10614

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllInstPython.py (modified) (2 diffs)
• VMMAll/IEMAllN8veRecompFuncs.h (modified) (2 diffs)
• include/IEMN8veRecompilerEmit.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py

@@ -3354 +3354 @@
     'IEM_MC_STORE_XREG_R64':                                     (McBlock.parseMcGeneric,           True,  True,  False, ),
     'IEM_MC_STORE_XREG_U128':                                    (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
-    'IEM_MC_STORE_XREG_U16':                                     (McBlock.parseMcGeneric,           True,  True,  False, ),
+    'IEM_MC_STORE_XREG_U16':                                     (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
     'IEM_MC_STORE_XREG_U32':                                     (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
     'IEM_MC_STORE_XREG_U32_U128':                                (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
@@ -3360 +3360 @@
     'IEM_MC_STORE_XREG_U64':                                     (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
     'IEM_MC_STORE_XREG_U64_ZX_U128':                             (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
-    'IEM_MC_STORE_XREG_U8':                                      (McBlock.parseMcGeneric,           True,  True,  False, ),
+    'IEM_MC_STORE_XREG_U8':                                      (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
     'IEM_MC_STORE_XREG_XMM':                                     (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
     'IEM_MC_STORE_XREG_XMM_U32':                                 (McBlock.parseMcGeneric,           True,  True,  False, ),

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h

@@ -7725 +7725 @@
 
 #define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQWord, a_u64Value) \
-    off = iemNativeEmitSimdStoreXregU64(pReNative, off, a_iXReg, a_u64Value, a_iQWord)
-
-/** Emits code for IEM_MC_STORE_XREG_U64. */
-DECL_INLINE_THROW(uint32_t)
-iemNativeEmitSimdStoreXregU64(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iXReg, uint8_t idxDstVar, uint8_t iQWord)
+    off = iemNativeEmitSimdStoreXregUxx(pReNative, off, a_iXReg, a_u64Value, sizeof(uint64_t), a_iQWord)
+
+#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDWord, a_u32Value) \
+    off = iemNativeEmitSimdStoreXregUxx(pReNative, off, a_iXReg, a_u32Value, sizeof(uint32_t), a_iDWord)
+
+#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u32Value) \
+    off = iemNativeEmitSimdStoreXregUxx(pReNative, off, a_iXReg, a_u32Value, sizeof(uint16_t), a_iWord)
+
+#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u32Value) \
+    off = iemNativeEmitSimdStoreXregUxx(pReNative, off, a_iXReg, a_u32Value, sizeof(uint8_t), a_iByte)
+
+/** Emits code for IEM_MC_STORE_XREG_U64/IEM_MC_STORE_XREG_U32/IEM_MC_STORE_XREG_U16/IEM_MC_STORE_XREG_U8. */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmitSimdStoreXregUxx(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iXReg, uint8_t idxDstVar, uint8_t cbLocal, uint8_t iElem)
 {
     IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
-    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxDstVar, sizeof(uint64_t));
+    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxDstVar, cbLocal);
+
+#ifdef VBOX_STRICT
+    switch (cbLocal)
+    {
+        case sizeof(uint64_t): Assert(iElem <  2); break;
+        case sizeof(uint32_t): Assert(iElem <  4); break;
+        case sizeof(uint16_t): Assert(iElem <  8); break;
+        case sizeof(uint8_t):  Assert(iElem < 16); break;
+        default: AssertFailed();
+    }
+#endif
 
     uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg),
@@ -7739 +7759 @@
     uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
 
-    off = iemNativeEmitSimdStoreGprToVecRegU64(pReNative, off, idxSimdRegDst, idxVarReg, iQWord);
-
-    /* Free but don't flush the source register. */
-    iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst);
-    iemNativeVarRegisterRelease(pReNative, idxDstVar);
-
-    return off;
-}
-
-
-#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDWord, a_u32Value) \
-    off = iemNativeEmitSimdStoreXregU32(pReNative, off, a_iXReg, a_u32Value, a_iDWord)
-
-/** Emits code for IEM_MC_STORE_XREG_U32. */
-DECL_INLINE_THROW(uint32_t)
-iemNativeEmitSimdStoreXregU32(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iXReg, uint8_t idxDstVar, uint8_t iDWord)
-{
-    IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxDstVar);
-    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxDstVar, sizeof(uint32_t));
-
-    uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg),
-                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate);
-
-    uint8_t const idxVarReg = iemNativeVarRegisterAcquire(pReNative, idxDstVar, &off);
-
-    off = iemNativeEmitSimdStoreGprToVecRegU32(pReNative, off, idxSimdRegDst, idxVarReg, iDWord);
+    switch (cbLocal)
+    {
+        case sizeof(uint64_t): off = iemNativeEmitSimdStoreGprToVecRegU64(pReNative, off, idxSimdRegDst, idxVarReg, iElem); break;
+        case sizeof(uint32_t): off = iemNativeEmitSimdStoreGprToVecRegU32(pReNative, off, idxSimdRegDst, idxVarReg, iElem); break;
+        case sizeof(uint16_t): off = iemNativeEmitSimdStoreGprToVecRegU16(pReNative, off, idxSimdRegDst, idxVarReg, iElem); break;
+        case sizeof(uint8_t):  off = iemNativeEmitSimdStoreGprToVecRegU8(pReNative, off, idxSimdRegDst, idxVarReg, iElem); break;
+        default: AssertFailed();
+    }
 
     /* Free but don't flush the source register. */

trunk/src/VBox/VMM/include/IEMN8veRecompilerEmit.h

@@ -8613 +8613 @@
 
 /**
+ * Emits a vecdst[x] = gprsrc store, 16-bit.
+ */
+DECL_FORCE_INLINE(uint32_t)
+iemNativeEmitSimdStoreGprToVecRegU16Ex(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iVecRegDst, uint8_t iGprSrc, uint8_t iWord)
+{
+#ifdef RT_ARCH_AMD64
+    /* pinsrw vecsrc, gpr, #iWord. */
+    pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    if (iVecRegDst >= 8 || iGprSrc >= 8)
+        pCodeBuf[off++] =   (iVecRegDst < 8 ? 0 : X86_OP_REX_R)
+                          | (iGprSrc < 8 ? 0 : X86_OP_REX_B);
+    pCodeBuf[off++] = 0x0f;
+    pCodeBuf[off++] = 0xc4;
+    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iGprSrc & 7);
+    pCodeBuf[off++] = iWord;
+#elif defined(RT_ARCH_ARM64)
+    /* ins vecsrc[iWord], gpr */
+    pCodeBuf[off++] = Armv8A64MkVecInstrIns(iVecRegDst, iGprSrc, iWord, kArmv8InstrUmovInsSz_U16);
+#else
+# error "port me"
+#endif
+    return off;
+}
+
+
+/**
+ * Emits a vecdst[x] = gprsrc store, 16-bit.
+ */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmitSimdStoreGprToVecRegU16(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iVecRegDst, uint8_t iGprSrc, uint8_t iWord)
+{
+    Assert(iWord <= 15);
+
+#ifdef RT_ARCH_AMD64
+    off = iemNativeEmitSimdStoreGprToVecRegU16Ex(iemNativeInstrBufEnsure(pReNative, off, 6), off, iVecRegDst, iGprSrc, iWord);
+#elif defined(RT_ARCH_ARM64)
+    off = iemNativeEmitSimdStoreGprToVecRegU16Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecRegDst, iGprSrc, iWord);
+#else
+# error "port me"
+#endif
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+    return off;
+}
+
+
+/**
+ * Emits a vecdst[x] = gprsrc store, 8-bit.
+ */
+DECL_FORCE_INLINE(uint32_t)
+iemNativeEmitSimdStoreGprToVecRegU8Ex(PIEMNATIVEINSTR pCodeBuf, uint32_t off, uint8_t iVecRegDst, uint8_t iGprSrc, uint8_t iByte)
+{
+#ifdef RT_ARCH_AMD64
+    /* pinsrb vecsrc, gpr, #iByte (ASSUMES SSE4.1). */
+    pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    if (iVecRegDst >= 8 || iGprSrc >= 8)
+        pCodeBuf[off++] =   (iVecRegDst < 8 ? 0 : X86_OP_REX_R)
+                          | (iGprSrc < 8 ? 0 : X86_OP_REX_B);
+    pCodeBuf[off++] = 0x0f;
+    pCodeBuf[off++] = 0x3a;
+    pCodeBuf[off++] = 0x20;
+    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, iVecRegDst & 7, iGprSrc & 7);
+    pCodeBuf[off++] = iByte;
+#elif defined(RT_ARCH_ARM64)
+    /* ins vecsrc[iByte], gpr */
+    pCodeBuf[off++] = Armv8A64MkVecInstrIns(iVecRegDst, iGprSrc, iByte, kArmv8InstrUmovInsSz_U8);
+#else
+# error "port me"
+#endif
+    return off;
+}
+
+
+/**
+ * Emits a vecdst[x] = gprsrc store, 8-bit.
+ */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmitSimdStoreGprToVecRegU8(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t iVecRegDst, uint8_t iGprSrc, uint8_t iByte)
+{
+    Assert(iByte <= 15);
+
+#ifdef RT_ARCH_AMD64
+    off = iemNativeEmitSimdStoreGprToVecRegU8Ex(iemNativeInstrBufEnsure(pReNative, off, 7), off, iVecRegDst, iGprSrc, iByte);
+#elif defined(RT_ARCH_ARM64)
+    off = iemNativeEmitSimdStoreGprToVecRegU8Ex(iemNativeInstrBufEnsure(pReNative, off, 1), off, iVecRegDst, iGprSrc, iByte);
+#else
+# error "port me"
+#endif
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+    return off;
+}
+
+
+/**
  * Emits a vecdst.au32[iDWord] = 0 store.
  */