Changeset 104129 in vbox for trunk/src/VBox
- Timestamp:
- Apr 2, 2024 12:37:36 PM (12 months ago)
- svn:sync-xref-src-repo-rev:
- 162550
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 14 edited
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VMMAll/IEMAll.cpp (modified) (1 diff)
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VMMAll/IEMAllAImpl.asm (modified) (27 diffs)
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VMMAll/IEMAllAImplC.cpp (modified) (69 diffs)
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VMMAll/IEMAllInstPython.py (modified) (2 diffs)
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VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (47 diffs)
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VMMAll/IEMAllInstVexMap1.cpp.h (modified) (12 diffs)
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VMMAll/IEMAllN8veLiveness.cpp (modified) (2 diffs)
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VMMAll/IEMAllN8veRecompFuncs.h (modified) (7 diffs)
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VMMAll/IEMAllN8veRecompiler.cpp (modified) (3 diffs)
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VMMAll/IEMAllThrdPython.py (modified) (2 diffs)
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include/IEMInternal.h (modified) (8 diffs)
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include/IEMMc.h (modified) (4 diffs)
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testcase/tstIEMAImpl.cpp (modified) (114 diffs)
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testcase/tstIEMCheckMc.cpp (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r103951 r104129 5483 5483 } 5484 5484 5485 /** @} */5486 5487 5488 /** @name SSE+AVX SIMD access and helpers.5489 *5490 * @{5491 */5492 /**5493 * Stores a result in a SIMD XMM register, updates the MXCSR.5494 *5495 * @param pVCpu The cross context virtual CPU structure of the calling thread.5496 * @param pResult The result to store.5497 * @param iXmmReg Which SIMD XMM register to store the result in.5498 */5499 void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT5500 {5501 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;5502 pFpuCtx->MXCSR |= pResult->MXCSR & X86_MXCSR_XCPT_FLAGS;5503 5504 /* The result is only updated if there is no unmasked exception pending. */5505 if (( ~((pFpuCtx->MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT)5506 & (pFpuCtx->MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0)5507 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXmmReg] = pResult->uResult;5508 }5509 5510 5511 /**5512 * Updates the MXCSR.5513 *5514 * @param pVCpu The cross context virtual CPU structure of the calling thread.5515 * @param fMxcsr The new MXCSR value.5516 */5517 void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT5518 {5519 PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;5520 pFpuCtx->MXCSR |= fMxcsr & X86_MXCSR_XCPT_FLAGS;5521 }5522 5485 /** @} */ 5523 5486 -
trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
r104128 r104129 5 5 6 6 ; 7 ; Copyright (C) 2011-202 3Oracle and/or its affiliates.7 ; Copyright (C) 2011-2024 Oracle and/or its affiliates. 8 8 ; 9 9 ; This file is part of VirtualBox base platform packages, as … … 184 184 %define T2_16 r10w 185 185 %define T2_8 r10b 186 187 ; 188 ; Return value, same as T0 but to make it more obvious 189 ; that this is a return value. 190 ; 191 %define R0 rax 192 %define R0_32 eax 193 %define R0_16 ax 194 %define R0_8 al 186 195 187 196 %else … … 4810 4819 ; Need to move this as well somewhere better? 4811 4820 ; 4812 struc IEMSSERESULT4813 .uResult resd 44814 .MXCSR resd 14815 endstruc4816 4817 4818 ;;4819 ; Need to move this as well somewhere better?4820 ;4821 4821 struc IEMAVX128RESULT 4822 4822 .uResult resd 4 … … 4836 4836 ;; 4837 4837 ; Initialize the SSE MXCSR register using the guest value partially to 4838 ; account for rounding mode .4838 ; account for rounding mode, load the value from the given register. 4839 4839 ; 4840 4840 ; @uses 4 bytes of stack to save the original value, T0. 4841 ; @param 1 Expression giving the address of the FXSTATE of the guest.4842 ; 4843 %macro SSE_LD_ FXSTATE_MXCSR 14841 ; @param 1 Expression giving the register holding the guest's MXCSR. 4842 ; 4843 %macro SSE_LD_MXCSR 1 4844 4844 sub xSP, 4 4845 4845 4846 4846 stmxcsr [xSP] 4847 mov T0_32, [%1 + X86FXSTATE.MXCSR]4847 mov T0_32, %1 4848 4848 and T0_32, X86_MXCSR_FZ | X86_MXCSR_RC_MASK | X86_MXCSR_DAZ 4849 4849 or T0_32, X86_MXCSR_XCPT_MASK … … 4859 4859 ; 4860 4860 ; @uses 4 bytes of stack to save the content of MXCSR value, T0, T1. 4861 ; @param 1 Expression giving the address where to return theMXCSR value.4862 ; @param 2 Expression giving the address of the FXSTATE of the guest.4861 ; @param 1 Expression giving the register to return the new guest's MXCSR value. 4862 ; @param 2 Expression giving the register holding original guest's MXCSR value. 4863 4863 ; 4864 4864 ; @note Restores the stack pointer. 4865 4865 ; 4866 %macro SSE_ST_ FXSTATE_MXCSR 24866 %macro SSE_ST_MXCSR 2 4867 4867 sub xSP, 4 4868 4868 stmxcsr [xSP] 4869 mov T0_32, [xSP]4869 mov %1, [xSP] 4870 4870 add xSP, 4 4871 4871 ; Merge the status bits into the original MXCSR value. 4872 mov T1_32, [%2 + X86FXSTATE.MXCSR] 4873 and T0_32, X86_MXCSR_XCPT_FLAGS 4874 or T0_32, T1_32 4875 mov [%1 + IEMSSERESULT.MXCSR], T0_32 4872 and %1, X86_MXCSR_XCPT_FLAGS 4873 or %1, %2 4876 4874 4877 4875 ldmxcsr [xSP] … … 4936 4934 ; @param 2 Flag whether the AVX variant of the instruction takes two or three operands, 0 to disable AVX variants 4937 4935 ; 4938 ; @param A0 FPU context (FXSTATE or XSAVEAREA). 4939 ; @param A1 Where to return the result including the MXCSR value. 4936 ; @returns R0_32 The new MXCSR value of the guest. 4937 ; @param A0 The guest's MXCSR register value to use. 4938 ; @param A1 Where to return the result. 4940 4939 ; @param A2 Pointer to the first media register size operand (input/output). 4941 4940 ; @param A3 Pointer to the second media register size operand (input). … … 4945 4944 PROLOGUE_4_ARGS 4946 4945 IEMIMPL_SSE_PROLOGUE 4947 SSE_LD_ FXSTATE_MXCSR A04946 SSE_LD_MXCSR A0_32 4948 4947 4949 4948 movdqu xmm0, [A2] 4950 4949 movdqu xmm1, [A3] 4951 4950 %1 xmm0, xmm1 4952 movdqu [A1 + IEMSSERESULT.uResult], xmm04953 4954 SSE_ST_ FXSTATE_MXCSR A1, A04951 movdqu [A1], xmm0 4952 4953 SSE_ST_MXCSR R0_32, A0_32 4955 4954 IEMIMPL_SSE_PROLOGUE 4956 4955 EPILOGUE_4_ARGS … … 5062 5061 ; @param 1 The instruction 5063 5062 ; 5064 ; @param A0 FPU context (FXSTATE or XSAVEAREA). 5065 ; @param A1 Where to return the result including the MXCSR value. 5063 ; @return R0_32 The new MXCSR value of the guest. 5064 ; @param A0 The guest's MXCSR register value to use. 5065 ; @param A1 Where to return the result. 5066 5066 ; @param A2 Pointer to the first media register size operand (input/output). 5067 5067 ; @param A3 Pointer to the second single precision floating point value (input). … … 5071 5071 PROLOGUE_4_ARGS 5072 5072 IEMIMPL_SSE_PROLOGUE 5073 SSE_LD_ FXSTATE_MXCSR A05073 SSE_LD_MXCSR A0_32 5074 5074 5075 5075 movdqu xmm0, [A2] 5076 5076 movd xmm1, [A3] 5077 5077 %1 xmm0, xmm1 5078 movdqu [A1 + IEMSSERESULT.uResult], xmm05079 5080 SSE_ST_ FXSTATE_MXCSR A1, A05078 movdqu [A1], xmm0 5079 5080 SSE_ST_MXCSR R0_32, A0_32 5081 5081 IEMIMPL_SSE_EPILOGUE 5082 5082 EPILOGUE_4_ARGS … … 5116 5116 ; @param 1 The instruction 5117 5117 ; 5118 ; @param A0 FPU context (FXSTATE or XSAVEAREA). 5119 ; @param A1 Where to return the result including the MXCSR value. 5118 ; @return R0_32 The new MXCSR value of the guest. 5119 ; @param A0 The guest's MXCSR register value to use. 5120 ; @param A1 Where to return the result. 5120 5121 ; @param A2 Pointer to the first media register size operand (input/output). 5121 5122 ; @param A3 Pointer to the second double precision floating point value (input). … … 5125 5126 PROLOGUE_4_ARGS 5126 5127 IEMIMPL_SSE_PROLOGUE 5127 SSE_LD_ FXSTATE_MXCSR A05128 SSE_LD_MXCSR A0_32 5128 5129 5129 5130 movdqu xmm0, [A2] 5130 5131 movq xmm1, [A3] 5131 5132 %1 xmm0, xmm1 5132 movdqu [A1 + IEMSSERESULT.uResult], xmm05133 5134 SSE_ST_ FXSTATE_MXCSR A1, A05133 movdqu [A1], xmm0 5134 5135 SSE_ST_MXCSR R0_32, A0_32 5135 5136 IEMIMPL_SSE_EPILOGUE 5136 5137 EPILOGUE_4_ARGS … … 5169 5170 ; 2 Whether the AVX256 result is 128-bit (0) or 256-bit (1). 5170 5171 ; 5171 ; @param A0 FPU context (FXSTATE or XSAVEAREA). 5172 ; @param A1 Where to return the result including the MXCSR value. 5172 ; @return R0_32 The new MXCSR value of the guest. 5173 ; @param A0_32 The guest's MXCSR register value to use. 5174 ; @param A1 Where to return the result. 5173 5175 ; @param A2 Pointer to the first media register size operand (input/output). 5174 5176 ; @param A3 Pointer to the second media register size operand (input). … … 5178 5180 PROLOGUE_4_ARGS 5179 5181 IEMIMPL_SSE_PROLOGUE 5180 SSE_LD_ FXSTATE_MXCSR A05182 SSE_LD_MXCSR A0_32 5181 5183 5182 5184 movdqu xmm0, [A2] 5183 5185 movdqu xmm1, [A3] 5184 5186 %1 xmm0, xmm1 5185 movdqu [A1 + IEMSSERESULT.uResult], xmm05186 5187 SSE_ST_ FXSTATE_MXCSR A1, A05187 movdqu [A1], xmm0 5188 5189 SSE_ST_MXCSR R0_32, A0_32 5188 5190 IEMIMPL_SSE_EPILOGUE 5189 5191 EPILOGUE_4_ARGS … … 5978 5980 5979 5981 ;; 5980 ; Restores the SSE MXCSR register with the original value.5981 ;5982 ; @uses 4 bytes of stack to save the content of MXCSR value, T0, T1.5983 ; @param 1 Expression giving the address where to return the MXCSR value - only the MXCSR is stored, no IEMSSERESULT is used.5984 ; @param 2 Expression giving the address of the FXSTATE of the guest.5985 ;5986 ; @note Restores the stack pointer.5987 ;5988 %macro SSE_ST_FXSTATE_MXCSR_ONLY 25989 sub xSP, 45990 stmxcsr [xSP]5991 mov T0_32, [xSP]5992 add xSP, 45993 ; Merge the status bits into the original MXCSR value.5994 mov T1_32, [%2 + X86FXSTATE.MXCSR]5995 and T0_32, X86_MXCSR_XCPT_FLAGS5996 or T0_32, T1_325997 mov [%1], T0_325998 5999 ldmxcsr [xSP]6000 add xSP, 46001 %endmacro6002 6003 6004 ;;6005 5982 ; cvttsd2si instruction - 32-bit variant. 6006 5983 ; 6007 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6008 ; @param A 1 Where to return the MXCSR value.6009 ; @param A 2Pointer to the result operand (output).6010 ; @param A 3Pointer to the second operand (input).5984 ; @return R0_32 The new MXCSR value of the guest. 5985 ; @param A0_32 The guest's MXCSR register value to use. 5986 ; @param A1 Pointer to the result operand (output). 5987 ; @param A2 Pointer to the second operand (input). 6011 5988 ; 6012 5989 BEGINPROC_FASTCALL iemAImpl_cvttsd2si_i32_r64, 16 6013 5990 PROLOGUE_4_ARGS 6014 5991 IEMIMPL_SSE_PROLOGUE 6015 SSE_LD_ FXSTATE_MXCSR A06016 6017 cvttsd2si T0_32, [A 3]6018 mov dword [A 2], T0_326019 6020 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A05992 SSE_LD_MXCSR A0_32 5993 5994 cvttsd2si T0_32, [A2] 5995 mov dword [A1], T0_32 5996 5997 SSE_ST_MXCSR R0_32, A0_32 6021 5998 IEMIMPL_SSE_EPILOGUE 6022 5999 EPILOGUE_4_ARGS … … 6026 6003 ; cvttsd2si instruction - 64-bit variant. 6027 6004 ; 6028 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6029 ; @param A 1 Where to return the MXCSR value.6030 ; @param A 2Pointer to the result operand (output).6031 ; @param A 3Pointer to the second operand (input).6005 ; @return R0_32 The new MXCSR value of the guest. 6006 ; @param A0_32 The guest's MXCSR register value to use. 6007 ; @param A1 Pointer to the result operand (output). 6008 ; @param A2 Pointer to the second operand (input). 6032 6009 ; 6033 6010 BEGINPROC_FASTCALL iemAImpl_cvttsd2si_i64_r64, 16 6034 PROLOGUE_ 4_ARGS6011 PROLOGUE_3_ARGS 6035 6012 IEMIMPL_SSE_PROLOGUE 6036 SSE_LD_ FXSTATE_MXCSR A06037 6038 cvttsd2si T0, [A 3]6039 mov qword [A 2], T06040 6041 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06013 SSE_LD_MXCSR A0_32 6014 6015 cvttsd2si T0, [A2] 6016 mov qword [A1], T0 6017 6018 SSE_ST_MXCSR R0_32, A0_32 6042 6019 IEMIMPL_SSE_EPILOGUE 6043 EPILOGUE_ 4_ARGS6020 EPILOGUE_3_ARGS 6044 6021 ENDPROC iemAImpl_cvttsd2si_i64_r64 6045 6022 … … 6048 6025 ; cvtsd2si instruction - 32-bit variant. 6049 6026 ; 6050 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6051 ; @param A 1 Where to return the MXCSR value.6052 ; @param A 2Pointer to the result operand (output).6053 ; @param A 3Pointer to the second operand (input).6027 ; @return R0_32 The new MXCSR value of the guest. 6028 ; @param A0_32 The guest's MXCSR register value to use. 6029 ; @param A1 Pointer to the result operand (output). 6030 ; @param A2 Pointer to the second operand (input). 6054 6031 ; 6055 6032 BEGINPROC_FASTCALL iemAImpl_cvtsd2si_i32_r64, 16 6056 PROLOGUE_ 4_ARGS6033 PROLOGUE_3_ARGS 6057 6034 IEMIMPL_SSE_PROLOGUE 6058 SSE_LD_ FXSTATE_MXCSR A06059 6060 cvtsd2si T0_32, [A 3]6061 mov dword [A 2], T0_326062 6063 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06035 SSE_LD_MXCSR A0_32 6036 6037 cvtsd2si T0_32, [A2] 6038 mov dword [A1], T0_32 6039 6040 SSE_ST_MXCSR R0_32, A0_32 6064 6041 IEMIMPL_SSE_EPILOGUE 6065 EPILOGUE_ 4_ARGS6042 EPILOGUE_3_ARGS 6066 6043 ENDPROC iemAImpl_cvtsd2si_i32_r64 6067 6044 … … 6069 6046 ; cvtsd2si instruction - 64-bit variant. 6070 6047 ; 6071 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6072 ; @param A 1 Where to return the MXCSR value.6073 ; @param A 2Pointer to the result operand (output).6074 ; @param A 3Pointer to the second operand (input).6048 ; @return R0_32 The new MXCSR value of the guest. 6049 ; @param A0_32 The guest's MXCSR register value to use. 6050 ; @param A1 Pointer to the result operand (output). 6051 ; @param A2 Pointer to the second operand (input). 6075 6052 ; 6076 6053 BEGINPROC_FASTCALL iemAImpl_cvtsd2si_i64_r64, 16 6077 PROLOGUE_ 4_ARGS6054 PROLOGUE_3_ARGS 6078 6055 IEMIMPL_SSE_PROLOGUE 6079 SSE_LD_ FXSTATE_MXCSR A06080 6081 cvtsd2si T0, [A 3]6082 mov qword [A 2], T06083 6084 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06056 SSE_LD_MXCSR A0_32 6057 6058 cvtsd2si T0, [A2] 6059 mov qword [A1], T0 6060 6061 SSE_ST_MXCSR R0_32, A0_32 6085 6062 IEMIMPL_SSE_EPILOGUE 6086 EPILOGUE_ 4_ARGS6063 EPILOGUE_3_ARGS 6087 6064 ENDPROC iemAImpl_cvtsd2si_i64_r64 6088 6065 … … 6091 6068 ; cvttss2si instruction - 32-bit variant. 6092 6069 ; 6093 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6094 ; @param A 1 Where to return the MXCSR value.6095 ; @param A 2Pointer to the result operand (output).6096 ; @param A 3Pointer to the second operand (input).6070 ; @return R0_32 The new MXCSR value of the guest. 6071 ; @param A0_32 The guest's MXCSR register value to use. 6072 ; @param A1 Pointer to the result operand (output). 6073 ; @param A2 Pointer to the second operand (input). 6097 6074 ; 6098 6075 BEGINPROC_FASTCALL iemAImpl_cvttss2si_i32_r32, 16 6099 PROLOGUE_ 4_ARGS6076 PROLOGUE_3_ARGS 6100 6077 IEMIMPL_SSE_PROLOGUE 6101 SSE_LD_ FXSTATE_MXCSR A06102 6103 cvttss2si T0_32, [A 3]6104 mov dword [A 2], T0_326105 6106 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06078 SSE_LD_MXCSR A0_32 6079 6080 cvttss2si T0_32, [A2] 6081 mov dword [A1], T0_32 6082 6083 SSE_ST_MXCSR R0_32, A0_32 6107 6084 IEMIMPL_SSE_EPILOGUE 6108 EPILOGUE_ 4_ARGS6085 EPILOGUE_3_ARGS 6109 6086 ENDPROC iemAImpl_cvttss2si_i32_r32 6110 6087 … … 6112 6089 ; cvttss2si instruction - 64-bit variant. 6113 6090 ; 6114 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6115 ; @param A 1 Where to return the MXCSR value.6116 ; @param A 2Pointer to the result operand (output).6117 ; @param A 3Pointer to the second operand (input).6091 ; @return R0_32 The new MXCSR value of the guest. 6092 ; @param A0_32 The guest's MXCSR register value to use. 6093 ; @param A1 Pointer to the result operand (output). 6094 ; @param A2 Pointer to the second operand (input). 6118 6095 ; 6119 6096 BEGINPROC_FASTCALL iemAImpl_cvttss2si_i64_r32, 16 6120 PROLOGUE_ 4_ARGS6097 PROLOGUE_3_ARGS 6121 6098 IEMIMPL_SSE_PROLOGUE 6122 SSE_LD_ FXSTATE_MXCSR A06123 6124 cvttss2si T0, [A 3]6125 mov qword [A 2], T06126 6127 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06099 SSE_LD_MXCSR A0_32 6100 6101 cvttss2si T0, [A2] 6102 mov qword [A1], T0 6103 6104 SSE_ST_MXCSR R0_32, A0_32 6128 6105 IEMIMPL_SSE_EPILOGUE 6129 EPILOGUE_ 4_ARGS6106 EPILOGUE_3_ARGS 6130 6107 ENDPROC iemAImpl_cvttss2si_i64_r32 6131 6108 … … 6134 6111 ; cvtss2si instruction - 32-bit variant. 6135 6112 ; 6136 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6137 ; @param A 1 Where to return the MXCSR value.6138 ; @param A 2Pointer to the result operand (output).6139 ; @param A 3Pointer to the second operand (input).6113 ; @return R0_32 The new MXCSR value of the guest. 6114 ; @param A0_32 The guest's MXCSR register value to use. 6115 ; @param A1 Pointer to the result operand (output). 6116 ; @param A2 Pointer to the second operand (input). 6140 6117 ; 6141 6118 BEGINPROC_FASTCALL iemAImpl_cvtss2si_i32_r32, 16 6142 PROLOGUE_ 4_ARGS6119 PROLOGUE_3_ARGS 6143 6120 IEMIMPL_SSE_PROLOGUE 6144 SSE_LD_ FXSTATE_MXCSR A06145 6146 cvtss2si T0_32, [A 3]6147 mov dword [A 2], T0_326148 6149 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06121 SSE_LD_MXCSR A0_32 6122 6123 cvtss2si T0_32, [A2] 6124 mov dword [A1], T0_32 6125 6126 SSE_ST_MXCSR R0_32, A0_32 6150 6127 IEMIMPL_SSE_EPILOGUE 6151 EPILOGUE_ 4_ARGS6128 EPILOGUE_3_ARGS 6152 6129 ENDPROC iemAImpl_cvtss2si_i32_r32 6153 6130 … … 6155 6132 ; cvtss2si instruction - 64-bit variant. 6156 6133 ; 6157 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6158 ; @param A 1 Where to return the MXCSR value.6159 ; @param A 2Pointer to the result operand (output).6160 ; @param A 3Pointer to the second operand (input).6134 ; @return R0_32 The new MXCSR value of the guest. 6135 ; @param A0_32 The guest's MXCSR register value to use. 6136 ; @param A1 Pointer to the result operand (output). 6137 ; @param A2 Pointer to the second operand (input). 6161 6138 ; 6162 6139 BEGINPROC_FASTCALL iemAImpl_cvtss2si_i64_r32, 16 6163 PROLOGUE_ 4_ARGS6140 PROLOGUE_3_ARGS 6164 6141 IEMIMPL_SSE_PROLOGUE 6165 SSE_LD_ FXSTATE_MXCSR A06166 6167 cvtss2si T0, [A 3]6168 mov qword [A 2], T06169 6170 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06142 SSE_LD_MXCSR A0_32 6143 6144 cvtss2si T0, [A2] 6145 mov qword [A1], T0 6146 6147 SSE_ST_MXCSR R0_32, A0_32 6171 6148 IEMIMPL_SSE_EPILOGUE 6172 EPILOGUE_ 4_ARGS6149 EPILOGUE_3_ARGS 6173 6150 ENDPROC iemAImpl_cvtss2si_i64_r32 6174 6151 … … 6177 6154 ; cvtsi2ss instruction - 32-bit variant. 6178 6155 ; 6179 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6180 ; @param A 1 Where to return the MXCSR value.6181 ; @param A 2Pointer to the result operand (output).6182 ; @param A 3Pointer to the second operand (input).6156 ; @return R0_32 The new MXCSR value of the guest. 6157 ; @param A0_32 The guest's MXCSR register value to use. 6158 ; @param A1 Pointer to the result operand (output). 6159 ; @param A2 Pointer to the second operand (input). 6183 6160 ; 6184 6161 BEGINPROC_FASTCALL iemAImpl_cvtsi2ss_r32_i32, 16 6185 PROLOGUE_ 4_ARGS6162 PROLOGUE_3_ARGS 6186 6163 IEMIMPL_SSE_PROLOGUE 6187 SSE_LD_ FXSTATE_MXCSR A06188 6189 cvtsi2ss xmm0, dword [A 3]6190 movd dword [A 2], xmm06191 6192 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06164 SSE_LD_MXCSR A0_32 6165 6166 cvtsi2ss xmm0, dword [A2] 6167 movd dword [A1], xmm0 6168 6169 SSE_ST_MXCSR R0_32, A0_32 6193 6170 IEMIMPL_SSE_EPILOGUE 6194 EPILOGUE_ 4_ARGS6171 EPILOGUE_3_ARGS 6195 6172 ENDPROC iemAImpl_cvtsi2ss_r32_i32 6196 6173 … … 6198 6175 ; cvtsi2ss instruction - 64-bit variant. 6199 6176 ; 6200 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6201 ; @param A 1 Where to return the MXCSR value.6202 ; @param A 2Pointer to the result operand (output).6203 ; @param A 3Pointer to the second operand (input).6177 ; @return R0_32 The new MXCSR value of the guest. 6178 ; @param A0_32 The guest's MXCSR register value to use. 6179 ; @param A1 Pointer to the result operand (output). 6180 ; @param A2 Pointer to the second operand (input). 6204 6181 ; 6205 6182 BEGINPROC_FASTCALL iemAImpl_cvtsi2ss_r32_i64, 16 6206 PROLOGUE_ 4_ARGS6183 PROLOGUE_3_ARGS 6207 6184 IEMIMPL_SSE_PROLOGUE 6208 SSE_LD_ FXSTATE_MXCSR A06209 6210 cvtsi2ss xmm0, qword [A 3]6211 movd dword [A 2], xmm06212 6213 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06185 SSE_LD_MXCSR A0_32 6186 6187 cvtsi2ss xmm0, qword [A2] 6188 movd dword [A1], xmm0 6189 6190 SSE_ST_MXCSR R0_32, A0_32 6214 6191 IEMIMPL_SSE_EPILOGUE 6215 EPILOGUE_ 4_ARGS6192 EPILOGUE_3_ARGS 6216 6193 ENDPROC iemAImpl_cvtsi2ss_r32_i64 6217 6194 … … 6220 6197 ; cvtsi2sd instruction - 32-bit variant. 6221 6198 ; 6222 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6223 ; @param A 1 Where to return the MXCSR value.6224 ; @param A 2Pointer to the result operand (output).6225 ; @param A 3Pointer to the second operand (input).6199 ; @return R0_32 The new MXCSR value of the guest. 6200 ; @param A0_32 The guest's MXCSR register value to use. 6201 ; @param A1 Pointer to the result operand (output). 6202 ; @param A2 Pointer to the second operand (input). 6226 6203 ; 6227 6204 BEGINPROC_FASTCALL iemAImpl_cvtsi2sd_r64_i32, 16 6228 PROLOGUE_ 4_ARGS6205 PROLOGUE_3_ARGS 6229 6206 IEMIMPL_SSE_PROLOGUE 6230 SSE_LD_ FXSTATE_MXCSR A06231 6232 cvtsi2sd xmm0, dword [A 3]6233 movq [A 2], xmm06234 6235 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06207 SSE_LD_MXCSR A0_32 6208 6209 cvtsi2sd xmm0, dword [A2] 6210 movq [A1], xmm0 6211 6212 SSE_ST_MXCSR R0_32, A0_32 6236 6213 IEMIMPL_SSE_EPILOGUE 6237 EPILOGUE_ 4_ARGS6214 EPILOGUE_3_ARGS 6238 6215 ENDPROC iemAImpl_cvtsi2sd_r64_i32 6239 6216 … … 6241 6218 ; cvtsi2sd instruction - 64-bit variant. 6242 6219 ; 6243 ; @ param A0 FPU context (FXSTATE or XSAVEAREA).6244 ; @param A 1 Where to return the MXCSR value.6245 ; @param A 2Pointer to the result operand (output).6246 ; @param A 3Pointer to the second operand (input).6220 ; @return R0_32 The new MXCSR value of the guest. 6221 ; @param A0_32 The guest's MXCSR register value to use. 6222 ; @param A1 Pointer to the result operand (output). 6223 ; @param A2 Pointer to the second operand (input). 6247 6224 ; 6248 6225 BEGINPROC_FASTCALL iemAImpl_cvtsi2sd_r64_i64, 16 6249 PROLOGUE_ 4_ARGS6226 PROLOGUE_3_ARGS 6250 6227 IEMIMPL_SSE_PROLOGUE 6251 SSE_LD_ FXSTATE_MXCSR A06252 6253 cvtsi2sd xmm0, qword [A 3]6254 movq [A 2], xmm06255 6256 SSE_ST_ FXSTATE_MXCSR_ONLY A1, A06228 SSE_LD_MXCSR A0_32 6229 6230 cvtsi2sd xmm0, qword [A2] 6231 movq [A1], xmm0 6232 6233 SSE_ST_MXCSR R0_32, A0_32 6257 6234 IEMIMPL_SSE_EPILOGUE 6258 EPILOGUE_ 4_ARGS6235 EPILOGUE_3_ARGS 6259 6236 ENDPROC iemAImpl_cvtsi2sd_r64_i64 6237 6238 6239 ; 6240 ; UCOMISS (SSE) 6241 ; 6242 ; @return R0_32 The new MXCSR value of the guest. 6243 ; @param A0_32 The guest's MXCSR register value to use (input). 6244 ; @param A1 Pointer to the EFLAGS value (input/output). 6245 ; @param A2 Pointer to the first source operand (aka readonly destination). 6246 ; @param A3 Pointer to the second source operand. 6247 ; 6248 BEGINPROC_FASTCALL iemAImpl_ucomiss_u128, 16 6249 PROLOGUE_4_ARGS 6250 IEMIMPL_SSE_PROLOGUE 6251 SSE_LD_MXCSR A0_32 6252 6253 movdqu xmm0, [A2] 6254 movdqu xmm1, [A3] 6255 ucomiss xmm0, xmm1 6256 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF 6257 6258 SSE_ST_MXCSR R0_32, A0_32 6259 IEMIMPL_SSE_EPILOGUE 6260 EPILOGUE_4_ARGS 6261 ENDPROC iemAImpl_ucomiss_u128 6262 6263 BEGINPROC_FASTCALL iemAImpl_vucomiss_u128, 16 6264 PROLOGUE_4_ARGS 6265 IEMIMPL_SSE_PROLOGUE 6266 SSE_LD_MXCSR A0_32 6267 6268 movdqu xmm0, [A2] 6269 movdqu xmm1, [A3] 6270 vucomiss xmm0, xmm1 6271 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF 6272 6273 SSE_ST_MXCSR R0_32, A0_32 6274 IEMIMPL_SSE_EPILOGUE 6275 EPILOGUE_3_ARGS 6276 ENDPROC iemAImpl_vucomiss_u128 6277 6278 6279 ; 6280 ; UCOMISD (SSE) 6281 ; 6282 ; @return R0_32 The new MXCSR value of the guest. 6283 ; @param A0_32 The guest's MXCSR register value to use (input). 6284 ; @param A1 Pointer to the EFLAGS value (input/output). 6285 ; @param A2 Pointer to the first source operand (aka readonly destination). 6286 ; @param A3 Pointer to the second source operand. 6287 ; 6288 BEGINPROC_FASTCALL iemAImpl_ucomisd_u128, 16 6289 PROLOGUE_4_ARGS 6290 IEMIMPL_SSE_PROLOGUE 6291 SSE_LD_MXCSR A0_32 6292 6293 movdqu xmm0, [A2] 6294 movdqu xmm1, [A3] 6295 ucomisd xmm0, xmm1 6296 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF 6297 6298 SSE_ST_MXCSR R0_32, A0_32 6299 IEMIMPL_SSE_EPILOGUE 6300 EPILOGUE_4_ARGS 6301 ENDPROC iemAImpl_ucomisd_u128 6302 6303 BEGINPROC_FASTCALL iemAImpl_vucomisd_u128, 16 6304 PROLOGUE_4_ARGS 6305 IEMIMPL_SSE_PROLOGUE 6306 SSE_LD_MXCSR A0_32 6307 6308 movdqu xmm0, [A2] 6309 movdqu xmm1, [A3] 6310 vucomisd xmm0, xmm1 6311 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF 6312 6313 SSE_ST_MXCSR R0_32, A0_32 6314 IEMIMPL_SSE_EPILOGUE 6315 EPILOGUE_4_ARGS 6316 ENDPROC iemAImpl_vucomisd_u128 6317 6318 ; 6319 ; COMISS (SSE) 6320 ; 6321 ; @return R0_32 The new MXCSR value of the guest. 6322 ; @param A0_32 The guest's MXCSR register value to use (input). 6323 ; @param A1 Pointer to the EFLAGS value (input/output). 6324 ; @param A2 Pointer to the first source operand (aka readonly destination). 6325 ; @param A3 Pointer to the second source operand. 6326 ; 6327 BEGINPROC_FASTCALL iemAImpl_comiss_u128, 16 6328 PROLOGUE_4_ARGS 6329 IEMIMPL_SSE_PROLOGUE 6330 SSE_LD_MXCSR A0_32 6331 6332 movdqu xmm0, [A2] 6333 movdqu xmm1, [A3] 6334 comiss xmm0, xmm1 6335 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF 6336 6337 SSE_ST_MXCSR R0_32, A0_32 6338 IEMIMPL_SSE_EPILOGUE 6339 EPILOGUE_4_ARGS 6340 ENDPROC iemAImpl_comiss_u128 6341 6342 BEGINPROC_FASTCALL iemAImpl_vcomiss_u128, 16 6343 PROLOGUE_4_ARGS 6344 IEMIMPL_SSE_PROLOGUE 6345 SSE_LD_MXCSR A0_32 6346 6347 movdqu xmm0, [A2] 6348 movdqu xmm1, [A3] 6349 vcomiss xmm0, xmm1 6350 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF 6351 6352 SSE_ST_MXCSR R0_32, A0_32 6353 IEMIMPL_SSE_EPILOGUE 6354 EPILOGUE_4_ARGS 6355 ENDPROC iemAImpl_vcomiss_u128 6356 6357 6358 ; 6359 ; COMISD (SSE) 6360 ; 6361 ; @return R0_32 The new MXCSR value of the guest. 6362 ; @param A0_32 The guest's MXCSR register value to use (input). 6363 ; @param A1 Pointer to the EFLAGS value (input/output). 6364 ; @param A2 Pointer to the first source operand (aka readonly destination). 6365 ; @param A3 Pointer to the second source operand. 6366 ; 6367 BEGINPROC_FASTCALL iemAImpl_comisd_u128, 16 6368 PROLOGUE_4_ARGS 6369 IEMIMPL_SSE_PROLOGUE 6370 SSE_LD_MXCSR A0_32 6371 6372 movdqu xmm0, [A2] 6373 movdqu xmm1, [A3] 6374 comisd xmm0, xmm1 6375 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF 6376 6377 SSE_ST_MXCSR R0_32, A0_32 6378 IEMIMPL_SSE_EPILOGUE 6379 EPILOGUE_4_ARGS 6380 ENDPROC iemAImpl_comisd_u128 6381 6382 BEGINPROC_FASTCALL iemAImpl_vcomisd_u128, 16 6383 PROLOGUE_4_ARGS 6384 IEMIMPL_SSE_PROLOGUE 6385 SSE_LD_MXCSR A0_32 6386 6387 movdqu xmm0, [A2] 6388 movdqu xmm1, [A3] 6389 vcomisd xmm0, xmm1 6390 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF 6391 6392 SSE_ST_MXCSR R0_32, A0_32 6393 IEMIMPL_SSE_EPILOGUE 6394 EPILOGUE_4_ARGS 6395 ENDPROC iemAImpl_vcomisd_u128 6260 6396 6261 6397 … … 6303 6439 add xSP, 4 6304 6440 %endmacro 6305 6306 6307 ;6308 ; UCOMISS (SSE)6309 ;6310 ; @param A0 Pointer to the MXCSR value (input/output).6311 ; @param A1 Pointer to the EFLAGS value (input/output).6312 ; @param A2 Pointer to the first source operand (aka readonly destination).6313 ; @param A3 Pointer to the second source operand.6314 ;6315 BEGINPROC_FASTCALL iemAImpl_ucomiss_u128, 166316 PROLOGUE_4_ARGS6317 IEMIMPL_SSE_PROLOGUE6318 SSE_LD_FXSTATE_MXCSR_ONLY A06319 6320 movdqu xmm0, [A2]6321 movdqu xmm1, [A3]6322 ucomiss xmm0, xmm16323 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF6324 6325 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A06326 IEMIMPL_SSE_EPILOGUE6327 EPILOGUE_4_ARGS6328 ENDPROC iemAImpl_ucomiss_u1286329 6330 BEGINPROC_FASTCALL iemAImpl_vucomiss_u128, 166331 PROLOGUE_4_ARGS6332 IEMIMPL_SSE_PROLOGUE6333 SSE_LD_FXSTATE_MXCSR_ONLY A06334 6335 movdqu xmm0, [A2]6336 movdqu xmm1, [A3]6337 vucomiss xmm0, xmm16338 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF6339 6340 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A06341 IEMIMPL_SSE_EPILOGUE6342 EPILOGUE_4_ARGS6343 ENDPROC iemAImpl_vucomiss_u1286344 6345 6346 ;6347 ; UCOMISD (SSE)6348 ;6349 ; @param A0 Pointer to the MXCSR value (input/output).6350 ; @param A1 Pointer to the EFLAGS value (input/output).6351 ; @param A2 Pointer to the first source operand (aka readonly destination).6352 ; @param A3 Pointer to the second source operand.6353 ;6354 BEGINPROC_FASTCALL iemAImpl_ucomisd_u128, 166355 PROLOGUE_4_ARGS6356 IEMIMPL_SSE_PROLOGUE6357 SSE_LD_FXSTATE_MXCSR_ONLY A06358 6359 movdqu xmm0, [A2]6360 movdqu xmm1, [A3]6361 ucomisd xmm0, xmm16362 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF6363 6364 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A06365 IEMIMPL_SSE_EPILOGUE6366 EPILOGUE_4_ARGS6367 ENDPROC iemAImpl_ucomisd_u1286368 6369 BEGINPROC_FASTCALL iemAImpl_vucomisd_u128, 166370 PROLOGUE_4_ARGS6371 IEMIMPL_SSE_PROLOGUE6372 SSE_LD_FXSTATE_MXCSR_ONLY A06373 6374 movdqu xmm0, [A2]6375 movdqu xmm1, [A3]6376 vucomisd xmm0, xmm16377 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF6378 6379 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A06380 IEMIMPL_SSE_EPILOGUE6381 EPILOGUE_4_ARGS6382 ENDPROC iemAImpl_vucomisd_u1286383 6384 ;6385 ; COMISS (SSE)6386 ;6387 ; @param A0 Pointer to the MXCSR value (input/output).6388 ; @param A1 Pointer to the EFLAGS value (input/output).6389 ; @param A2 Pointer to the first source operand (aka readonly destination).6390 ; @param A3 Pointer to the second source operand.6391 ;6392 BEGINPROC_FASTCALL iemAImpl_comiss_u128, 166393 PROLOGUE_4_ARGS6394 IEMIMPL_SSE_PROLOGUE6395 SSE_LD_FXSTATE_MXCSR_ONLY A06396 6397 movdqu xmm0, [A2]6398 movdqu xmm1, [A3]6399 comiss xmm0, xmm16400 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF6401 6402 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A06403 IEMIMPL_SSE_EPILOGUE6404 EPILOGUE_4_ARGS6405 ENDPROC iemAImpl_comiss_u1286406 6407 BEGINPROC_FASTCALL iemAImpl_vcomiss_u128, 166408 PROLOGUE_4_ARGS6409 IEMIMPL_SSE_PROLOGUE6410 SSE_LD_FXSTATE_MXCSR_ONLY A06411 6412 movdqu xmm0, [A2]6413 movdqu xmm1, [A3]6414 vcomiss xmm0, xmm16415 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF6416 6417 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A06418 IEMIMPL_SSE_EPILOGUE6419 EPILOGUE_4_ARGS6420 ENDPROC iemAImpl_vcomiss_u1286421 6422 6423 ;6424 ; COMISD (SSE)6425 ;6426 ; @param A0 Pointer to the MXCSR value (input/output).6427 ; @param A1 Pointer to the EFLAGS value (input/output).6428 ; @param A2 Pointer to the first source operand (aka readonly destination).6429 ; @param A3 Pointer to the second source operand.6430 ;6431 BEGINPROC_FASTCALL iemAImpl_comisd_u128, 166432 PROLOGUE_4_ARGS6433 IEMIMPL_SSE_PROLOGUE6434 SSE_LD_FXSTATE_MXCSR_ONLY A06435 6436 movdqu xmm0, [A2]6437 movdqu xmm1, [A3]6438 comisd xmm0, xmm16439 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF6440 6441 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A06442 IEMIMPL_SSE_EPILOGUE6443 EPILOGUE_4_ARGS6444 ENDPROC iemAImpl_comisd_u1286445 6446 BEGINPROC_FASTCALL iemAImpl_vcomisd_u128, 166447 PROLOGUE_4_ARGS6448 IEMIMPL_SSE_PROLOGUE6449 SSE_LD_FXSTATE_MXCSR_ONLY A06450 6451 movdqu xmm0, [A2]6452 movdqu xmm1, [A3]6453 vcomisd xmm0, xmm16454 IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF6455 6456 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A06457 IEMIMPL_SSE_EPILOGUE6458 EPILOGUE_4_ARGS6459 ENDPROC iemAImpl_vcomisd_u1286460 6441 6461 6442 … … 6846 6827 IEMIMPL_ADX_32 adox, X86_EFL_OF 6847 6828 IEMIMPL_ADX_64 adox, X86_EFL_OF 6829 -
trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
r104103 r104129 5 5 6 6 /* 7 * Copyright (C) 2011-202 3Oracle and/or its affiliates.7 * Copyright (C) 2011-2024 Oracle and/or its affiliates. 8 8 * 9 9 * This file is part of VirtualBox base platform packages, as … … 15828 15828 15829 15829 15830 IEM_DECL_IMPL_DEF( void, iemAImpl_addps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))15831 { 15832 pResult->MXCSR = iemAImpl_addps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);15833 pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);15834 pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);15835 pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);15830 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 15831 { 15832 return iemAImpl_addps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0]) 15833 | iemAImpl_addps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1]) 15834 | iemAImpl_addps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2]) 15835 | iemAImpl_addps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]); 15836 15836 } 15837 15837 #endif … … 15842 15842 */ 15843 15843 #ifdef IEM_WITHOUT_ASSEMBLY 15844 IEM_DECL_IMPL_DEF( void, iemAImpl_addss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))15845 { 15846 pResult-> MXCSR = iemAImpl_addps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);15847 pResult-> uResult.ar32[1] = puSrc1->ar32[1];15848 pResult-> uResult.ar32[2] = puSrc1->ar32[2];15849 pResult->uResult.ar32[3] = puSrc1->ar32[3];15844 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)) 15845 { 15846 pResult->ar32[1] = puSrc1->ar32[1]; 15847 pResult->ar32[2] = puSrc1->ar32[2]; 15848 pResult->ar32[3] = puSrc1->ar32[3]; 15849 return iemAImpl_addps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2); 15850 15850 } 15851 15851 #endif … … 15870 15870 15871 15871 15872 IEM_DECL_IMPL_DEF( void, iemAImpl_addpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))15873 { 15874 pResult->MXCSR = iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);15875 pResult->MXCSR |= iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);15872 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 15873 { 15874 return iemAImpl_addpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0]) 15875 | iemAImpl_addpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]); 15876 15876 } 15877 15877 #endif … … 15882 15882 */ 15883 15883 #ifdef IEM_WITHOUT_ASSEMBLY 15884 IEM_DECL_IMPL_DEF( void, iemAImpl_addsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))15885 { 15886 pResult-> MXCSR = iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);15887 pResult->uResult.ar64[1] = puSrc1->ar64[1];15884 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2)) 15885 { 15886 pResult->ar64[1] = puSrc1->ar64[1]; 15887 return iemAImpl_addpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2); 15888 15888 } 15889 15889 #endif … … 15908 15908 15909 15909 15910 IEM_DECL_IMPL_DEF( void, iemAImpl_mulps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))15911 { 15912 pResult->MXCSR = iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);15913 pResult->MXCSR |= iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);15914 pResult->MXCSR |= iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);15915 pResult->MXCSR |= iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);15910 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_mulps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 15911 { 15912 return iemAImpl_mulps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0]) 15913 | iemAImpl_mulps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1]) 15914 | iemAImpl_mulps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2]) 15915 | iemAImpl_mulps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]); 15916 15916 } 15917 15917 #endif … … 15922 15922 */ 15923 15923 #ifdef IEM_WITHOUT_ASSEMBLY 15924 IEM_DECL_IMPL_DEF( void, iemAImpl_mulss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))15925 { 15926 pResult-> MXCSR = iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);15927 pResult-> uResult.ar32[1] = puSrc1->ar32[1];15928 pResult-> uResult.ar32[2] = puSrc1->ar32[2];15929 pResult->uResult.ar32[3] = puSrc1->ar32[3];15924 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_mulss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)) 15925 { 15926 pResult->ar32[1] = puSrc1->ar32[1]; 15927 pResult->ar32[2] = puSrc1->ar32[2]; 15928 pResult->ar32[3] = puSrc1->ar32[3]; 15929 return iemAImpl_mulps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2); 15930 15930 } 15931 15931 #endif … … 15950 15950 15951 15951 15952 IEM_DECL_IMPL_DEF( void, iemAImpl_mulpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))15953 { 15954 pResult->MXCSR = iemAImpl_mulpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);15955 pResult->MXCSR |= iemAImpl_mulpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);15952 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_mulpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 15953 { 15954 return iemAImpl_mulpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0]) 15955 | iemAImpl_mulpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]); 15956 15956 } 15957 15957 #endif … … 15962 15962 */ 15963 15963 #ifdef IEM_WITHOUT_ASSEMBLY 15964 IEM_DECL_IMPL_DEF( void, iemAImpl_mulsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))15965 { 15966 pResult-> MXCSR = iemAImpl_mulpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);15967 pResult->uResult.ar64[1] = puSrc1->ar64[1];15964 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_mulsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2)) 15965 { 15966 pResult->ar64[1] = puSrc1->ar64[1]; 15967 return iemAImpl_mulpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2); 15968 15968 } 15969 15969 #endif … … 15988 15988 15989 15989 15990 IEM_DECL_IMPL_DEF( void, iemAImpl_subps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))15991 { 15992 pResult->MXCSR = iemAImpl_subps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);15993 pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);15994 pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);15995 pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);15990 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_subps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 15991 { 15992 return iemAImpl_subps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0]) 15993 | iemAImpl_subps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1]) 15994 | iemAImpl_subps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2]) 15995 | iemAImpl_subps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]); 15996 15996 } 15997 15997 #endif … … 16002 16002 */ 16003 16003 #ifdef IEM_WITHOUT_ASSEMBLY 16004 IEM_DECL_IMPL_DEF( void, iemAImpl_subss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))16005 { 16006 pResult-> MXCSR = iemAImpl_subps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);16007 pResult-> uResult.ar32[1] = puSrc1->ar32[1];16008 pResult-> uResult.ar32[2] = puSrc1->ar32[2];16009 pResult->uResult.ar32[3] = puSrc1->ar32[3];16004 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_subss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)) 16005 { 16006 pResult->ar32[1] = puSrc1->ar32[1]; 16007 pResult->ar32[2] = puSrc1->ar32[2]; 16008 pResult->ar32[3] = puSrc1->ar32[3]; 16009 return iemAImpl_subps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2); 16010 16010 } 16011 16011 #endif … … 16030 16030 16031 16031 16032 IEM_DECL_IMPL_DEF( void, iemAImpl_subpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16033 { 16034 pResult->MXCSR = iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);16035 pResult->MXCSR |= iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);16032 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_subpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16033 { 16034 return iemAImpl_subpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0]) 16035 | iemAImpl_subpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]); 16036 16036 } 16037 16037 #endif … … 16042 16042 */ 16043 16043 #ifdef IEM_WITHOUT_ASSEMBLY 16044 IEM_DECL_IMPL_DEF( void, iemAImpl_subsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))16045 { 16046 pResult-> MXCSR = iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);16047 pResult->uResult.ar64[1] = puSrc1->ar64[1];16044 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_subsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2)) 16045 { 16046 pResult->ar64[1] = puSrc1->ar64[1]; 16047 return iemAImpl_subpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2); 16048 16048 } 16049 16049 #endif … … 16082 16082 16083 16083 16084 IEM_DECL_IMPL_DEF( void, iemAImpl_minps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16085 { 16086 pResult->MXCSR = iemAImpl_minps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);16087 pResult->MXCSR |= iemAImpl_minps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);16088 pResult->MXCSR |= iemAImpl_minps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);16089 pResult->MXCSR |= iemAImpl_minps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);16084 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_minps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16085 { 16086 return iemAImpl_minps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0]) 16087 | iemAImpl_minps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1]) 16088 | iemAImpl_minps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2]) 16089 | iemAImpl_minps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]); 16090 16090 } 16091 16091 #endif … … 16096 16096 */ 16097 16097 #ifdef IEM_WITHOUT_ASSEMBLY 16098 IEM_DECL_IMPL_DEF( void, iemAImpl_minss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))16099 { 16100 pResult-> MXCSR = iemAImpl_minps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);16101 pResult-> uResult.ar32[1] = puSrc1->ar32[1];16102 pResult-> uResult.ar32[2] = puSrc1->ar32[2];16103 pResult->uResult.ar32[3] = puSrc1->ar32[3];16098 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_minss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)) 16099 { 16100 pResult->ar32[1] = puSrc1->ar32[1]; 16101 pResult->ar32[2] = puSrc1->ar32[2]; 16102 pResult->ar32[3] = puSrc1->ar32[3]; 16103 return iemAImpl_minps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2); 16104 16104 } 16105 16105 #endif … … 16138 16138 16139 16139 16140 IEM_DECL_IMPL_DEF( void, iemAImpl_minpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16141 { 16142 pResult->MXCSR = iemAImpl_minpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);16143 pResult->MXCSR |= iemAImpl_minpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);16140 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_minpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16141 { 16142 return iemAImpl_minpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0]) 16143 | iemAImpl_minpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]); 16144 16144 } 16145 16145 #endif … … 16150 16150 */ 16151 16151 #ifdef IEM_WITHOUT_ASSEMBLY 16152 IEM_DECL_IMPL_DEF( void, iemAImpl_minsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))16153 { 16154 pResult-> MXCSR = iemAImpl_minpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);16155 pResult->uResult.ar64[1] = puSrc1->ar64[1];16152 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_minsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2)) 16153 { 16154 pResult->ar64[1] = puSrc1->ar64[1]; 16155 return iemAImpl_minpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2); 16156 16156 } 16157 16157 #endif … … 16196 16196 16197 16197 16198 IEM_DECL_IMPL_DEF( void, iemAImpl_divps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16199 { 16200 pResult->MXCSR = iemAImpl_divps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);16201 pResult->MXCSR |= iemAImpl_divps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);16202 pResult->MXCSR |= iemAImpl_divps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);16203 pResult->MXCSR |= iemAImpl_divps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);16198 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_divps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16199 { 16200 return iemAImpl_divps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0]) 16201 | iemAImpl_divps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1]) 16202 | iemAImpl_divps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2]) 16203 | iemAImpl_divps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]); 16204 16204 } 16205 16205 #endif … … 16210 16210 */ 16211 16211 #ifdef IEM_WITHOUT_ASSEMBLY 16212 IEM_DECL_IMPL_DEF( void, iemAImpl_divss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))16213 { 16214 pResult-> MXCSR = iemAImpl_divps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);16215 pResult-> uResult.ar32[1] = puSrc1->ar32[1];16216 pResult-> uResult.ar32[2] = puSrc1->ar32[2];16217 pResult->uResult.ar32[3] = puSrc1->ar32[3];16212 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_divss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)) 16213 { 16214 pResult->ar32[1] = puSrc1->ar32[1]; 16215 pResult->ar32[2] = puSrc1->ar32[2]; 16216 pResult->ar32[3] = puSrc1->ar32[3]; 16217 return iemAImpl_divps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2); 16218 16218 } 16219 16219 #endif … … 16258 16258 16259 16259 16260 IEM_DECL_IMPL_DEF( void, iemAImpl_divpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16261 { 16262 pResult->MXCSR = iemAImpl_divpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);16263 pResult->MXCSR |= iemAImpl_divpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);16260 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_divpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16261 { 16262 return iemAImpl_divpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0]) 16263 | iemAImpl_divpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]); 16264 16264 } 16265 16265 #endif … … 16270 16270 */ 16271 16271 #ifdef IEM_WITHOUT_ASSEMBLY 16272 IEM_DECL_IMPL_DEF( void, iemAImpl_divsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))16273 { 16274 pResult-> MXCSR = iemAImpl_divpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);16275 pResult->uResult.ar64[1] = puSrc1->ar64[1];16272 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_divsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2)) 16273 { 16274 pResult->ar64[1] = puSrc1->ar64[1]; 16275 return iemAImpl_divpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2); 16276 16276 } 16277 16277 #endif … … 16310 16310 16311 16311 16312 IEM_DECL_IMPL_DEF( void, iemAImpl_maxps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16313 { 16314 pResult->MXCSR = iemAImpl_maxps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);16315 pResult->MXCSR |= iemAImpl_maxps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);16316 pResult->MXCSR |= iemAImpl_maxps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);16317 pResult->MXCSR |= iemAImpl_maxps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);16312 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_maxps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16313 { 16314 return iemAImpl_maxps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0]) 16315 | iemAImpl_maxps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1]) 16316 | iemAImpl_maxps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2]) 16317 | iemAImpl_maxps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]); 16318 16318 } 16319 16319 #endif … … 16324 16324 */ 16325 16325 #ifdef IEM_WITHOUT_ASSEMBLY 16326 IEM_DECL_IMPL_DEF( void, iemAImpl_maxss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))16327 { 16328 pResult-> MXCSR = iemAImpl_maxps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);16329 pResult-> uResult.ar32[1] = puSrc1->ar32[1];16330 pResult-> uResult.ar32[2] = puSrc1->ar32[2];16331 pResult->uResult.ar32[3] = puSrc1->ar32[3];16326 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_maxss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)) 16327 { 16328 pResult->ar32[1] = puSrc1->ar32[1]; 16329 pResult->ar32[2] = puSrc1->ar32[2]; 16330 pResult->ar32[3] = puSrc1->ar32[3]; 16331 return iemAImpl_maxps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2); 16332 16332 } 16333 16333 #endif … … 16366 16366 16367 16367 16368 IEM_DECL_IMPL_DEF( void, iemAImpl_maxpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16369 { 16370 pResult->MXCSR = iemAImpl_maxpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);16371 pResult->MXCSR |= iemAImpl_maxpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);16368 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_maxpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16369 { 16370 return iemAImpl_maxpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0]) 16371 | iemAImpl_maxpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]); 16372 16372 } 16373 16373 #endif … … 16378 16378 */ 16379 16379 #ifdef IEM_WITHOUT_ASSEMBLY 16380 IEM_DECL_IMPL_DEF( void, iemAImpl_maxsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))16381 { 16382 pResult-> MXCSR = iemAImpl_maxpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);16383 pResult->uResult.ar64[1] = puSrc1->ar64[1];16380 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_maxsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2)) 16381 { 16382 pResult->ar64[1] = puSrc1->ar64[1]; 16383 return iemAImpl_maxpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2); 16384 16384 } 16385 16385 #endif … … 16401 16401 16402 16402 16403 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtss2sd_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))16404 { 16405 pResult-> MXCSR = iemAImpl_cvtss2sd_u128_r32_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, pr32Src2);16406 pResult->uResult.ar64[1] = puSrc1->ar64[1];16403 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtss2sd_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)) 16404 { 16405 pResult->ar64[1] = puSrc1->ar64[1]; 16406 return iemAImpl_cvtss2sd_u128_r32_worker(&pResult->ar64[0], uMxCsrIn, pr32Src2); 16407 16407 } 16408 16408 #endif … … 16424 16424 16425 16425 16426 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtsd2ss_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))16427 { 16428 pResult-> MXCSR = iemAImpl_cvtsd2ss_u128_r64_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, pr64Src2);16429 pResult-> uResult.ar32[1] = puSrc1->ar32[1];16430 pResult-> uResult.ar32[2] = puSrc1->ar32[2];16431 pResult->uResult.ar32[3] = puSrc1->ar32[3];16426 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsd2ss_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2)) 16427 { 16428 pResult->ar32[1] = puSrc1->ar32[1]; 16429 pResult->ar32[2] = puSrc1->ar32[2]; 16430 pResult->ar32[3] = puSrc1->ar32[3]; 16431 return iemAImpl_cvtsd2ss_u128_r64_worker(&pResult->ar32[0], uMxCsrIn, pr64Src2); 16432 16432 } 16433 16433 #endif … … 16438 16438 */ 16439 16439 #ifdef IEM_WITHOUT_ASSEMBLY 16440 IEM_DECL_IMPL_DEF( void, iemAImpl_haddps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16441 { 16442 pResult->MXCSR = iemAImpl_addps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc1->ar32[1]);16443 pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc1->ar32[3]);16444 pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc2->ar32[0], &puSrc2->ar32[1]);16445 pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc2->ar32[2], &puSrc2->ar32[3]);16440 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_haddps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16441 { 16442 return iemAImpl_addps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc1->ar32[1]) 16443 | iemAImpl_addps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[2], &puSrc1->ar32[3]) 16444 | iemAImpl_addps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc2->ar32[0], &puSrc2->ar32[1]) 16445 | iemAImpl_addps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc2->ar32[2], &puSrc2->ar32[3]); 16446 16446 } 16447 16447 #endif … … 16452 16452 */ 16453 16453 #ifdef IEM_WITHOUT_ASSEMBLY 16454 IEM_DECL_IMPL_DEF( void, iemAImpl_haddpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16455 { 16456 pResult->MXCSR = iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc1->ar64[1]);16457 pResult->MXCSR |= iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc2->ar64[0], &puSrc2->ar64[1]);16454 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_haddpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16455 { 16456 return iemAImpl_addpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc1->ar64[1]) 16457 | iemAImpl_addpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc2->ar64[0], &puSrc2->ar64[1]); 16458 16458 } 16459 16459 #endif … … 16464 16464 */ 16465 16465 #ifdef IEM_WITHOUT_ASSEMBLY 16466 IEM_DECL_IMPL_DEF( void, iemAImpl_hsubps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16467 { 16468 pResult->MXCSR = iemAImpl_subps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc1->ar32[1]);16469 pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc1->ar32[3]);16470 pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc2->ar32[0], &puSrc2->ar32[1]);16471 pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc2->ar32[2], &puSrc2->ar32[3]);16466 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_hsubps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16467 { 16468 return iemAImpl_subps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc1->ar32[1]) 16469 | iemAImpl_subps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[2], &puSrc1->ar32[3]) 16470 | iemAImpl_subps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc2->ar32[0], &puSrc2->ar32[1]) 16471 | iemAImpl_subps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc2->ar32[2], &puSrc2->ar32[3]); 16472 16472 } 16473 16473 #endif … … 16478 16478 */ 16479 16479 #ifdef IEM_WITHOUT_ASSEMBLY 16480 IEM_DECL_IMPL_DEF( void, iemAImpl_hsubpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16481 { 16482 pResult->MXCSR = iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc1->ar64[1]);16483 pResult->MXCSR |= iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc2->ar64[0], &puSrc2->ar64[1]);16480 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_hsubpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16481 { 16482 return iemAImpl_subpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc1->ar64[1]) 16483 | iemAImpl_subpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc2->ar64[0], &puSrc2->ar64[1]); 16484 16484 } 16485 16485 #endif … … 16514 16514 16515 16515 16516 IEM_DECL_IMPL_DEF( void, iemAImpl_sqrtps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16516 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sqrtps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16517 16517 { 16518 16518 RT_NOREF(puSrc1); 16519 16519 16520 pResult->MXCSR = iemAImpl_sqrtps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc2->ar32[0]);16521 pResult->MXCSR |= iemAImpl_sqrtps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc2->ar32[1]);16522 pResult->MXCSR |= iemAImpl_sqrtps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc2->ar32[2]);16523 pResult->MXCSR |= iemAImpl_sqrtps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc2->ar32[3]);16520 return iemAImpl_sqrtps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc2->ar32[0]) 16521 | iemAImpl_sqrtps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc2->ar32[1]) 16522 | iemAImpl_sqrtps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc2->ar32[2]) 16523 | iemAImpl_sqrtps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc2->ar32[3]); 16524 16524 } 16525 16525 #endif … … 16530 16530 */ 16531 16531 #ifdef IEM_WITHOUT_ASSEMBLY 16532 IEM_DECL_IMPL_DEF( void, iemAImpl_sqrtss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))16533 { 16534 pResult-> MXCSR = iemAImpl_sqrtps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, pr32Src2);16535 pResult-> uResult.ar32[1] = puSrc1->ar32[1];16536 pResult-> uResult.ar32[2] = puSrc1->ar32[2];16537 pResult->uResult.ar32[3] = puSrc1->ar32[3];16532 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sqrtss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)) 16533 { 16534 pResult->ar32[1] = puSrc1->ar32[1]; 16535 pResult->ar32[2] = puSrc1->ar32[2]; 16536 pResult->ar32[3] = puSrc1->ar32[3]; 16537 return iemAImpl_sqrtps_u128_worker(&pResult->ar32[0], uMxCsrIn, pr32Src2); 16538 16538 } 16539 16539 #endif … … 16568 16568 16569 16569 16570 IEM_DECL_IMPL_DEF( void, iemAImpl_sqrtpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16570 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sqrtpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16571 16571 { 16572 16572 RT_NOREF(puSrc1); 16573 16573 16574 pResult->MXCSR = iemAImpl_sqrtpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc2->ar64[0]);16575 pResult->MXCSR |= iemAImpl_sqrtpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc2->ar64[1]);16574 return iemAImpl_sqrtpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc2->ar64[0]) 16575 | iemAImpl_sqrtpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc2->ar64[1]); 16576 16576 } 16577 16577 #endif … … 16582 16582 */ 16583 16583 #ifdef IEM_WITHOUT_ASSEMBLY 16584 IEM_DECL_IMPL_DEF( void, iemAImpl_sqrtsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))16585 { 16586 pResult-> MXCSR = iemAImpl_sqrtpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, pr64Src2);16587 pResult->uResult.ar64[1] = puSrc1->ar64[1];16584 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sqrtsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2)) 16585 { 16586 pResult->ar64[1] = puSrc1->ar64[1]; 16587 return iemAImpl_sqrtpd_u128_worker(&pResult->ar64[0], uMxCsrIn, pr64Src2); 16588 16588 } 16589 16589 #endif … … 16618 16618 16619 16619 16620 IEM_DECL_IMPL_DEF( void, iemAImpl_rsqrtps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16620 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_rsqrtps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16621 16621 { 16622 16622 RT_NOREF(puSrc1); 16623 16623 16624 pResult->MXCSR = iemAImpl_rsqrt_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc2->ar32[0]);16625 pResult->MXCSR |= iemAImpl_rsqrt_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc2->ar32[1]);16626 pResult->MXCSR |= iemAImpl_rsqrt_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc2->ar32[2]);16627 pResult->MXCSR |= iemAImpl_rsqrt_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc2->ar32[3]);16624 return iemAImpl_rsqrt_worker(&pResult->ar32[0], uMxCsrIn, &puSrc2->ar32[0]) 16625 | iemAImpl_rsqrt_worker(&pResult->ar32[1], uMxCsrIn, &puSrc2->ar32[1]) 16626 | iemAImpl_rsqrt_worker(&pResult->ar32[2], uMxCsrIn, &puSrc2->ar32[2]) 16627 | iemAImpl_rsqrt_worker(&pResult->ar32[3], uMxCsrIn, &puSrc2->ar32[3]); 16628 16628 } 16629 16629 … … 16632 16632 * RSQRTSS 16633 16633 */ 16634 IEM_DECL_IMPL_DEF( void, iemAImpl_rsqrtss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))16635 { 16636 pResult-> MXCSR = iemAImpl_rsqrt_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, pr32Src2);16637 pResult-> uResult.ar32[1] = puSrc1->ar32[1];16638 pResult-> uResult.ar32[2] = puSrc1->ar32[2];16639 pResult->uResult.ar32[3] = puSrc1->ar32[3];16634 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_rsqrtss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)) 16635 { 16636 pResult->ar32[1] = puSrc1->ar32[1]; 16637 pResult->ar32[2] = puSrc1->ar32[2]; 16638 pResult->ar32[3] = puSrc1->ar32[3]; 16639 return iemAImpl_rsqrt_worker(&pResult->ar32[0], uMxCsrIn, pr32Src2); 16640 16640 } 16641 16641 #endif … … 16665 16665 16666 16666 16667 IEM_DECL_IMPL_DEF( void, iemAImpl_rcpps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16667 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_rcpps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16668 16668 { 16669 16669 RT_NOREF(puSrc1); 16670 16670 16671 pResult->MXCSR = iemAImpl_rcp_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc2->ar32[0]);16672 pResult->MXCSR |= iemAImpl_rcp_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc2->ar32[1]);16673 pResult->MXCSR |= iemAImpl_rcp_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc2->ar32[2]);16674 pResult->MXCSR |= iemAImpl_rcp_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc2->ar32[3]);16671 return iemAImpl_rcp_worker(&pResult->ar32[0], uMxCsrIn, &puSrc2->ar32[0]) 16672 | iemAImpl_rcp_worker(&pResult->ar32[1], uMxCsrIn, &puSrc2->ar32[1]) 16673 | iemAImpl_rcp_worker(&pResult->ar32[2], uMxCsrIn, &puSrc2->ar32[2]) 16674 | iemAImpl_rcp_worker(&pResult->ar32[3], uMxCsrIn, &puSrc2->ar32[3]); 16675 16675 } 16676 16676 … … 16679 16679 * RCPSS 16680 16680 */ 16681 IEM_DECL_IMPL_DEF( void, iemAImpl_rcpss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))16682 { 16683 pResult-> MXCSR = iemAImpl_rcp_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, pr32Src2);16684 pResult-> uResult.ar32[1] = puSrc1->ar32[1];16685 pResult-> uResult.ar32[2] = puSrc1->ar32[2];16686 pResult->uResult.ar32[3] = puSrc1->ar32[3];16681 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_rcpss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)) 16682 { 16683 pResult->ar32[1] = puSrc1->ar32[1]; 16684 pResult->ar32[2] = puSrc1->ar32[2]; 16685 pResult->ar32[3] = puSrc1->ar32[3]; 16686 return iemAImpl_rcp_worker(&pResult->ar32[0], uMxCsrIn, pr32Src2); 16687 16687 } 16688 16688 #endif … … 16693 16693 */ 16694 16694 #ifdef IEM_WITHOUT_ASSEMBLY 16695 IEM_DECL_IMPL_DEF( void, iemAImpl_addsubps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16695 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addsubps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16696 16696 { 16697 16697 RT_NOREF(puSrc1); 16698 16698 16699 pResult->MXCSR = iemAImpl_subps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);16700 pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);16701 pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);16702 pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);16699 return iemAImpl_subps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0]) 16700 | iemAImpl_addps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1]) 16701 | iemAImpl_subps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2]) 16702 | iemAImpl_addps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]); 16703 16703 } 16704 16704 #endif … … 16709 16709 */ 16710 16710 #ifdef IEM_WITHOUT_ASSEMBLY 16711 IEM_DECL_IMPL_DEF( void, iemAImpl_addsubpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16711 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addsubpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16712 16712 { 16713 16713 RT_NOREF(puSrc1); 16714 16714 16715 pResult->MXCSR = iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);16716 pResult->MXCSR |= iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);16715 return iemAImpl_subpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0]) 16716 | iemAImpl_addpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]); 16717 16717 } 16718 16718 #endif … … 16734 16734 16735 16735 16736 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtpd2ps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16736 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtpd2ps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16737 16737 { 16738 16738 RT_NOREF(puSrc1); 16739 16739 16740 pResult-> MXCSR = iemAImpl_cvtpd2ps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc2->ar64[0]);16741 pResult-> MXCSR |= iemAImpl_cvtpd2ps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc2->ar64[1]);16742 pResult->uResult.au32[2] = 0;16743 pResult->uResult.au32[3] = 0;16740 pResult->au32[2] = 0; 16741 pResult->au32[3] = 0; 16742 return iemAImpl_cvtpd2ps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc2->ar64[0]) 16743 | iemAImpl_cvtpd2ps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc2->ar64[1]); 16744 16744 } 16745 16745 #endif … … 16761 16761 16762 16762 16763 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtps2pd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16763 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16764 16764 { 16765 16765 RT_NOREF(puSrc1); 16766 16766 16767 pResult->MXCSR = iemAImpl_cvtps2pd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc2->ar32[0]);16768 pResult->MXCSR |= iemAImpl_cvtps2pd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc2->ar32[1]);16767 return iemAImpl_cvtps2pd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc2->ar32[0]) 16768 | iemAImpl_cvtps2pd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc2->ar32[1]); 16769 16769 } 16770 16770 #endif … … 16783 16783 16784 16784 16785 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtdq2ps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16785 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtdq2ps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16786 16786 { 16787 16787 RT_NOREF(puSrc1); 16788 16788 16789 pResult->MXCSR = iemAImpl_cvtdq2ps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, puSrc2->ai32[0]);16790 pResult->MXCSR |= iemAImpl_cvtdq2ps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, puSrc2->ai32[1]);16791 pResult->MXCSR |= iemAImpl_cvtdq2ps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, puSrc2->ai32[2]);16792 pResult->MXCSR |= iemAImpl_cvtdq2ps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, puSrc2->ai32[3]);16789 return iemAImpl_cvtdq2ps_u128_worker(&pResult->ar32[0], uMxCsrIn, puSrc2->ai32[0]) 16790 | iemAImpl_cvtdq2ps_u128_worker(&pResult->ar32[1], uMxCsrIn, puSrc2->ai32[1]) 16791 | iemAImpl_cvtdq2ps_u128_worker(&pResult->ar32[2], uMxCsrIn, puSrc2->ai32[2]) 16792 | iemAImpl_cvtdq2ps_u128_worker(&pResult->ar32[3], uMxCsrIn, puSrc2->ai32[3]); 16793 16793 } 16794 16794 #endif … … 16810 16810 16811 16811 16812 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtps2dq_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16812 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtps2dq_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16813 16813 { 16814 16814 RT_NOREF(puSrc1); 16815 16815 16816 pResult->MXCSR = iemAImpl_cvtps2dq_u128_worker(&pResult->uResult.ai32[0], pFpuState->MXCSR, &puSrc2->ar32[0]);16817 pResult->MXCSR |= iemAImpl_cvtps2dq_u128_worker(&pResult->uResult.ai32[1], pFpuState->MXCSR, &puSrc2->ar32[1]);16818 pResult->MXCSR |= iemAImpl_cvtps2dq_u128_worker(&pResult->uResult.ai32[2], pFpuState->MXCSR, &puSrc2->ar32[2]);16819 pResult->MXCSR |= iemAImpl_cvtps2dq_u128_worker(&pResult->uResult.ai32[3], pFpuState->MXCSR, &puSrc2->ar32[3]);16816 return iemAImpl_cvtps2dq_u128_worker(&pResult->ai32[0], uMxCsrIn, &puSrc2->ar32[0]) 16817 | iemAImpl_cvtps2dq_u128_worker(&pResult->ai32[1], uMxCsrIn, &puSrc2->ar32[1]) 16818 | iemAImpl_cvtps2dq_u128_worker(&pResult->ai32[2], uMxCsrIn, &puSrc2->ar32[2]) 16819 | iemAImpl_cvtps2dq_u128_worker(&pResult->ai32[3], uMxCsrIn, &puSrc2->ar32[3]); 16820 16820 } 16821 16821 #endif … … 16838 16838 16839 16839 16840 IEM_DECL_IMPL_DEF( void, iemAImpl_cvttps2dq_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16840 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttps2dq_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16841 16841 { 16842 16842 RT_NOREF(puSrc1); 16843 16843 16844 pResult->MXCSR = iemAImpl_cvttps2dq_u128_worker(&pResult->uResult.ai32[0], pFpuState->MXCSR, &puSrc2->ar32[0]);16845 pResult->MXCSR |= iemAImpl_cvttps2dq_u128_worker(&pResult->uResult.ai32[1], pFpuState->MXCSR, &puSrc2->ar32[1]);16846 pResult->MXCSR |= iemAImpl_cvttps2dq_u128_worker(&pResult->uResult.ai32[2], pFpuState->MXCSR, &puSrc2->ar32[2]);16847 pResult->MXCSR |= iemAImpl_cvttps2dq_u128_worker(&pResult->uResult.ai32[3], pFpuState->MXCSR, &puSrc2->ar32[3]);16844 return iemAImpl_cvttps2dq_u128_worker(&pResult->ai32[0], uMxCsrIn, &puSrc2->ar32[0]) 16845 | iemAImpl_cvttps2dq_u128_worker(&pResult->ai32[1], uMxCsrIn, &puSrc2->ar32[1]) 16846 | iemAImpl_cvttps2dq_u128_worker(&pResult->ai32[2], uMxCsrIn, &puSrc2->ar32[2]) 16847 | iemAImpl_cvttps2dq_u128_worker(&pResult->ai32[3], uMxCsrIn, &puSrc2->ar32[3]); 16848 16848 } 16849 16849 #endif … … 16866 16866 16867 16867 16868 IEM_DECL_IMPL_DEF( void, iemAImpl_cvttpd2dq_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16868 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttpd2dq_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16869 16869 { 16870 16870 RT_NOREF(puSrc1); 16871 16871 16872 pResult-> MXCSR = iemAImpl_cvttpd2dq_u128_worker(&pResult->uResult.ai32[0], pFpuState->MXCSR, &puSrc2->ar64[0]);16873 pResult->MXCSR |= iemAImpl_cvttpd2dq_u128_worker(&pResult->uResult.ai32[1], pFpuState->MXCSR, &puSrc2->ar64[1]);16874 pResult->uResult.au64[1] = 0;16872 pResult->au64[1] = 0; 16873 return iemAImpl_cvttpd2dq_u128_worker(&pResult->ai32[0], uMxCsrIn, &puSrc2->ar64[0]) 16874 | iemAImpl_cvttpd2dq_u128_worker(&pResult->ai32[1], uMxCsrIn, &puSrc2->ar64[1]); 16875 16875 } 16876 16876 #endif … … 16889 16889 16890 16890 16891 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtdq2pd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16891 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtdq2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16892 16892 { 16893 16893 RT_NOREF(puSrc1); 16894 16894 16895 pResult->MXCSR = iemAImpl_cvtdq2pd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, puSrc2->ai32[0]);16896 pResult->MXCSR |= iemAImpl_cvtdq2pd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, puSrc2->ai32[1]);16895 return iemAImpl_cvtdq2pd_u128_worker(&pResult->ar64[0], uMxCsrIn, puSrc2->ai32[0]) 16896 | iemAImpl_cvtdq2pd_u128_worker(&pResult->ar64[1], uMxCsrIn, puSrc2->ai32[1]); 16897 16897 } 16898 16898 #endif … … 16914 16914 16915 16915 16916 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtpd2dq_u128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))16916 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtpd2dq_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16917 16917 { 16918 16918 RT_NOREF(puSrc1); 16919 16919 16920 pResult-> MXCSR = iemAImpl_cvtpd2dq_u128_worker(&pResult->uResult.ai32[0], pFpuState->MXCSR, &puSrc2->ar64[0]);16921 pResult->MXCSR |= iemAImpl_cvtpd2dq_u128_worker(&pResult->uResult.ai32[1], pFpuState->MXCSR, &puSrc2->ar64[1]);16922 pResult->uResult.au64[1] = 0;16920 pResult->au64[1] = 0; 16921 return iemAImpl_cvtpd2dq_u128_worker(&pResult->ai32[0], uMxCsrIn, &puSrc2->ar64[0]) 16922 | iemAImpl_cvtpd2dq_u128_worker(&pResult->ai32[1], uMxCsrIn, &puSrc2->ar64[1]); 16923 16923 } 16924 16924 #endif … … 18232 18232 */ 18233 18233 #ifdef IEM_WITHOUT_ASSEMBLY 18234 IEM_DECL_IMPL_DEF( void, iemAImpl_cvttsd2si_i32_r64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint64_t *pu64Src))18234 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttsd2si_i32_r64,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint64_t *pu64Src)) 18235 18235 { 18236 18236 RTFLOAT64U r64Src; 18237 18237 18238 18238 r64Src.u = *pu64Src; 18239 iemSsePrepareValueR64(&r64Src, pFpuState->MXCSR, &r64Src); /* The de-normal flag is not set. */18240 18241 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18239 iemSsePrepareValueR64(&r64Src, uMxCsrIn, &r64Src); /* The de-normal flag is not set. */ 18240 18241 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18242 18242 *pi32Dst = f64_to_i32_r_minMag(iemFpSoftF64FromIprt(&r64Src), true /*exact*/, &SoftState); 18243 *pfMxcsr = pFpuState->MXCSR| (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);18244 } 18245 18246 18247 IEM_DECL_IMPL_DEF( void, iemAImpl_cvttsd2si_i64_r64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint64_t *pu64Src))18243 return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 18244 } 18245 18246 18247 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttsd2si_i64_r64,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint64_t *pu64Src)) 18248 18248 { 18249 18249 RTFLOAT64U r64Src; 18250 18250 18251 18251 r64Src.u = *pu64Src; 18252 iemSsePrepareValueR64(&r64Src, pFpuState->MXCSR, &r64Src); /* The de-normal flag is not set. */18253 18254 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18252 iemSsePrepareValueR64(&r64Src, uMxCsrIn, &r64Src); /* The de-normal flag is not set. */ 18253 18254 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18255 18255 *pi64Dst = f64_to_i64_r_minMag(iemFpSoftF64FromIprt(&r64Src), true /*exact*/, &SoftState); 18256 *pfMxcsr = pFpuState->MXCSR| (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);18256 return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 18257 18257 } 18258 18258 #endif … … 18263 18263 */ 18264 18264 #ifdef IEM_WITHOUT_ASSEMBLY 18265 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtsd2si_i32_r64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint64_t *pu64Src))18265 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsd2si_i32_r64,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint64_t *pu64Src)) 18266 18266 { 18267 18267 RTFLOAT64U r64Src; 18268 18268 18269 18269 r64Src.u = *pu64Src; 18270 iemSsePrepareValueR64(&r64Src, pFpuState->MXCSR, &r64Src); /* The de-normal flag is not set. */18271 18272 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18270 iemSsePrepareValueR64(&r64Src, uMxCsrIn, &r64Src); /* The de-normal flag is not set. */ 18271 18272 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18273 18273 *pi32Dst = f64_to_i32(iemFpSoftF64FromIprt(&r64Src), SoftState.roundingMode, true /*exact*/, &SoftState); 18274 *pfMxcsr = pFpuState->MXCSR| (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);18275 } 18276 18277 18278 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtsd2si_i64_r64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint64_t *pu64Src))18274 return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 18275 } 18276 18277 18278 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsd2si_i64_r64,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint64_t *pu64Src)) 18279 18279 { 18280 18280 RTFLOAT64U r64Src; 18281 18281 18282 18282 r64Src.u = *pu64Src; 18283 iemSsePrepareValueR64(&r64Src, pFpuState->MXCSR, &r64Src); /* The de-normal flag is not set. */18284 18285 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18283 iemSsePrepareValueR64(&r64Src, uMxCsrIn, &r64Src); /* The de-normal flag is not set. */ 18284 18285 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18286 18286 *pi64Dst = f64_to_i64(iemFpSoftF64FromIprt(&r64Src), SoftState.roundingMode, true /*exact*/, &SoftState); 18287 *pfMxcsr = pFpuState->MXCSR| (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);18287 return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 18288 18288 } 18289 18289 #endif … … 18294 18294 */ 18295 18295 #ifdef IEM_WITHOUT_ASSEMBLY 18296 IEM_DECL_IMPL_DEF( void, iemAImpl_cvttss2si_i32_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src))18296 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttss2si_i32_r32,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint32_t *pu32Src)) 18297 18297 { 18298 18298 RTFLOAT32U r32Src; 18299 18299 18300 18300 r32Src.u = *pu32Src; 18301 iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */18302 18303 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18301 iemSsePrepareValueR32(&r32Src, uMxCsrIn, &r32Src); /* The de-normal flag is not set. */ 18302 18303 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18304 18304 *pi32Dst = f32_to_i32_r_minMag(iemFpSoftF32FromIprt(&r32Src), true /*exact*/, &SoftState); 18305 *pfMxcsr = pFpuState->MXCSR| (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);18306 } 18307 18308 18309 IEM_DECL_IMPL_DEF( void, iemAImpl_cvttss2si_i64_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src))18305 return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 18306 } 18307 18308 18309 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttss2si_i64_r32,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint32_t *pu32Src)) 18310 18310 { 18311 18311 RTFLOAT32U r32Src; 18312 18312 18313 18313 r32Src.u = *pu32Src; 18314 iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */18315 18316 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18314 iemSsePrepareValueR32(&r32Src, uMxCsrIn, &r32Src); /* The de-normal flag is not set. */ 18315 18316 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18317 18317 *pi64Dst = f32_to_i64_r_minMag(iemFpSoftF32FromIprt(&r32Src), true /*exact*/, &SoftState); 18318 *pfMxcsr = pFpuState->MXCSR| (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);18318 return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 18319 18319 } 18320 18320 #endif … … 18325 18325 */ 18326 18326 #ifdef IEM_WITHOUT_ASSEMBLY 18327 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtss2si_i32_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src))18327 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtss2si_i32_r32,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint32_t *pu32Src)) 18328 18328 { 18329 18329 RTFLOAT32U r32Src; 18330 18330 18331 18331 r32Src.u = *pu32Src; 18332 iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */18333 18334 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18332 iemSsePrepareValueR32(&r32Src, uMxCsrIn, &r32Src); /* The de-normal flag is not set. */ 18333 18334 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18335 18335 *pi32Dst = f32_to_i32(iemFpSoftF32FromIprt(&r32Src), SoftState.roundingMode, true /*exact*/, &SoftState); 18336 *pfMxcsr = pFpuState->MXCSR| (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);18337 } 18338 18339 18340 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtss2si_i64_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src))18336 return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 18337 } 18338 18339 18340 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtss2si_i64_r32,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint32_t *pu32Src)) 18341 18341 { 18342 18342 RTFLOAT32U r32Src; 18343 18343 18344 18344 r32Src.u = *pu32Src; 18345 iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */18346 18347 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18345 iemSsePrepareValueR32(&r32Src, uMxCsrIn, &r32Src); /* The de-normal flag is not set. */ 18346 18347 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18348 18348 *pi64Dst = f32_to_i64(iemFpSoftF32FromIprt(&r32Src), SoftState.roundingMode, true /*exact*/, &SoftState); 18349 *pfMxcsr = pFpuState->MXCSR| (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);18349 return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS); 18350 18350 } 18351 18351 #endif … … 18356 18356 */ 18357 18357 #ifdef IEM_WITHOUT_ASSEMBLY 18358 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtsi2sd_r64_i32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t *pi32Src))18359 { 18360 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18358 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsi2sd_r64_i32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src)) 18359 { 18360 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18361 18361 float64_t r64Res = i32_to_f64(*pi32Src, &SoftState); 18362 *pfMxcsr = iemSseSoftStateAndR64ToMxcsrAndIprtResult(&SoftState, r64Res, pr64Dst, pFpuState->MXCSR);18363 } 18364 18365 18366 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtsi2sd_r64_i64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t *pi64Src))18367 { 18368 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18362 return iemSseSoftStateAndR64ToMxcsrAndIprtResult(&SoftState, r64Res, pr64Dst, uMxCsrIn); 18363 } 18364 18365 18366 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsi2sd_r64_i64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src)) 18367 { 18368 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18369 18369 float64_t r64Res = i64_to_f64(*pi64Src, &SoftState); 18370 *pfMxcsr = iemSseSoftStateAndR64ToMxcsrAndIprtResult(&SoftState, r64Res, pr64Dst, pFpuState->MXCSR);18370 return iemSseSoftStateAndR64ToMxcsrAndIprtResult(&SoftState, r64Res, pr64Dst, uMxCsrIn); 18371 18371 } 18372 18372 #endif … … 18377 18377 */ 18378 18378 #ifdef IEM_WITHOUT_ASSEMBLY 18379 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtsi2ss_r32_i32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t *pi32Src))18380 { 18381 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18379 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsi2ss_r32_i32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src)) 18380 { 18381 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18382 18382 float32_t r32Res = i32_to_f32(*pi32Src, &SoftState); 18383 *pfMxcsr = iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Res, pr32Dst, pFpuState->MXCSR);18384 } 18385 18386 18387 IEM_DECL_IMPL_DEF( void, iemAImpl_cvtsi2ss_r32_i64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t *pi64Src))18388 { 18389 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( pFpuState->MXCSR);18383 return iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Res, pr32Dst, uMxCsrIn); 18384 } 18385 18386 18387 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsi2ss_r32_i64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src)) 18388 { 18389 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18390 18390 float32_t r32Res = i64_to_f32(*pi64Src, &SoftState); 18391 *pfMxcsr = iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Res, pr32Dst, pFpuState->MXCSR);18391 return iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Res, pr32Dst, uMxCsrIn); 18392 18392 } 18393 18393 #endif … … 18398 18398 */ 18399 18399 #ifdef IEM_WITHOUT_ASSEMBLY 18400 IEM_DECL_IMPL_DEF( void, iemAImpl_ucomiss_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))18400 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_ucomiss_u128,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18401 18401 { 18402 18402 uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS; … … 18404 18404 if (RTFLOAT32U_IS_SIGNALLING_NAN(&puSrc1->ar32[0]) || RTFLOAT32U_IS_SIGNALLING_NAN(&puSrc2->ar32[0])) 18405 18405 { 18406 *pfMxcsr|= X86_MXCSR_IE;18406 uMxCsrIn |= X86_MXCSR_IE; 18407 18407 fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */ 18408 18408 } … … 18414 18414 else 18415 18415 { 18416 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( *pfMxcsr);18416 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18417 18417 18418 18418 RTFLOAT32U r32Src1, r32Src2; 18419 uint32_t fDe = iemSsePrepareValueR32(&r32Src1, *pfMxcsr, &puSrc1->ar32[0]);18420 fDe |= iemSsePrepareValueR32(&r32Src2, *pfMxcsr, &puSrc2->ar32[0]);18419 uint32_t fDe = iemSsePrepareValueR32(&r32Src1, uMxCsrIn, &puSrc1->ar32[0]); 18420 fDe |= iemSsePrepareValueR32(&r32Src2, uMxCsrIn, &puSrc2->ar32[0]); 18421 18421 18422 18422 float32_t f32Src1 = iemFpSoftF32FromIprt(&r32Src1); … … 18428 18428 /* else: GREATER_THAN 000 */ 18429 18429 18430 *pfMxcsr|= fDe;18430 uMxCsrIn |= fDe; 18431 18431 } 18432 18432 18433 18433 *pfEFlags = fEFlagsNew; 18434 } 18435 #endif 18436 18437 IEM_DECL_IMPL_DEF(void, iemAImpl_vucomiss_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18438 { 18439 iemAImpl_ucomiss_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2); 18434 return uMxCsrIn; 18435 } 18436 #endif 18437 18438 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vucomiss_u128_fallback,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18439 { 18440 return iemAImpl_ucomiss_u128(uMxCsrIn, pfEFlags, puSrc1, puSrc2); 18440 18441 } 18441 18442 … … 18445 18446 */ 18446 18447 #ifdef IEM_WITHOUT_ASSEMBLY 18447 IEM_DECL_IMPL_DEF( void, iemAImpl_ucomisd_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))18448 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_ucomisd_u128,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18448 18449 { 18449 18450 uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS; … … 18451 18452 if (RTFLOAT64U_IS_SIGNALLING_NAN(&puSrc1->ar64[0]) || RTFLOAT64U_IS_SIGNALLING_NAN(&puSrc2->ar64[0])) 18452 18453 { 18453 *pfMxcsr|= X86_MXCSR_IE;18454 uMxCsrIn |= X86_MXCSR_IE; 18454 18455 fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */ 18455 18456 } … … 18461 18462 else 18462 18463 { 18463 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( *pfMxcsr);18464 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18464 18465 18465 18466 RTFLOAT64U r64Src1, r64Src2; 18466 uint32_t fDe = iemSsePrepareValueR64(&r64Src1, *pfMxcsr, &puSrc1->ar64[0])18467 | iemSsePrepareValueR64(&r64Src2, *pfMxcsr, &puSrc2->ar64[0]);18467 uint32_t fDe = iemSsePrepareValueR64(&r64Src1, uMxCsrIn, &puSrc1->ar64[0]) 18468 | iemSsePrepareValueR64(&r64Src2, uMxCsrIn, &puSrc2->ar64[0]); 18468 18469 18469 18470 float64_t f64Src1 = iemFpSoftF64FromIprt(&r64Src1); … … 18475 18476 /* else: GREATER_THAN 000 */ 18476 18477 18477 *pfMxcsr|= fDe;18478 uMxCsrIn |= fDe; 18478 18479 } 18479 18480 18480 18481 *pfEFlags = fEFlagsNew; 18481 } 18482 #endif 18483 18484 IEM_DECL_IMPL_DEF(void, iemAImpl_vucomisd_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18485 { 18486 iemAImpl_ucomisd_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2); 18482 return uMxCsrIn; 18483 } 18484 #endif 18485 18486 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vucomisd_u128_fallback,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18487 { 18488 return iemAImpl_ucomisd_u128(uMxCsrIn, pfEFlags, puSrc1, puSrc2); 18487 18489 } 18488 18490 … … 18492 18494 */ 18493 18495 #ifdef IEM_WITHOUT_ASSEMBLY 18494 IEM_DECL_IMPL_DEF( void, iemAImpl_comiss_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))18496 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_comiss_u128,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18495 18497 { 18496 18498 uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS; … … 18499 18501 || RTFLOAT32U_IS_QUIET_NAN(&puSrc1->ar32[0]) || RTFLOAT32U_IS_QUIET_NAN(&puSrc2->ar32[0])) 18500 18502 { 18501 *pfMxcsr|= X86_MXCSR_IE;18503 uMxCsrIn |= X86_MXCSR_IE; 18502 18504 fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */ 18503 18505 } 18504 18506 else 18505 18507 { 18506 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( *pfMxcsr);18508 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18507 18509 18508 18510 RTFLOAT32U r32Src1, r32Src2; 18509 uint32_t fDe = iemSsePrepareValueR32(&r32Src1, *pfMxcsr, &puSrc1->ar32[0])18510 | iemSsePrepareValueR32(&r32Src2, *pfMxcsr, &puSrc2->ar32[0]);18511 uint32_t fDe = iemSsePrepareValueR32(&r32Src1, uMxCsrIn, &puSrc1->ar32[0]) 18512 | iemSsePrepareValueR32(&r32Src2, uMxCsrIn, &puSrc2->ar32[0]); 18511 18513 18512 18514 float32_t f32Src1 = iemFpSoftF32FromIprt(&r32Src1); … … 18518 18520 /* else: GREATER_THAN 000 */ 18519 18521 18520 *pfMxcsr|= fDe;18522 uMxCsrIn |= fDe; 18521 18523 } 18522 18524 18523 18525 *pfEFlags = fEFlagsNew; 18524 } 18525 #endif 18526 18527 18528 IEM_DECL_IMPL_DEF(void, iemAImpl_vcomiss_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18529 { 18530 iemAImpl_comiss_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2); 18526 return uMxCsrIn; 18527 } 18528 #endif 18529 18530 18531 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcomiss_u128_fallback,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18532 { 18533 return iemAImpl_comiss_u128(uMxCsrIn, pfEFlags, puSrc1, puSrc2); 18531 18534 } 18532 18535 … … 18536 18539 */ 18537 18540 #ifdef IEM_WITHOUT_ASSEMBLY 18538 IEM_DECL_IMPL_DEF( void, iemAImpl_comisd_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))18541 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_comisd_u128,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18539 18542 { 18540 18543 uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS; … … 18543 18546 || RTFLOAT64U_IS_QUIET_NAN(&puSrc1->ar64[0]) || RTFLOAT64U_IS_QUIET_NAN(&puSrc2->ar64[0])) 18544 18547 { 18545 *pfMxcsr|= X86_MXCSR_IE;18548 uMxCsrIn |= X86_MXCSR_IE; 18546 18549 fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */ 18547 18550 } 18548 18551 else 18549 18552 { 18550 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR( *pfMxcsr);18553 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn); 18551 18554 18552 18555 RTFLOAT64U r64Src1, r64Src2; 18553 uint32_t fDe = iemSsePrepareValueR64(&r64Src1, *pfMxcsr, &puSrc1->ar64[0]);18554 fDe |= iemSsePrepareValueR64(&r64Src2, *pfMxcsr, &puSrc2->ar64[0]);18556 uint32_t fDe = iemSsePrepareValueR64(&r64Src1, uMxCsrIn, &puSrc1->ar64[0]); 18557 fDe |= iemSsePrepareValueR64(&r64Src2, uMxCsrIn, &puSrc2->ar64[0]); 18555 18558 18556 18559 float64_t f64Src1 = iemFpSoftF64FromIprt(&r64Src1); … … 18562 18565 /* else: GREATER_THAN 000 */ 18563 18566 18564 *pfMxcsr|= fDe;18567 uMxCsrIn |= fDe; 18565 18568 } 18566 18569 18567 18570 *pfEFlags = fEFlagsNew; 18568 } 18569 #endif 18570 18571 IEM_DECL_IMPL_DEF(void, iemAImpl_vcomisd_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18572 { 18573 iemAImpl_comisd_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2); 18571 return uMxCsrIn; 18572 } 18573 #endif 18574 18575 IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcomisd_u128_fallback,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 18576 { 18577 return iemAImpl_comisd_u128(uMxCsrIn, pfEFlags, puSrc1, puSrc2); 18574 18578 } 18575 18579 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r104099 r104129 2995 2995 'IEM_MC_CALL_AVX_AIMPL_2': (McBlock.parseMcCallAvxAImpl, True, True, g_fNativeSimd), 2996 2996 'IEM_MC_CALL_AVX_AIMPL_3': (McBlock.parseMcCallAvxAImpl, True, True, g_fNativeSimd), 2997 'IEM_MC_CALL_AVX_AIMPL_NEW_3': (McBlock.parseMcCallAvxAImpl, True, True, False, ), 2997 2998 'IEM_MC_CALL_CIMPL_0': (McBlock.parseMcCallCImpl, True, True, False, ), 2998 2999 'IEM_MC_CALL_CIMPL_1': (McBlock.parseMcCallCImpl, True, True, False, ), … … 3055 3056 'IEM_MC_FETCH_MEM_I16': (McBlock.parseMcGeneric, True, True, False, ), 3056 3057 'IEM_MC_FETCH_MEM_I32': (McBlock.parseMcGeneric, True, True, False, ), 3057 'IEM_MC_FETCH_MEM_I64': (McBlock.parseMcGeneric, True, True, False, ),3058 'IEM_MC_FETCH_MEM_I64': (McBlock.parseMcGeneric, True, True, False, ), 3058 3059 'IEM_MC_FETCH_MEM_R32': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), 3059 3060 'IEM_MC_FETCH_MEM_R64': (McBlock.parseMcGeneric, True, True, g_fNativeSimd), -
trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
r104118 r104129 654 654 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 655 655 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 656 IEM_MC_LOCAL( IEMSSERESULT,SseRes);657 IEM_MC_ARG_LOCAL_REF(P IEMSSERESULT,pSseRes, SseRes, 0);656 IEM_MC_LOCAL(X86XMMREG, SseRes); 657 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pSseRes, SseRes, 0); 658 658 IEM_MC_ARG(PCX86XMMREG, pSrc1, 1); 659 659 IEM_MC_ARG(PCX86XMMREG, pSrc2, 2); … … 675 675 */ 676 676 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 677 IEM_MC_LOCAL( IEMSSERESULT,SseRes);677 IEM_MC_LOCAL(X86XMMREG, SseRes); 678 678 IEM_MC_LOCAL(X86XMMREG, uSrc2); 679 IEM_MC_ARG_LOCAL_REF(P IEMSSERESULT,pSseRes, SseRes, 0);679 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pSseRes, SseRes, 0); 680 680 IEM_MC_ARG(PCX86XMMREG, pSrc1, 1); 681 681 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, pSrc2, uSrc2, 2); … … 718 718 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 719 719 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 720 IEM_MC_LOCAL( IEMSSERESULT,SseRes);721 IEM_MC_ARG_LOCAL_REF(P IEMSSERESULT,pSseRes, SseRes, 0);720 IEM_MC_LOCAL(X86XMMREG, SseRes); 721 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pSseRes, SseRes, 0); 722 722 IEM_MC_ARG(PCX86XMMREG, pSrc1, 1); 723 723 IEM_MC_ARG(PCRTFLOAT32U, pSrc2, 2); … … 739 739 */ 740 740 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 741 IEM_MC_LOCAL( IEMSSERESULT,SseRes);741 IEM_MC_LOCAL(X86XMMREG, SseRes); 742 742 IEM_MC_LOCAL(RTFLOAT32U, r32Src2); 743 IEM_MC_ARG_LOCAL_REF(P IEMSSERESULT,pSseRes, SseRes, 0);743 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pSseRes, SseRes, 0); 744 744 IEM_MC_ARG(PCX86XMMREG, pSrc1, 1); 745 745 IEM_MC_ARG_LOCAL_REF(PCRTFLOAT32U, pr32Src2, r32Src2, 2); … … 782 782 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 783 783 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 784 IEM_MC_LOCAL( IEMSSERESULT,SseRes);785 IEM_MC_ARG_LOCAL_REF(P IEMSSERESULT,pSseRes, SseRes, 0);784 IEM_MC_LOCAL(X86XMMREG, SseRes); 785 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pSseRes, SseRes, 0); 786 786 IEM_MC_ARG(PCX86XMMREG, pSrc1, 1); 787 787 IEM_MC_ARG(PCX86XMMREG, pSrc2, 2); … … 803 803 */ 804 804 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 805 IEM_MC_LOCAL( IEMSSERESULT,SseRes);805 IEM_MC_LOCAL(X86XMMREG, SseRes); 806 806 IEM_MC_LOCAL(X86XMMREG, uSrc2); 807 IEM_MC_ARG_LOCAL_REF(P IEMSSERESULT,pSseRes, SseRes, 0);807 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pSseRes, SseRes, 0); 808 808 IEM_MC_ARG(PCX86XMMREG, pSrc1, 1); 809 809 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, pSrc2, uSrc2, 2); … … 846 846 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 847 847 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 848 IEM_MC_LOCAL( IEMSSERESULT,SseRes);849 IEM_MC_ARG_LOCAL_REF(P IEMSSERESULT,pSseRes, SseRes, 0);848 IEM_MC_LOCAL(X86XMMREG, SseRes); 849 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pSseRes, SseRes, 0); 850 850 IEM_MC_ARG(PCX86XMMREG, pSrc1, 1); 851 851 IEM_MC_ARG(PCRTFLOAT64U, pSrc2, 2); … … 867 867 */ 868 868 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 869 IEM_MC_LOCAL( IEMSSERESULT,SseRes);869 IEM_MC_LOCAL(X86XMMREG, SseRes); 870 870 IEM_MC_LOCAL(RTFLOAT64U, r64Src2); 871 IEM_MC_ARG_LOCAL_REF(P IEMSSERESULT,pSseRes, SseRes, 0);871 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pSseRes, SseRes, 0); 872 872 IEM_MC_ARG(PCX86XMMREG, pSrc1, 1); 873 873 IEM_MC_ARG_LOCAL_REF(PCRTFLOAT64U, pr64Src2, r64Src2, 2); … … 970 970 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 971 971 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3); 972 IEM_MC_LOCAL( IEMSSERESULT,SseRes);973 IEM_MC_ARG_LOCAL_REF(P IEMSSERESULT,pSseRes, SseRes, 0);972 IEM_MC_LOCAL(X86XMMREG, SseRes); 973 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pSseRes, SseRes, 0); 974 974 IEM_MC_ARG(PCX86XMMREG, pSrc1, 1); 975 975 IEM_MC_ARG(PCX86XMMREG, pSrc2, 2); … … 991 991 */ 992 992 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 993 IEM_MC_LOCAL( IEMSSERESULT,SseRes);993 IEM_MC_LOCAL(X86XMMREG, SseRes); 994 994 IEM_MC_LOCAL(X86XMMREG, uSrc2); 995 IEM_MC_ARG_LOCAL_REF(P IEMSSERESULT,pSseRes, SseRes, 0);995 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pSseRes, SseRes, 0); 996 996 IEM_MC_ARG(PCX86XMMREG, pSrc1, 1); 997 997 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, pSrc2, uSrc2, 2); … … 3614 3614 /* XMM, greg64 */ 3615 3615 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 3616 IEM_MC_LOCAL(uint32_t, fMxcsr);3617 3616 IEM_MC_LOCAL(RTFLOAT32U, r32Dst); 3618 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3619 IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U, pr32Dst, r32Dst, 1); 3620 IEM_MC_ARG(const int64_t *, pi64Src, 2); 3617 IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U, pr32Dst, r32Dst, 0); 3618 IEM_MC_ARG(const int64_t *, pi64Src, 1); 3621 3619 3622 3620 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 3623 3621 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3624 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */3622 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 3625 3623 3626 3624 IEM_MC_REF_GREG_I64_CONST(pi64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 3627 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2ss_r32_i64, pfMxcsr, pr32Dst, pi64Src); 3628 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3625 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i64, pr32Dst, pi64Src); 3629 3626 IEM_MC_IF_MXCSR_XCPT_PENDING() { 3630 3627 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 3641 3638 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 3642 3639 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 3643 IEM_MC_LOCAL(uint32_t, fMxcsr);3644 3640 IEM_MC_LOCAL(RTFLOAT32U, r32Dst); 3645 3641 IEM_MC_LOCAL(int64_t, i64Src); 3646 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3647 IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U, pr32Dst, r32Dst, 1); 3648 IEM_MC_ARG_LOCAL_REF(const int64_t *, pi64Src, i64Src, 2); 3642 IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U, pr32Dst, r32Dst, 0); 3643 IEM_MC_ARG_LOCAL_REF(const int64_t *, pi64Src, i64Src, 1); 3649 3644 3650 3645 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 3651 3646 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 3652 3647 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3653 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */3648 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 3654 3649 3655 3650 IEM_MC_FETCH_MEM_I64(i64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 3656 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2ss_r32_i64, pfMxcsr, pr32Dst, pi64Src); 3657 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3651 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i64, pr32Dst, pi64Src); 3658 3652 IEM_MC_IF_MXCSR_XCPT_PENDING() { 3659 3653 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 3672 3666 /* greg, XMM */ 3673 3667 IEM_MC_BEGIN(0, 0); 3674 IEM_MC_LOCAL(uint32_t, fMxcsr);3675 3668 IEM_MC_LOCAL(RTFLOAT32U, r32Dst); 3676 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3677 IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U, pr32Dst, r32Dst, 1); 3678 IEM_MC_ARG(const int32_t *, pi32Src, 2); 3669 IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U, pr32Dst, r32Dst, 0); 3670 IEM_MC_ARG(const int32_t *, pi32Src, 1); 3679 3671 3680 3672 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 3681 3673 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3682 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */3674 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 3683 3675 3684 3676 IEM_MC_REF_GREG_I32_CONST(pi32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 3685 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2ss_r32_i32, pfMxcsr, pr32Dst, pi32Src); 3686 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3677 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i32, pr32Dst, pi32Src); 3687 3678 IEM_MC_IF_MXCSR_XCPT_PENDING() { 3688 3679 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 3699 3690 IEM_MC_BEGIN(0, 0); 3700 3691 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 3701 IEM_MC_LOCAL(uint32_t, fMxcsr);3702 3692 IEM_MC_LOCAL(RTFLOAT32U, r32Dst); 3703 3693 IEM_MC_LOCAL(int32_t, i32Src); 3704 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3705 IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U, pr32Dst, r32Dst, 1); 3706 IEM_MC_ARG_LOCAL_REF(const int32_t *, pi32Src, i32Src, 2); 3694 IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U, pr32Dst, r32Dst, 0); 3695 IEM_MC_ARG_LOCAL_REF(const int32_t *, pi32Src, i32Src, 1); 3707 3696 3708 3697 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 3709 3698 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 3710 3699 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3711 IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */3700 IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 3712 3701 3713 3702 IEM_MC_FETCH_MEM_I32(i32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 3714 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2ss_r32_i32, pfMxcsr, pr32Dst, pi32Src); 3715 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3703 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i32, pr32Dst, pi32Src); 3716 3704 IEM_MC_IF_MXCSR_XCPT_PENDING() { 3717 3705 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 3739 3727 /* XMM, greg64 */ 3740 3728 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 3741 IEM_MC_LOCAL(uint32_t, fMxcsr);3742 3729 IEM_MC_LOCAL(RTFLOAT64U, r64Dst); 3743 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3744 IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Dst, r64Dst, 1); 3745 IEM_MC_ARG(const int64_t *, pi64Src, 2); 3730 IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Dst, r64Dst, 0); 3731 IEM_MC_ARG(const int64_t *, pi64Src, 1); 3746 3732 3747 3733 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 3748 3734 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3749 IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */3735 IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 3750 3736 3751 3737 IEM_MC_REF_GREG_I64_CONST(pi64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 3752 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2sd_r64_i64, pfMxcsr, pr64Dst, pi64Src); 3753 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3738 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i64, pr64Dst, pi64Src); 3754 3739 IEM_MC_IF_MXCSR_XCPT_PENDING() { 3755 3740 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 3766 3751 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 3767 3752 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 3768 IEM_MC_LOCAL(uint32_t, fMxcsr);3769 3753 IEM_MC_LOCAL(RTFLOAT64U, r64Dst); 3770 3754 IEM_MC_LOCAL(int64_t, i64Src); 3771 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3772 IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Dst, r64Dst, 1); 3773 IEM_MC_ARG_LOCAL_REF(const int64_t *, pi64Src, i64Src, 2); 3755 IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Dst, r64Dst, 0); 3756 IEM_MC_ARG_LOCAL_REF(const int64_t *, pi64Src, i64Src, 1); 3774 3757 3775 3758 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 3776 3759 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 3777 3760 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3778 IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */3761 IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 3779 3762 3780 3763 IEM_MC_FETCH_MEM_I64(i64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 3781 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2sd_r64_i64, pfMxcsr, pr64Dst, pi64Src); 3782 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3764 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i64, pr64Dst, pi64Src); 3783 3765 IEM_MC_IF_MXCSR_XCPT_PENDING() { 3784 3766 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 3797 3779 /* XMM, greg32 */ 3798 3780 IEM_MC_BEGIN(0, 0); 3799 IEM_MC_LOCAL(uint32_t, fMxcsr);3800 3781 IEM_MC_LOCAL(RTFLOAT64U, r64Dst); 3801 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3802 IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Dst, r64Dst, 1); 3803 IEM_MC_ARG(const int32_t *, pi32Src, 2); 3782 IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Dst, r64Dst, 0); 3783 IEM_MC_ARG(const int32_t *, pi32Src, 1); 3804 3784 3805 3785 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 3806 3786 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3807 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */3787 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 3808 3788 3809 3789 IEM_MC_REF_GREG_I32_CONST(pi32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 3810 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2sd_r64_i32, pfMxcsr, pr64Dst, pi32Src); 3811 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3790 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i32, pr64Dst, pi32Src); 3812 3791 IEM_MC_IF_MXCSR_XCPT_PENDING() { 3813 3792 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 3824 3803 IEM_MC_BEGIN(0, 0); 3825 3804 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 3826 IEM_MC_LOCAL(uint32_t, fMxcsr);3827 3805 IEM_MC_LOCAL(RTFLOAT64U, r64Dst); 3828 3806 IEM_MC_LOCAL(int32_t, i32Src); 3829 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 3830 IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Dst, r64Dst, 1); 3831 IEM_MC_ARG_LOCAL_REF(const int32_t *, pi32Src, i32Src, 2); 3807 IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Dst, r64Dst, 0); 3808 IEM_MC_ARG_LOCAL_REF(const int32_t *, pi32Src, i32Src, 1); 3832 3809 3833 3810 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 3834 3811 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 3835 3812 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 3836 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */3813 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 3837 3814 3838 3815 IEM_MC_FETCH_MEM_I32(i32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 3839 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2sd_r64_i32, pfMxcsr, pr64Dst, pi32Src); 3840 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 3816 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i32, pr64Dst, pi32Src); 3841 3817 IEM_MC_IF_MXCSR_XCPT_PENDING() { 3842 3818 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4081 4057 /* greg64, XMM */ 4082 4058 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 4083 IEM_MC_LOCAL(uint32_t, fMxcsr);4084 4059 IEM_MC_LOCAL(int64_t, i64Dst); 4085 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4086 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 4087 IEM_MC_ARG(const uint32_t *, pu32Src, 2); 4060 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 0); 4061 IEM_MC_ARG(const uint32_t *, pu32Src, 1); 4088 4062 4089 4063 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 4090 4064 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4091 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4065 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4092 4066 4093 4067 IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 4094 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src); 4095 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4068 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i64_r32, pi64Dst, pu32Src); 4096 4069 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4097 4070 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4108 4081 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 4109 4082 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4110 IEM_MC_LOCAL(uint32_t, fMxcsr);4111 4083 IEM_MC_LOCAL(int64_t, i64Dst); 4112 4084 IEM_MC_LOCAL(uint32_t, u32Src); 4113 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4114 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 4115 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 2); 4085 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 0); 4086 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 1); 4116 4087 4117 4088 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4118 4089 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 4119 4090 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4120 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4091 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4121 4092 4122 4093 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4123 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src); 4124 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4094 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i64_r32, pi64Dst, pu32Src); 4125 4095 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4126 4096 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4139 4109 /* greg, XMM */ 4140 4110 IEM_MC_BEGIN(0, 0); 4141 IEM_MC_LOCAL(uint32_t, fMxcsr);4142 4111 IEM_MC_LOCAL(int32_t, i32Dst); 4143 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4144 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 4145 IEM_MC_ARG(const uint32_t *, pu32Src, 2); 4112 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 0); 4113 IEM_MC_ARG(const uint32_t *, pu32Src, 1); 4146 4114 4147 4115 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 4148 4116 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4149 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4117 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4150 4118 4151 4119 IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 4152 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src); 4153 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4120 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i32_r32, pi32Dst, pu32Src); 4154 4121 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4155 4122 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4166 4133 IEM_MC_BEGIN(0, 0); 4167 4134 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4168 IEM_MC_LOCAL(uint32_t, fMxcsr);4169 4135 IEM_MC_LOCAL(int32_t, i32Dst); 4170 4136 IEM_MC_LOCAL(uint32_t, u32Src); 4171 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4172 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 4173 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 2); 4137 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 0); 4138 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 1); 4174 4139 4175 4140 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4176 4141 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 4177 4142 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4178 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4143 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4179 4144 4180 4145 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4181 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src); 4182 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4146 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i32_r32, pi32Dst, pu32Src); 4183 4147 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4184 4148 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4206 4170 /* greg64, XMM */ 4207 4171 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 4208 IEM_MC_LOCAL(uint32_t, fMxcsr);4209 4172 IEM_MC_LOCAL(int64_t, i64Dst); 4210 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4211 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 4212 IEM_MC_ARG(const uint64_t *, pu64Src, 2); 4173 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 0); 4174 IEM_MC_ARG(const uint64_t *, pu64Src, 1); 4213 4175 4214 4176 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 4215 4177 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4216 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4178 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4217 4179 4218 4180 IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 4219 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttsd2si_i64_r64, pfMxcsr, pi64Dst, pu64Src); 4220 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4181 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i64_r64, pi64Dst, pu64Src); 4221 4182 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4222 4183 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4233 4194 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 4234 4195 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4235 IEM_MC_LOCAL(uint32_t, fMxcsr);4236 4196 IEM_MC_LOCAL(int64_t, i64Dst); 4237 4197 IEM_MC_LOCAL(uint64_t, u64Src); 4238 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4239 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 4240 IEM_MC_ARG_LOCAL_REF(const uint64_t *, pu64Src, u64Src, 2); 4198 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 0); 4199 IEM_MC_ARG_LOCAL_REF(const uint64_t *, pu64Src, u64Src, 1); 4241 4200 4242 4201 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4243 4202 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 4244 4203 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4245 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4204 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4246 4205 4247 4206 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4248 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttsd2si_i64_r64, pfMxcsr, pi64Dst, pu64Src); 4249 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4207 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i64_r64, pi64Dst, pu64Src); 4250 4208 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4251 4209 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4264 4222 /* greg, XMM */ 4265 4223 IEM_MC_BEGIN(0, 0); 4266 IEM_MC_LOCAL(uint32_t, fMxcsr);4267 4224 IEM_MC_LOCAL(int32_t, i32Dst); 4268 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4269 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 4270 IEM_MC_ARG(const uint64_t *, pu64Src, 2); 4225 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 0); 4226 IEM_MC_ARG(const uint64_t *, pu64Src, 1); 4271 4227 4272 4228 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 4273 4229 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4274 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4230 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4275 4231 4276 4232 IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 4277 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttsd2si_i32_r64, pfMxcsr, pi32Dst, pu64Src); 4278 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4233 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i32_r64, pi32Dst, pu64Src); 4279 4234 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4280 4235 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4291 4246 IEM_MC_BEGIN(0, 0); 4292 4247 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4293 IEM_MC_LOCAL(uint32_t, fMxcsr);4294 4248 IEM_MC_LOCAL(int32_t, i32Dst); 4295 4249 IEM_MC_LOCAL(uint64_t, u64Src); 4296 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4297 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 4298 IEM_MC_ARG_LOCAL_REF(const uint64_t *, pu64Src, u64Src, 2); 4250 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 0); 4251 IEM_MC_ARG_LOCAL_REF(const uint64_t *, pu64Src, u64Src, 1); 4299 4252 4300 4253 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4301 4254 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 4302 4255 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4303 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4256 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4304 4257 4305 4258 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4306 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttsd2si_i32_r64, pfMxcsr, pi32Dst, pu64Src); 4307 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4259 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i32_r64, pi32Dst, pu64Src); 4308 4260 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4309 4261 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4469 4421 /* greg64, XMM */ 4470 4422 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 4471 IEM_MC_LOCAL(uint32_t, fMxcsr);4472 4423 IEM_MC_LOCAL(int64_t, i64Dst); 4473 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4474 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 4475 IEM_MC_ARG(const uint32_t *, pu32Src, 2); 4424 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 0); 4425 IEM_MC_ARG(const uint32_t *, pu32Src, 1); 4476 4426 4477 4427 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 4478 4428 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4479 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4429 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4480 4430 4481 4431 IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 4482 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src); 4483 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4432 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i64_r32, pi64Dst, pu32Src); 4484 4433 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4485 4434 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4496 4445 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 4497 4446 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4498 IEM_MC_LOCAL(uint32_t, fMxcsr);4499 4447 IEM_MC_LOCAL(int64_t, i64Dst); 4500 4448 IEM_MC_LOCAL(uint32_t, u32Src); 4501 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4502 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 4503 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 2); 4449 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 0); 4450 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 1); 4504 4451 4505 4452 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4506 4453 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 4507 4454 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4508 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4455 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4509 4456 4510 4457 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4511 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src); 4512 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4458 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i64_r32, pi64Dst, pu32Src); 4513 4459 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4514 4460 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4527 4473 /* greg, XMM */ 4528 4474 IEM_MC_BEGIN(0, 0); 4529 IEM_MC_LOCAL(uint32_t, fMxcsr);4530 4475 IEM_MC_LOCAL(int32_t, i32Dst); 4531 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4532 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 4533 IEM_MC_ARG(const uint32_t *, pu32Src, 2); 4476 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 0); 4477 IEM_MC_ARG(const uint32_t *, pu32Src, 1); 4534 4478 4535 4479 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 4536 4480 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4537 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4481 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4538 4482 4539 4483 IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 4540 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src); 4541 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4484 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i32_r32, pi32Dst, pu32Src); 4542 4485 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4543 4486 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4554 4497 IEM_MC_BEGIN(0, 0); 4555 4498 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4556 IEM_MC_LOCAL(uint32_t, fMxcsr);4557 4499 IEM_MC_LOCAL(int32_t, i32Dst); 4558 4500 IEM_MC_LOCAL(uint32_t, u32Src); 4559 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4560 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 4561 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 2); 4501 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 0); 4502 IEM_MC_ARG_LOCAL_REF(const uint32_t *, pu32Src, u32Src, 1); 4562 4503 4563 4504 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4564 4505 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 4565 4506 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4566 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4507 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4567 4508 4568 4509 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4569 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src); 4570 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4510 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i32_r32, pi32Dst, pu32Src); 4571 4511 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4572 4512 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4594 4534 /* greg64, XMM */ 4595 4535 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 4596 IEM_MC_LOCAL(uint32_t, fMxcsr);4597 4536 IEM_MC_LOCAL(int64_t, i64Dst); 4598 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4599 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 4600 IEM_MC_ARG(const uint64_t *, pu64Src, 2); 4537 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 0); 4538 IEM_MC_ARG(const uint64_t *, pu64Src, 1); 4601 4539 4602 4540 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 4603 4541 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4604 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4542 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4605 4543 4606 4544 IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 4607 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i64_r64, pfMxcsr, pi64Dst, pu64Src); 4608 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4545 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i64_r64, pi64Dst, pu64Src); 4609 4546 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4610 4547 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4621 4558 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); 4622 4559 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4623 IEM_MC_LOCAL(uint32_t, fMxcsr);4624 4560 IEM_MC_LOCAL(int64_t, i64Dst); 4625 4561 IEM_MC_LOCAL(uint64_t, u64Src); 4626 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4627 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 1); 4628 IEM_MC_ARG_LOCAL_REF(const uint64_t *, pu64Src, u64Src, 2); 4562 IEM_MC_ARG_LOCAL_REF(int64_t *, pi64Dst, i64Dst, 0); 4563 IEM_MC_ARG_LOCAL_REF(const uint64_t *, pu64Src, u64Src, 1); 4629 4564 4630 4565 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); … … 4634 4569 4635 4570 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4636 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i64_r64, pfMxcsr, pi64Dst, pu64Src); 4637 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4571 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i64_r64, pi64Dst, pu64Src); 4638 4572 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4639 4573 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4652 4586 /* greg32, XMM */ 4653 4587 IEM_MC_BEGIN(0, 0); 4654 IEM_MC_LOCAL(uint32_t, fMxcsr);4655 4588 IEM_MC_LOCAL(int32_t, i32Dst); 4656 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4657 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 4658 IEM_MC_ARG(const uint64_t *, pu64Src, 2); 4589 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 0); 4590 IEM_MC_ARG(const uint64_t *, pu64Src, 1); 4659 4591 4660 4592 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 4661 4593 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4662 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4594 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4663 4595 4664 4596 IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); 4665 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i32_r64, pfMxcsr, pi32Dst, pu64Src); 4666 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4597 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i32_r64, pi32Dst, pu64Src); 4667 4598 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4668 4599 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4679 4610 IEM_MC_BEGIN(0, 0); 4680 4611 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4681 IEM_MC_LOCAL(uint32_t, fMxcsr);4682 4612 IEM_MC_LOCAL(int32_t, i32Dst); 4683 4613 IEM_MC_LOCAL(uint64_t, u64Src); 4684 IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr, 0); 4685 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 1); 4686 IEM_MC_ARG_LOCAL_REF(const uint64_t *, pu64Src, u64Src, 2); 4614 IEM_MC_ARG_LOCAL_REF(int32_t *, pi32Dst, i32Dst, 0); 4615 IEM_MC_ARG_LOCAL_REF(const uint64_t *, pu64Src, u64Src, 1); 4687 4616 4688 4617 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4689 4618 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 4690 4619 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4691 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_ 3() is calling this but the tstIEMCheckMc testcase depends on it. */4620 IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */ 4692 4621 4693 4622 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4694 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i32_r64, pfMxcsr, pi32Dst, pu64Src); 4695 IEM_MC_SSE_UPDATE_MXCSR(fMxcsr); 4623 IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i32_r64, pi32Dst, pu64Src); 4696 4624 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4697 4625 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4725 4653 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 4726 4654 IEM_MC_LOCAL(uint32_t, fEFlags); 4727 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4728 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4729 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4730 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 4655 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 4656 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 4657 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2); 4731 4658 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4732 4659 IEM_MC_PREPARE_SSE_USAGE(); 4733 4660 IEM_MC_FETCH_EFLAGS(fEFlags); 4734 IEM_MC_REF_MXCSR(pfMxcsr);4735 4661 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4736 4662 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 4737 IEM_MC_CALL_ VOID_AIMPL_4(iemAImpl_ucomiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);4663 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomiss_u128, pEFlags, puSrc1, puSrc2); 4738 4664 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4739 4665 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4752 4678 IEM_MC_BEGIN(0, 0); 4753 4679 IEM_MC_LOCAL(uint32_t, fEFlags); 4754 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4755 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4756 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4680 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 4681 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 4757 4682 IEM_MC_LOCAL(X86XMMREG, uSrc2); 4758 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);4683 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2); 4759 4684 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4760 4685 … … 4766 4691 IEM_MC_PREPARE_SSE_USAGE(); 4767 4692 IEM_MC_FETCH_EFLAGS(fEFlags); 4768 IEM_MC_REF_MXCSR(pfMxcsr);4769 4693 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4770 IEM_MC_CALL_ VOID_AIMPL_4(iemAImpl_ucomiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);4694 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomiss_u128, pEFlags, puSrc1, puSrc2); 4771 4695 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4772 4696 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4799 4723 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 4800 4724 IEM_MC_LOCAL(uint32_t, fEFlags); 4801 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4802 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4803 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4804 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 4725 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 4726 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 4727 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2); 4805 4728 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4806 4729 IEM_MC_PREPARE_SSE_USAGE(); 4807 4730 IEM_MC_FETCH_EFLAGS(fEFlags); 4808 IEM_MC_REF_MXCSR(pfMxcsr);4809 4731 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4810 4732 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 4811 IEM_MC_CALL_ VOID_AIMPL_4(iemAImpl_ucomisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);4733 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomisd_u128, pEFlags, puSrc1, puSrc2); 4812 4734 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4813 4735 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4826 4748 IEM_MC_BEGIN(0, 0); 4827 4749 IEM_MC_LOCAL(uint32_t, fEFlags); 4828 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4829 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4830 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4750 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 4751 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 4831 4752 IEM_MC_LOCAL(X86XMMREG, uSrc2); 4832 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);4753 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2); 4833 4754 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4834 4755 … … 4840 4761 IEM_MC_PREPARE_SSE_USAGE(); 4841 4762 IEM_MC_FETCH_EFLAGS(fEFlags); 4842 IEM_MC_REF_MXCSR(pfMxcsr);4843 4763 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4844 IEM_MC_CALL_ VOID_AIMPL_4(iemAImpl_ucomisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);4764 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomisd_u128, pEFlags, puSrc1, puSrc2); 4845 4765 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4846 4766 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4877 4797 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse); 4878 4798 IEM_MC_LOCAL(uint32_t, fEFlags); 4879 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4880 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4881 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4882 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 4799 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 4800 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 4801 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2); 4883 4802 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4884 4803 IEM_MC_PREPARE_SSE_USAGE(); 4885 4804 IEM_MC_FETCH_EFLAGS(fEFlags); 4886 IEM_MC_REF_MXCSR(pfMxcsr);4887 4805 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4888 4806 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 4889 IEM_MC_CALL_ VOID_AIMPL_4(iemAImpl_comiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);4807 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comiss_u128, pEFlags, puSrc1, puSrc2); 4890 4808 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4891 4809 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4904 4822 IEM_MC_BEGIN(0, 0); 4905 4823 IEM_MC_LOCAL(uint32_t, fEFlags); 4906 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4907 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4908 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4824 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 4825 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 4909 4826 IEM_MC_LOCAL(X86XMMREG, uSrc2); 4910 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);4827 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2); 4911 4828 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4912 4829 … … 4918 4835 IEM_MC_PREPARE_SSE_USAGE(); 4919 4836 IEM_MC_FETCH_EFLAGS(fEFlags); 4920 IEM_MC_REF_MXCSR(pfMxcsr);4921 4837 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4922 IEM_MC_CALL_ VOID_AIMPL_4(iemAImpl_comiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);4838 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comiss_u128, pEFlags, puSrc1, puSrc2); 4923 4839 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4924 4840 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4951 4867 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2); 4952 4868 IEM_MC_LOCAL(uint32_t, fEFlags); 4953 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4954 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4955 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4956 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 4869 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 4870 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 4871 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2); 4957 4872 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4958 4873 IEM_MC_PREPARE_SSE_USAGE(); 4959 4874 IEM_MC_FETCH_EFLAGS(fEFlags); 4960 IEM_MC_REF_MXCSR(pfMxcsr);4961 4875 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4962 4876 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 4963 IEM_MC_CALL_ VOID_AIMPL_4(iemAImpl_comisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);4877 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comisd_u128, pEFlags, puSrc1, puSrc2); 4964 4878 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4965 4879 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 4978 4892 IEM_MC_BEGIN(0, 0); 4979 4893 IEM_MC_LOCAL(uint32_t, fEFlags); 4980 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4981 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4982 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4894 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 4895 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 4983 4896 IEM_MC_LOCAL(X86XMMREG, uSrc2); 4984 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);4897 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2); 4985 4898 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4986 4899 … … 4992 4905 IEM_MC_PREPARE_SSE_USAGE(); 4993 4906 IEM_MC_FETCH_EFLAGS(fEFlags); 4994 IEM_MC_REF_MXCSR(pfMxcsr);4995 4907 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4996 IEM_MC_CALL_ VOID_AIMPL_4(iemAImpl_comisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);4908 IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comisd_u128, pEFlags, puSrc1, puSrc2); 4997 4909 IEM_MC_IF_MXCSR_XCPT_PENDING() { 4998 4910 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); -
trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h
r104076 r104129 2296 2296 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx); 2297 2297 IEM_MC_LOCAL(uint32_t, fEFlags); 2298 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2299 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2300 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2301 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 2298 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 2299 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 2300 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2); 2302 2301 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2303 2302 IEM_MC_PREPARE_AVX_USAGE(); 2304 2303 IEM_MC_FETCH_EFLAGS(fEFlags); 2305 IEM_MC_REF_MXCSR(pfMxcsr);2306 2304 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2307 2305 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 2308 IEM_MC_CALL_ VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),2309 pfMxcsr,pEFlags, puSrc1, puSrc2);2306 IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback), 2307 pEFlags, puSrc1, puSrc2); 2310 2308 IEM_MC_IF_MXCSR_XCPT_PENDING() { 2311 2309 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 2324 2322 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 2325 2323 IEM_MC_LOCAL(uint32_t, fEFlags); 2326 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2327 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2328 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2324 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 2325 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 2329 2326 IEM_MC_LOCAL(X86XMMREG, uSrc2); 2330 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);2327 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2); 2331 2328 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2332 2329 … … 2338 2335 IEM_MC_PREPARE_AVX_USAGE(); 2339 2336 IEM_MC_FETCH_EFLAGS(fEFlags); 2340 IEM_MC_REF_MXCSR(pfMxcsr);2341 2337 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2342 IEM_MC_CALL_ VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),2343 pfMxcsr,pEFlags, puSrc1, puSrc2);2338 IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback), 2339 pEFlags, puSrc1, puSrc2); 2344 2340 IEM_MC_IF_MXCSR_XCPT_PENDING() { 2345 2341 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 2372 2368 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx); 2373 2369 IEM_MC_LOCAL(uint32_t, fEFlags); 2374 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2375 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2376 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2377 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 2370 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 2371 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 2372 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2); 2378 2373 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2379 2374 IEM_MC_PREPARE_AVX_USAGE(); 2380 2375 IEM_MC_FETCH_EFLAGS(fEFlags); 2381 IEM_MC_REF_MXCSR(pfMxcsr);2382 2376 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2383 2377 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 2384 IEM_MC_CALL_ VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),2385 pfMxcsr,pEFlags, puSrc1, puSrc2);2378 IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback), 2379 pEFlags, puSrc1, puSrc2); 2386 2380 IEM_MC_IF_MXCSR_XCPT_PENDING() { 2387 2381 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 2400 2394 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 2401 2395 IEM_MC_LOCAL(uint32_t, fEFlags); 2402 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2403 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2404 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2396 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 2397 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 2405 2398 IEM_MC_LOCAL(X86XMMREG, uSrc2); 2406 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);2399 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2); 2407 2400 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2408 2401 … … 2414 2407 IEM_MC_PREPARE_AVX_USAGE(); 2415 2408 IEM_MC_FETCH_EFLAGS(fEFlags); 2416 IEM_MC_REF_MXCSR(pfMxcsr);2417 2409 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2418 IEM_MC_CALL_ VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),2419 pfMxcsr,pEFlags, puSrc1, puSrc2);2410 IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback), 2411 pEFlags, puSrc1, puSrc2); 2420 2412 IEM_MC_IF_MXCSR_XCPT_PENDING() { 2421 2413 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 2451 2443 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx); 2452 2444 IEM_MC_LOCAL(uint32_t, fEFlags); 2453 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2454 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2455 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2456 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 2445 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 2446 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 2447 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2); 2457 2448 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2458 2449 IEM_MC_PREPARE_AVX_USAGE(); 2459 2450 IEM_MC_FETCH_EFLAGS(fEFlags); 2460 IEM_MC_REF_MXCSR(pfMxcsr);2461 2451 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2462 2452 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 2463 IEM_MC_CALL_ VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),2464 pfMxcsr,pEFlags, puSrc1, puSrc2);2453 IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback), 2454 pEFlags, puSrc1, puSrc2); 2465 2455 IEM_MC_IF_MXCSR_XCPT_PENDING() { 2466 2456 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 2479 2469 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 2480 2470 IEM_MC_LOCAL(uint32_t, fEFlags); 2481 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2482 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2483 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2471 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 2472 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 2484 2473 IEM_MC_LOCAL(X86XMMREG, uSrc2); 2485 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);2474 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2); 2486 2475 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2487 2476 … … 2493 2482 IEM_MC_PREPARE_AVX_USAGE(); 2494 2483 IEM_MC_FETCH_EFLAGS(fEFlags); 2495 IEM_MC_REF_MXCSR(pfMxcsr);2496 2484 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2497 IEM_MC_CALL_ VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),2498 pfMxcsr,pEFlags, puSrc1, puSrc2);2485 IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback), 2486 pEFlags, puSrc1, puSrc2); 2499 2487 IEM_MC_IF_MXCSR_XCPT_PENDING() { 2500 2488 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 2527 2515 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx); 2528 2516 IEM_MC_LOCAL(uint32_t, fEFlags); 2529 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2530 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2531 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2532 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 2517 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 2518 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 2519 IEM_MC_ARG(PCX86XMMREG, puSrc2, 2); 2533 2520 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2534 2521 IEM_MC_PREPARE_AVX_USAGE(); 2535 2522 IEM_MC_FETCH_EFLAGS(fEFlags); 2536 IEM_MC_REF_MXCSR(pfMxcsr);2537 2523 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2538 2524 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 2539 IEM_MC_CALL_ VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),2540 pfMxcsr,pEFlags, puSrc1, puSrc2);2525 IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback), 2526 pEFlags, puSrc1, puSrc2); 2541 2527 IEM_MC_IF_MXCSR_XCPT_PENDING() { 2542 2528 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); … … 2555 2541 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 2556 2542 IEM_MC_LOCAL(uint32_t, fEFlags); 2557 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2558 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2559 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2543 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 0); 2544 IEM_MC_ARG(PCX86XMMREG, puSrc1, 1); 2560 2545 IEM_MC_LOCAL(X86XMMREG, uSrc2); 2561 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3);2546 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 2); 2562 2547 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2563 2548 … … 2569 2554 IEM_MC_PREPARE_AVX_USAGE(); 2570 2555 IEM_MC_FETCH_EFLAGS(fEFlags); 2571 IEM_MC_REF_MXCSR(pfMxcsr);2572 2556 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2573 IEM_MC_CALL_ VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),2574 pfMxcsr,pEFlags, puSrc1, puSrc2);2557 IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback), 2558 pEFlags, puSrc1, puSrc2); 2575 2559 IEM_MC_IF_MXCSR_XCPT_PENDING() { 2576 2560 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp
r104099 r104129 1081 1081 #define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() NOP() 1082 1082 1083 #define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) IEM_LIVENESS_MXCSR_MODIFY() //;IEM_LIVENESS_XREG_CLOBBER(a_iXmmReg)1083 #define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) NOP() //IEM_LIVENESS_XREG_CLOBBER(a_iXmmReg) 1084 1084 #define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) IEM_LIVENESS_MXCSR_MODIFY() 1085 1085 … … 1094 1094 #define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) NOP() 1095 1095 #define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) NOP() 1096 #define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) NOP()1097 #define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) NOP()1096 #define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) IEM_LIVENESS_MXCSR_MODIFY() 1097 #define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) IEM_LIVENESS_MXCSR_MODIFY() 1098 1098 #define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a0, a1) NOP() 1099 1099 #define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a0, a1, a2) NOP() 1100 #define IEM_MC_CALL_AVX_AIMPL_NEW_3(a_pfnAImpl, a0, a1, a2) IEM_LIVENESS_MXCSR_MODIFY() 1100 1101 1101 1102 #define IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit) \ -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
r104107 r104129 1150 1150 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR 1151 1151 #define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \ 1152 off = iemNativeEmitSimdMaybeRaiseSseAvxSimdFpOrUdXcpt(pReNative, off )1152 off = iemNativeEmitSimdMaybeRaiseSseAvxSimdFpOrUdXcpt(pReNative, off, pCallEntry->idxInstr) 1153 1153 1154 1154 /** Emits code for IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT. */ 1155 1155 DECL_INLINE_THROW(uint32_t) 1156 iemNativeEmitSimdMaybeRaiseSseAvxSimdFpOrUdXcpt(PIEMRECOMPILERSTATE pReNative, uint32_t off) 1157 { 1156 iemNativeEmitSimdMaybeRaiseSseAvxSimdFpOrUdXcpt(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr) 1157 { 1158 /* 1159 * Make sure we don't have any outstanding guest register writes as we may 1160 * raise an \#UD or \#XF and all guest register must be up to date in CPUMCTX. 1161 */ 1162 off = iemNativeRegFlushPendingWrites(pReNative, off); 1163 1164 #ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING 1165 off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr)); 1166 #else 1167 RT_NOREF(idxInstr); 1168 #endif 1169 1158 1170 uint8_t const idxLabelRaiseSseAvxFpRelated = iemNativeLabelCreate(pReNative, kIemNativeLabelType_RaiseSseAvxFpRelated); 1159 1171 uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ReadOnly); … … 8550 8562 8551 8563 8552 #define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \8553 off = iemNativeEmitSimdSseUpdateMxcsr(pReNative, off, a_fMxcsr)8554 8555 /** Emits code for IEM_MC_SSE_UPDATE_MXCSR. */8556 DECL_INLINE_THROW(uint32_t)8557 iemNativeEmitSimdSseUpdateMxcsr(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxMxCsrVar)8558 {8559 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxMxCsrVar);8560 IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxMxCsrVar, sizeof(uint32_t));8561 8562 uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ForUpdate);8563 uint8_t const idxVarRegMxCsr = iemNativeVarRegisterAcquire(pReNative, idxMxCsrVar, &off, true /*fInitalized*/);8564 uint8_t const idxVarRegTmp = iemNativeRegAllocTmp(pReNative, &off);8565 8566 /** @todo r=aeichner I think it would be safe to spare the temporary register and trash8567 * the variable MXCSR register as it isn't used afterwards in the microcode block anyway.8568 * Needs verification though, so play it safe for now.8569 */8570 /* mov tmp, varmxcsr */8571 off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxVarRegTmp, idxVarRegMxCsr);8572 /* and tmp, X86_MXCSR_XCPT_FLAGS */8573 off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxVarRegTmp, X86_MXCSR_XCPT_FLAGS);8574 /* or mxcsr, tmp */8575 off = iemNativeEmitOrGpr32ByGpr(pReNative, off, idxRegMxCsr, idxVarRegTmp);8576 8577 /* Writeback the MXCSR register value (there is no delayed writeback for such registers at the moment). */8578 off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxRegMxCsr, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.XState.x87.MXCSR));8579 8580 /* Free but don't flush the MXCSR register. */8581 iemNativeRegFreeTmp(pReNative, idxRegMxCsr);8582 iemNativeVarRegisterRelease(pReNative, idxMxCsrVar);8583 iemNativeRegFreeTmp(pReNative, idxVarRegTmp);8584 8585 return off;8586 }8587 8588 8589 8564 #define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \ 8590 8565 off = iemNativeEmitSimdSseStoreResult(pReNative, off, a_SseData, a_iXmmReg) … … 8592 8567 /** Emits code for IEM_MC_STORE_SSE_RESULT. */ 8593 8568 DECL_INLINE_THROW(uint32_t) 8594 iemNativeEmitSimdSseStoreResult(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxSseDataVar, uint8_t iXReg) 8595 { 8596 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxSseDataVar); 8597 IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxSseDataVar, sizeof(IEMSSERESULT)); 8598 8599 /** @todo r=aeichner We probably need to rework this MC statement and the users to make thing more efficient. */ 8600 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 8601 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite); 8602 uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ForUpdate); 8603 uint8_t const idxVarRegResAddr = iemNativeRegAllocTmp(pReNative, &off); 8604 uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off); 8605 8606 off = iemNativeEmitLoadArgGregWithVarAddr(pReNative, off, idxVarRegResAddr, idxSseDataVar, false /*fFlushShadows*/); 8607 8608 /* Update MXCSR. */ 8609 off = iemNativeEmitLoadGprByGprU32(pReNative, off, idxRegTmp, idxVarRegResAddr, RT_UOFFSETOF_DYN(IEMSSERESULT, MXCSR)); 8610 /* tmp &= X86_MXCSR_XCPT_FLAGS. */ 8611 off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_FLAGS); 8612 /* mxcsr |= tmp */ 8613 off = iemNativeEmitOrGpr32ByGpr(pReNative, off, idxRegMxCsr, idxRegTmp); 8614 8615 /* Writeback the MXCSR register value (there is no delayed writeback for such registers at the moment). */ 8616 off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxRegMxCsr, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.XState.x87.MXCSR)); 8569 iemNativeEmitSimdSseStoreResult(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxSseRes, uint8_t iXReg) 8570 { 8571 IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxSseRes); 8572 IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxSseRes, sizeof(X86XMMREG)); 8573 8574 /* The ForUpdate is important as we might end up not writing the result value to the register in case of an unmasked exception. */ 8575 uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg), 8576 kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); 8577 uint8_t const idxVarRegRes = iemNativeVarSimdRegisterAcquire(pReNative, idxSseRes, &off, true /*fInitalized*/); 8578 uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ReadOnly); 8579 uint8_t const idxRegTmp = iemNativeRegAllocTmp(pReNative, &off); 8617 8580 8618 8581 /* Update the value if there is no unmasked exception. */ … … 8631 8594 uint32_t offFixup = off; 8632 8595 off = iemNativeEmitJnzToFixed(pReNative, off, off); 8633 AssertCompileMemberSize(IEMSSERESULT, uResult, sizeof(RTFLOAT128U)); 8634 off = iemNativeEmitLoadVecRegByGprU128(pReNative, off, idxSimdRegDst, idxVarRegResAddr, RT_UOFFSETOF_DYN(IEMSSERESULT, uResult)); 8596 off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, idxSimdRegDst, idxVarRegRes); 8635 8597 iemNativeFixupFixedJump(pReNative, offFixup, off); 8636 8598 8637 8599 /* Free but don't flush the shadowed register. */ 8600 iemNativeVarRegisterRelease(pReNative, idxSseRes); 8638 8601 iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); 8639 8602 iemNativeRegFreeTmp(pReNative, idxRegMxCsr); 8640 iemNativeRegFreeTmp(pReNative, idxVarRegResAddr);8641 8603 iemNativeRegFreeTmp(pReNative, idxRegTmp); 8642 8604 … … 8655 8617 iemNativeEmitCallSseAImplCommon(PIEMRECOMPILERSTATE pReNative, uint32_t off, uintptr_t pfnAImpl, uint8_t cArgs) 8656 8618 { 8619 /* Grab the MXCSR register, it must not be call volatile or we end up freeing it when setting up the call below. */ 8620 uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, 8621 kIemNativeGstRegUse_ForUpdate, true /*fNoVolatileRegs*/); 8622 AssertRelease(!(RT_BIT_32(idxRegMxCsr) & IEMNATIVE_CALL_VOLATILE_GREG_MASK)); 8623 8657 8624 /* 8658 8625 * Need to do the FPU preparation. … … 8663 8630 * Do all the call setup and cleanup. 8664 8631 */ 8665 off = iemNativeEmitCallCommon(pReNative, off, cArgs + IEM_SSE_AIMPL_HIDDEN_ARGS, IEM_SSE_AIMPL_HIDDEN_ARGS );8632 off = iemNativeEmitCallCommon(pReNative, off, cArgs + IEM_SSE_AIMPL_HIDDEN_ARGS, IEM_SSE_AIMPL_HIDDEN_ARGS, false /*fFlushPendingWrites*/); 8666 8633 8667 8634 /* 8668 * Load the XState::x87 pointer.8635 * Load the MXCSR register into the first argument and mask out the current exception flags. 8669 8636 */ 8670 off = iemNativeEmitLeaGprByGstRegRef(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, kIemNativeGstRegRef_X87, 0 /*idxRegInClass*/); 8637 off = iemNativeEmitLoadGprFromGpr32(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, idxRegMxCsr); 8638 off = iemNativeEmitAndGpr32ByImm(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, ~X86_MXCSR_XCPT_FLAGS); 8671 8639 8672 8640 /* … … 8675 8643 off = iemNativeEmitCallImm(pReNative, off, pfnAImpl); 8676 8644 8645 /* 8646 * The updated MXCSR is in the return register. 8647 */ 8648 off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxRegMxCsr, IEMNATIVE_CALL_RET_GREG); 8649 8650 #ifndef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK 8651 /* Writeback the MXCSR register value (there is no delayed writeback for such registers at the moment). */ 8652 off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxRegMxCsr, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.XState.x87.MXCSR)); 8653 #endif 8654 iemNativeRegFreeTmp(pReNative, idxRegMxCsr); 8655 8677 8656 return off; 8678 8657 } -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
r104115 r104129 2640 2640 uint8_t const idxHstReg = pReNative->Core.aidxGstRegShadows[enmGstReg]; 2641 2641 2642 Assert(enmGstReg >= kIemNativeGstReg_GprFirst && enmGstReg <= kIemNativeGstReg_GprLast); 2642 Assert( ( enmGstReg >= kIemNativeGstReg_GprFirst 2643 && enmGstReg <= kIemNativeGstReg_GprLast) 2644 || enmGstReg == kIemNativeGstReg_MxCsr); 2643 2645 Assert( idxHstReg != UINT8_MAX 2644 2646 && pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(enmGstReg)); … … 3324 3326 if ( ( enmIntendedUse == kIemNativeGstRegUse_ForFullWrite 3325 3327 || enmIntendedUse == kIemNativeGstRegUse_ForUpdate) 3326 && enmGstReg >= kIemNativeGstReg_GprFirst3327 && enmGstReg <= kIemNativeGstReg_GprLast3328 )3328 && ( ( enmGstReg >= kIemNativeGstReg_GprFirst 3329 && enmGstReg <= kIemNativeGstReg_GprLast) 3330 || enmGstReg == kIemNativeGstReg_MxCsr)) 3329 3331 { 3330 3332 # ifdef IEMNATIVE_WITH_TB_DEBUG_INFO … … 3356 3358 if ( ( enmIntendedUse == kIemNativeGstRegUse_ForFullWrite 3357 3359 || enmIntendedUse == kIemNativeGstRegUse_ForUpdate) 3358 && enmGstReg >= kIemNativeGstReg_GprFirst3359 && enmGstReg <= kIemNativeGstReg_GprLast3360 )3360 && ( ( enmGstReg >= kIemNativeGstReg_GprFirst 3361 && enmGstReg <= kIemNativeGstReg_GprLast) 3362 || enmGstReg == kIemNativeGstReg_MxCsr)) 3361 3363 { 3362 3364 # ifdef IEMNATIVE_WITH_TB_DEBUG_INFO -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py
r104099 r104129 82 82 'RTUINT128U': ( 128, False, 'RTUINT128U', ), 83 83 'X86XMMREG': ( 128, False, 'X86XMMREG', ), 84 'IEMSSERESULT': ( 128+32, False, 'IEMSSERESULT', ),85 84 'IEMMEDIAF2XMMSRC': ( 256, False, 'IEMMEDIAF2XMMSRC',), 86 85 'RTUINT256U': ( 256, False, 'RTUINT256U', ), … … 1898 1897 'IEM_MC_CALL_AVX_AIMPL_4': '__aimpl_avx', 1899 1898 'IEM_MC_CALL_AVX_AIMPL_5': '__aimpl_avx', 1899 'IEM_MC_CALL_AVX_AIMPL_NEW_3': '__aimpl_avx', 1900 1900 }; 1901 1901 def analyzeAndAnnotateName(self, aoStmts: List[iai.McStmt]): -
trunk/src/VBox/VMM/include/IEMInternal.h
r104115 r104129 5 5 6 6 /* 7 * Copyright (C) 2011-202 3Oracle and/or its affiliates.7 * Copyright (C) 2011-2024 Oracle and/or its affiliates. 8 8 * 9 9 * This file is part of VirtualBox base platform packages, as … … 3850 3850 FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback; 3851 3851 3852 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */3852 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */ 3853 3853 typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64; 3854 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */3854 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */ 3855 3855 typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64; 3856 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */3856 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */ 3857 3857 typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32; 3858 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */3858 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */ 3859 3859 typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32; 3860 3860 … … 3871 3871 FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32; 3872 3872 3873 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));3873 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src)); 3874 3874 typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32; 3875 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));3875 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src)); 3876 3876 typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64; 3877 3877 … … 3879 3879 FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64; 3880 3880 3881 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));3881 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src)); 3882 3882 typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32; 3883 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));3883 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src)); 3884 3884 typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64; 3885 3885 … … 3888 3888 3889 3889 3890 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));3890 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSR128,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)); 3891 3891 typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128; 3892 3892 … … 4247 4247 * @{ */ 4248 4248 /** 4249 * A SSE result.4250 */4251 typedef struct IEMSSERESULT4252 {4253 /** The output value. */4254 X86XMMREG uResult;4255 /** The output status. */4256 uint32_t MXCSR;4257 } IEMSSERESULT;4258 AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);4259 /** Pointer to a SSE result. */4260 typedef IEMSSERESULT *PIEMSSERESULT;4261 /** Pointer to a const SSE result. */4262 typedef IEMSSERESULT const *PCIEMSSERESULT;4263 4264 4265 /**4266 4249 * A AVX128 result. 4267 4250 */ … … 4297 4280 4298 4281 4299 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));4282 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)); 4300 4283 typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128; 4301 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));4284 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2)); 4302 4285 typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32; 4303 typedef IEM_DECL_IMPL_TYPE( void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULTpResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));4286 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2)); 4304 4287 typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64; 4305 4288 … … 5479 5462 /** @name SSE+AVX SIMD access and helpers. 5480 5463 * @{ */ 5481 void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;5482 5464 void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT; 5483 5465 /** @} */ -
trunk/src/VBox/VMM/include/IEMMc.h
r104099 r104129 2960 2960 2961 2961 /** Stores SSE SIMD result updating MXCSR. */ 2962 #define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \ 2963 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg) 2964 /** Updates MXCSR. */ 2965 #define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \ 2966 iemSseUpdateMxcsr(pVCpu, a_fMxcsr) 2962 #define IEM_MC_STORE_SSE_RESULT(a_Res, a_iXmmReg) \ 2963 do { \ 2964 PCX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87; \ 2965 if (( ~((pFpuCtx->MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \ 2966 & (pFpuCtx->MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0) \ 2967 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXmmReg)] = (a_Res); \ 2968 } while (0) 2967 2969 2968 2970 /** Prepares for using the SSE state. … … 3024 3026 do { \ 3025 3027 IEM_MC_PREPARE_SSE_USAGE(); \ 3026 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \ 3028 pVCpu->cpum.GstCtx.XState.x87.MXCSR = a_pfnAImpl(pVCpu->cpum.GstCtx.XState.x87.MXCSR & ~X86_MXCSR_XCPT_FLAGS, \ 3029 (a0), (a1)); \ 3027 3030 } while (0) 3028 3031 … … 3038 3041 do { \ 3039 3042 IEM_MC_PREPARE_SSE_USAGE(); \ 3040 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \ 3043 pVCpu->cpum.GstCtx.XState.x87.MXCSR = a_pfnAImpl(pVCpu->cpum.GstCtx.XState.x87.MXCSR & ~X86_MXCSR_XCPT_FLAGS, \ 3044 (a0), (a1), (a2)); \ 3041 3045 } while (0) 3042 3046 … … 3071 3075 IEM_MC_PREPARE_AVX_USAGE(); \ 3072 3076 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState, (a1), (a2), (a3)); \ 3077 } while (0) 3078 3079 /** 3080 * Calls a AVX assembly implementation taking three visible arguments. 3081 * 3082 * @param a_pfnAImpl Pointer to the assembly SSE routine. 3083 * @param a0 The first extra argument. 3084 * @param a1 The second extra argument. 3085 * @param a2 The third extra argument. 3086 * 3087 * @note The and'ing with X86_MXCSR_XCPT_FLAGS is just a precaution as 3088 * the called helper should return an MXCSR with only new exception flags 3089 * added. 3090 * @note This is temporarily required for the v(u)comis* stuff because 3091 * tstIEMAImpl will not compile otherwise, will be removed once the AVX 3092 * stuff is reworked, see @bugref{10641} 3093 */ 3094 #define IEM_MC_CALL_AVX_AIMPL_NEW_3(a_pfnAImpl, a0, a1, a2) \ 3095 do { \ 3096 IEM_MC_PREPARE_SSE_USAGE(); \ 3097 pVCpu->cpum.GstCtx.XState.x87.MXCSR |= a_pfnAImpl(pVCpu->cpum.GstCtx.XState.x87.MXCSR, (a0), (a1), (a2)) \ 3098 & X86_MXCSR_XCPT_FLAGS; \ 3073 3099 } while (0) 3074 3100 -
trunk/src/VBox/VMM/testcase/tstIEMAImpl.cpp
r104051 r104129 5 5 6 6 /* 7 * Copyright (C) 2022-202 3Oracle and/or its affiliates.7 * Copyright (C) 2022-2024 Oracle and/or its affiliates. 8 8 * 9 9 * This file is part of VirtualBox base platform packages, as … … 5594 5594 }; 5595 5595 5596 X86FXSTATE State;5597 RT_ZERO(State);5598 5596 uint32_t cMinNormalPairs = (cTests - 144) / 4; 5599 5597 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32); iFn++) … … 5635 5633 for (uint8_t iFz = 0; iFz < 2; iFz++) 5636 5634 { 5637 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)5638 | (iRounding << X86_MXCSR_RC_SHIFT)5639 | (iDaz ? X86_MXCSR_DAZ : 0)5640 | (iFz ? X86_MXCSR_FZ : 0)5641 | X86_MXCSR_XCPT_MASK;5642 IEMSSERESULTResM; RT_ZERO(ResM);5643 pfn(&State, &ResM, &TestData.InVal1, &TestData.InVal2);5644 TestData.fMxcsrIn = State.MXCSR;5645 TestData.fMxcsrOut = ResM.MXCSR;5646 TestData.OutVal = ResM .uResult;5635 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 5636 | (iRounding << X86_MXCSR_RC_SHIFT) 5637 | (iDaz ? X86_MXCSR_DAZ : 0) 5638 | (iFz ? X86_MXCSR_FZ : 0) 5639 | X86_MXCSR_XCPT_MASK; 5640 X86XMMREG ResM; RT_ZERO(ResM); 5641 uint32_t uMxCsrOutM = pfn(uMxCsrIn, &ResM, &TestData.InVal1, &TestData.InVal2); 5642 TestData.fMxcsrIn = uMxCsrIn; 5643 TestData.fMxcsrOut = uMxCsrOutM; 5644 TestData.OutVal = ResM; 5647 5645 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 5648 5646 5649 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;5650 IEMSSERESULTResU; RT_ZERO(ResU);5651 pfn(&State, &ResU, &TestData.InVal1, &TestData.InVal2);5652 TestData.fMxcsrIn = State.MXCSR;5653 TestData.fMxcsrOut = ResU.MXCSR;5654 TestData.OutVal = ResU .uResult;5647 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 5648 X86XMMREG ResU; RT_ZERO(ResU); 5649 uint32_t uMxCsrOutU = pfn(uMxCsrIn, &ResU, &TestData.InVal1, &TestData.InVal2); 5650 TestData.fMxcsrIn = uMxCsrIn; 5651 TestData.fMxcsrOut = uMxCsrOutU; 5652 TestData.OutVal = ResU; 5655 5653 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 5656 5654 5657 uint16_t fXcpt = ( ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;5655 uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS; 5658 5656 if (fXcpt) 5659 5657 { 5660 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;5661 IEMSSERESULTRes1; RT_ZERO(Res1);5662 pfn(&State, &Res1, &TestData.InVal1, &TestData.InVal2);5663 TestData.fMxcsrIn = State.MXCSR;5664 TestData.fMxcsrOut = Res1.MXCSR;5665 TestData.OutVal = Res1 .uResult;5658 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 5659 X86XMMREG Res1; RT_ZERO(Res1); 5660 uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &Res1, &TestData.InVal1, &TestData.InVal2); 5661 TestData.fMxcsrIn = uMxCsrIn; 5662 TestData.fMxcsrOut = uMxCsrOut1; 5663 TestData.OutVal = Res1; 5666 5664 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 5667 5665 5668 if ((( Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR& X86_MXCSR_XCPT_FLAGS))5666 if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS)) 5669 5667 { 5670 fXcpt |= Res1.MXCSR& X86_MXCSR_XCPT_FLAGS;5671 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);5672 IEMSSERESULTRes2; RT_ZERO(Res2);5673 pfn(&State, &Res2, &TestData.InVal1, &TestData.InVal2);5674 TestData.fMxcsrIn = State.MXCSR;5675 TestData.fMxcsrOut = Res2.MXCSR;5676 TestData.OutVal = Res2 .uResult;5668 fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS; 5669 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 5670 X86XMMREG Res2; RT_ZERO(Res2); 5671 uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &Res2, &TestData.InVal1, &TestData.InVal2); 5672 TestData.fMxcsrIn = uMxCsrIn; 5673 TestData.fMxcsrOut = uMxCsrOut2; 5674 TestData.OutVal = Res2; 5677 5675 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 5678 5676 } … … 5681 5679 if (fUnmasked & fXcpt) 5682 5680 { 5683 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);5684 IEMSSERESULTRes3; RT_ZERO(Res3);5685 pfn(&State, &Res3, &TestData.InVal1, &TestData.InVal2);5686 TestData.fMxcsrIn = State.MXCSR;5687 TestData.fMxcsrOut = Res3.MXCSR;5688 TestData.OutVal = Res3 .uResult;5681 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 5682 X86XMMREG Res3; RT_ZERO(Res3); 5683 uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &Res3, &TestData.InVal1, &TestData.InVal2); 5684 TestData.fMxcsrIn = uMxCsrIn; 5685 TestData.fMxcsrOut = uMxCsrOut3; 5686 TestData.OutVal = Res3; 5689 5687 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 5690 5688 } … … 5701 5699 static void SseBinaryR32Test(void) 5702 5700 { 5703 X86FXSTATE State;5704 RT_ZERO(State);5705 5701 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32); iFn++) 5706 5702 { … … 5717 5713 for (uint32_t iTest = 0; iTest < cbTests / sizeof(paTests[0]); iTest++) 5718 5714 { 5719 IEMSSERESULT Res; RT_ZERO(Res); 5720 5721 State.MXCSR = paTests[iTest].fMxcsrIn; 5722 pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].InVal2); 5723 bool fValsIdentical = RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[0], &paTests[iTest].OutVal.ar32[0]) 5724 && RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[1], &paTests[iTest].OutVal.ar32[1]) 5725 && RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[2], &paTests[iTest].OutVal.ar32[2]) 5726 && RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]); 5727 if ( Res.MXCSR != paTests[iTest].fMxcsrOut 5715 X86XMMREG Res; RT_ZERO(Res); 5716 5717 uint32_t uMxCsrOut = pfn(paTests[iTest].fMxcsrIn, &Res, &paTests[iTest].InVal1, &paTests[iTest].InVal2); 5718 bool fValsIdentical = RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[0], &paTests[iTest].OutVal.ar32[0]) 5719 && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[1], &paTests[iTest].OutVal.ar32[1]) 5720 && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[2], &paTests[iTest].OutVal.ar32[2]) 5721 && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[3], &paTests[iTest].OutVal.ar32[3]); 5722 if ( uMxCsrOut != paTests[iTest].fMxcsrOut 5728 5723 || !fValsIdentical) 5729 5724 RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s'%s'%s in2=%s'%s'%s'%s\n" … … 5735 5730 FormatR32(&paTests[iTest].InVal2.ar32[0]), FormatR32(&paTests[iTest].InVal2.ar32[1]), 5736 5731 FormatR32(&paTests[iTest].InVal2.ar32[2]), FormatR32(&paTests[iTest].InVal2.ar32[3]), 5737 iVar ? " " : "", Res.MXCSR,5738 FormatR32(&Res. uResult.ar32[0]), FormatR32(&Res.uResult.ar32[1]),5739 FormatR32(&Res. uResult.ar32[2]), FormatR32(&Res.uResult.ar32[3]),5732 iVar ? " " : "", uMxCsrOut, 5733 FormatR32(&Res.ar32[0]), FormatR32(&Res.ar32[1]), 5734 FormatR32(&Res.ar32[2]), FormatR32(&Res.ar32[3]), 5740 5735 iVar ? " " : "", paTests[iTest].fMxcsrOut, 5741 5736 FormatR32(&paTests[iTest].OutVal.ar32[0]), FormatR32(&paTests[iTest].OutVal.ar32[1]), 5742 5737 FormatR32(&paTests[iTest].OutVal.ar32[2]), FormatR32(&paTests[iTest].OutVal.ar32[3]), 5743 MxcsrDiff( Res.MXCSR, paTests[iTest].fMxcsrOut),5738 MxcsrDiff(uMxCsrOut, paTests[iTest].fMxcsrOut), 5744 5739 !fValsIdentical ? " - val" : "", 5745 5740 FormatMxcsr(paTests[iTest].fMxcsrIn) ); … … 5786 5781 }; 5787 5782 5788 X86FXSTATE State;5789 RT_ZERO(State);5790 5783 uint32_t cMinNormalPairs = (cTests - 144) / 4; 5791 5784 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64); iFn++) … … 5820 5813 for (uint8_t iFz = 0; iFz < 2; iFz++) 5821 5814 { 5822 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)5823 | (iRounding << X86_MXCSR_RC_SHIFT)5824 | (iDaz ? X86_MXCSR_DAZ : 0)5825 | (iFz ? X86_MXCSR_FZ : 0)5826 | X86_MXCSR_XCPT_MASK;5827 IEMSSERESULTResM; RT_ZERO(ResM);5828 pfn(&State, &ResM, &TestData.InVal1, &TestData.InVal2);5829 TestData.fMxcsrIn = State.MXCSR;5830 TestData.fMxcsrOut = ResM.MXCSR;5831 TestData.OutVal = ResM .uResult;5815 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 5816 | (iRounding << X86_MXCSR_RC_SHIFT) 5817 | (iDaz ? X86_MXCSR_DAZ : 0) 5818 | (iFz ? X86_MXCSR_FZ : 0) 5819 | X86_MXCSR_XCPT_MASK; 5820 X86XMMREG ResM; RT_ZERO(ResM); 5821 uint32_t uMxCsrOutM = pfn(uMxCsrIn, &ResM, &TestData.InVal1, &TestData.InVal2); 5822 TestData.fMxcsrIn = uMxCsrIn; 5823 TestData.fMxcsrOut = uMxCsrOutM; 5824 TestData.OutVal = ResM; 5832 5825 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 5833 5826 5834 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;5835 IEMSSERESULTResU; RT_ZERO(ResU);5836 pfn(&State, &ResU, &TestData.InVal1, &TestData.InVal2);5837 TestData.fMxcsrIn = State.MXCSR;5838 TestData.fMxcsrOut = ResU.MXCSR;5839 TestData.OutVal = ResU .uResult;5827 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 5828 X86XMMREG ResU; RT_ZERO(ResU); 5829 uint32_t uMxCsrOutU = pfn(uMxCsrIn, &ResU, &TestData.InVal1, &TestData.InVal2); 5830 TestData.fMxcsrIn = uMxCsrIn; 5831 TestData.fMxcsrOut = uMxCsrOutU; 5832 TestData.OutVal = ResU; 5840 5833 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 5841 5834 5842 uint16_t fXcpt = ( ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;5835 uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS; 5843 5836 if (fXcpt) 5844 5837 { 5845 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;5846 IEMSSERESULTRes1; RT_ZERO(Res1);5847 pfn(&State, &Res1, &TestData.InVal1, &TestData.InVal2);5848 TestData.fMxcsrIn = State.MXCSR;5849 TestData.fMxcsrOut = Res1.MXCSR;5850 TestData.OutVal = Res1 .uResult;5838 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 5839 X86XMMREG Res1; RT_ZERO(Res1); 5840 uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &Res1, &TestData.InVal1, &TestData.InVal2); 5841 TestData.fMxcsrIn = uMxCsrIn; 5842 TestData.fMxcsrOut = uMxCsrOut1; 5843 TestData.OutVal = Res1; 5851 5844 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 5852 5845 5853 if ((( Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR& X86_MXCSR_XCPT_FLAGS))5846 if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS)) 5854 5847 { 5855 fXcpt |= Res1.MXCSR& X86_MXCSR_XCPT_FLAGS;5856 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);5857 IEMSSERESULTRes2; RT_ZERO(Res2);5858 pfn(&State, &Res2, &TestData.InVal1, &TestData.InVal2);5859 TestData.fMxcsrIn = State.MXCSR;5860 TestData.fMxcsrOut = Res2.MXCSR;5861 TestData.OutVal = Res2 .uResult;5848 fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS; 5849 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 5850 X86XMMREG Res2; RT_ZERO(Res2); 5851 uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &Res2, &TestData.InVal1, &TestData.InVal2); 5852 TestData.fMxcsrIn = uMxCsrIn; 5853 TestData.fMxcsrOut = uMxCsrOut2; 5854 TestData.OutVal = Res2; 5862 5855 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 5863 5856 } … … 5866 5859 if (fUnmasked & fXcpt) 5867 5860 { 5868 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);5869 IEMSSERESULTRes3; RT_ZERO(Res3);5870 pfn(&State, &Res3, &TestData.InVal1, &TestData.InVal2);5871 TestData.fMxcsrIn = State.MXCSR;5872 TestData.fMxcsrOut = Res3.MXCSR;5873 TestData.OutVal = Res3 .uResult;5861 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 5862 X86XMMREG Res3; RT_ZERO(Res3); 5863 uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &Res3, &TestData.InVal1, &TestData.InVal2); 5864 TestData.fMxcsrIn = uMxCsrIn; 5865 TestData.fMxcsrOut = uMxCsrOut3; 5866 TestData.OutVal = Res3; 5874 5867 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 5875 5868 } … … 5887 5880 static void SseBinaryR64Test(void) 5888 5881 { 5889 X86FXSTATE State;5890 RT_ZERO(State);5891 5882 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64); iFn++) 5892 5883 { … … 5903 5894 for (uint32_t iTest = 0; iTest < cTests; iTest++) 5904 5895 { 5905 IEMSSERESULTRes; RT_ZERO(Res);5906 5907 State.MXCSR= paTests[iTest].fMxcsrIn;5908 pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].InVal2);5909 if ( Res.MXCSR!= paTests[iTest].fMxcsrOut5910 || !RTFLOAT64U_ARE_IDENTICAL(&Res. uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])5911 || !RTFLOAT64U_ARE_IDENTICAL(&Res. uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))5896 X86XMMREG Res; RT_ZERO(Res); 5897 5898 uint32_t uMxCsrIn = paTests[iTest].fMxcsrIn; 5899 uint32_t uMxCsrOut = pfn(uMxCsrIn, &Res, &paTests[iTest].InVal1, &paTests[iTest].InVal2); 5900 if ( uMxCsrOut != paTests[iTest].fMxcsrOut 5901 || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0]) 5902 || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1])) 5912 5903 RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s in2=%s'%s\n" 5913 5904 "%s -> mxcsr=%#08x %s'%s\n" … … 5916 5907 FormatR64(&paTests[iTest].InVal1.ar64[0]), FormatR64(&paTests[iTest].InVal1.ar64[1]), 5917 5908 FormatR64(&paTests[iTest].InVal2.ar64[0]), FormatR64(&paTests[iTest].InVal2.ar64[1]), 5918 iVar ? " " : "", Res.MXCSR,5919 FormatR64(&Res. uResult.ar64[0]), FormatR64(&Res.uResult.ar64[1]),5909 iVar ? " " : "", uMxCsrOut, 5910 FormatR64(&Res.ar64[0]), FormatR64(&Res.ar64[1]), 5920 5911 iVar ? " " : "", paTests[iTest].fMxcsrOut, 5921 5912 FormatR64(&paTests[iTest].OutVal.ar64[0]), FormatR64(&paTests[iTest].OutVal.ar64[1]), 5922 MxcsrDiff( Res.MXCSR, paTests[iTest].fMxcsrOut),5923 ( !RTFLOAT64U_ARE_IDENTICAL(&Res. uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])5924 || !RTFLOAT64U_ARE_IDENTICAL(&Res. uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))5913 MxcsrDiff(uMxCsrOut, paTests[iTest].fMxcsrOut), 5914 ( !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0]) 5915 || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1])) 5925 5916 ? " - val" : "", 5926 5917 FormatMxcsr(paTests[iTest].fMxcsrIn) ); … … 5963 5954 }; 5964 5955 5965 X86FXSTATE State;5966 RT_ZERO(State);5967 5956 uint32_t cMinNormalPairs = (cTests - 144) / 4; 5968 5957 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R32); iFn++) … … 6002 5991 for (uint8_t iFz = 0; iFz < 2; iFz++) 6003 5992 { 6004 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)6005 | (iRounding << X86_MXCSR_RC_SHIFT)6006 | (iDaz ? X86_MXCSR_DAZ : 0)6007 | (iFz ? X86_MXCSR_FZ : 0)6008 | X86_MXCSR_XCPT_MASK;6009 IEMSSERESULTResM; RT_ZERO(ResM);6010 pfn(&State, &ResM, &TestData.InVal1, &TestData.r32Val2);6011 TestData.fMxcsrIn = State.MXCSR;6012 TestData.fMxcsrOut = ResM.MXCSR;6013 TestData.OutVal = ResM .uResult;5993 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 5994 | (iRounding << X86_MXCSR_RC_SHIFT) 5995 | (iDaz ? X86_MXCSR_DAZ : 0) 5996 | (iFz ? X86_MXCSR_FZ : 0) 5997 | X86_MXCSR_XCPT_MASK; 5998 X86XMMREG ResM; RT_ZERO(ResM); 5999 uint32_t uMxCsrOutM = pfn(uMxCsrIn, &ResM, &TestData.InVal1, &TestData.r32Val2); 6000 TestData.fMxcsrIn = uMxCsrIn; 6001 TestData.fMxcsrOut = uMxCsrOutM; 6002 TestData.OutVal = ResM; 6014 6003 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6015 6004 6016 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;6017 IEMSSERESULTResU; RT_ZERO(ResU);6018 pfn(&State, &ResU, &TestData.InVal1, &TestData.r32Val2);6019 TestData.fMxcsrIn = State.MXCSR;6020 TestData.fMxcsrOut = ResU.MXCSR;6021 TestData.OutVal = ResU .uResult;6005 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 6006 X86XMMREG ResU; RT_ZERO(ResU); 6007 uint32_t uMxCsrOutU = pfn(uMxCsrIn, &ResU, &TestData.InVal1, &TestData.r32Val2); 6008 TestData.fMxcsrIn = uMxCsrIn; 6009 TestData.fMxcsrOut = uMxCsrOutU; 6010 TestData.OutVal = ResU; 6022 6011 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6023 6012 6024 uint16_t fXcpt = ( ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;6013 uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS; 6025 6014 if (fXcpt) 6026 6015 { 6027 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;6028 IEMSSERESULTRes1; RT_ZERO(Res1);6029 pfn(&State, &Res1, &TestData.InVal1, &TestData.r32Val2);6030 TestData.fMxcsrIn = State.MXCSR;6031 TestData.fMxcsrOut = Res1.MXCSR;6032 TestData.OutVal = Res1 .uResult;6016 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 6017 X86XMMREG Res1; RT_ZERO(Res1); 6018 uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &Res1, &TestData.InVal1, &TestData.r32Val2); 6019 TestData.fMxcsrIn = uMxCsrIn; 6020 TestData.fMxcsrOut = uMxCsrOut1; 6021 TestData.OutVal = Res1; 6033 6022 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6034 6023 6035 if ((( Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR& X86_MXCSR_XCPT_FLAGS))6024 if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS)) 6036 6025 { 6037 fXcpt |= Res1.MXCSR& X86_MXCSR_XCPT_FLAGS;6038 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);6039 IEMSSERESULTRes2; RT_ZERO(Res2);6040 pfn(&State, &Res2, &TestData.InVal1, &TestData.r32Val2);6041 TestData.fMxcsrIn = State.MXCSR;6042 TestData.fMxcsrOut = Res2.MXCSR;6043 TestData.OutVal = Res2 .uResult;6026 fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS; 6027 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 6028 X86XMMREG Res2; RT_ZERO(Res2); 6029 uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &Res2, &TestData.InVal1, &TestData.r32Val2); 6030 TestData.fMxcsrIn = uMxCsrIn; 6031 TestData.fMxcsrOut = uMxCsrOut2; 6032 TestData.OutVal = Res2; 6044 6033 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6045 6034 } … … 6048 6037 if (fUnmasked & fXcpt) 6049 6038 { 6050 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);6051 IEMSSERESULTRes3; RT_ZERO(Res3);6052 pfn(&State, &Res3, &TestData.InVal1, &TestData.r32Val2);6053 TestData.fMxcsrIn = State.MXCSR;6054 TestData.fMxcsrOut = Res3.MXCSR;6055 TestData.OutVal = Res3 .uResult;6039 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 6040 X86XMMREG Res3; RT_ZERO(Res3); 6041 uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &Res3, &TestData.InVal1, &TestData.r32Val2); 6042 TestData.fMxcsrIn = uMxCsrIn; 6043 TestData.fMxcsrOut = uMxCsrOut3; 6044 TestData.OutVal = Res3; 6056 6045 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6057 6046 } … … 6068 6057 static void SseBinaryU128R32Test(void) 6069 6058 { 6070 X86FXSTATE State;6071 RT_ZERO(State);6072 6059 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R32); iFn++) 6073 6060 { … … 6084 6071 for (uint32_t iTest = 0; iTest < cTests; iTest++) 6085 6072 { 6086 IEMSSERESULTRes; RT_ZERO(Res);6087 6088 State.MXCSR= paTests[iTest].fMxcsrIn;6089 pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].r32Val2);6090 bool fValsIdentical = RTFLOAT32U_ARE_IDENTICAL(&Res. uResult.ar32[0], &paTests[iTest].OutVal.ar32[0])6091 && RTFLOAT32U_ARE_IDENTICAL(&Res. uResult.ar32[1], &paTests[iTest].OutVal.ar32[1])6092 && RTFLOAT32U_ARE_IDENTICAL(&Res. uResult.ar32[2], &paTests[iTest].OutVal.ar32[2])6093 && RTFLOAT32U_ARE_IDENTICAL(&Res. uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]);6094 if ( Res.MXCSR!= paTests[iTest].fMxcsrOut6073 X86XMMREG Res; RT_ZERO(Res); 6074 6075 uint32_t uMxCsrIn = paTests[iTest].fMxcsrIn; 6076 uint32_t uMxCsrOut = pfn(uMxCsrIn, &Res, &paTests[iTest].InVal1, &paTests[iTest].r32Val2); 6077 bool fValsIdentical = RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[0], &paTests[iTest].OutVal.ar32[0]) 6078 && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[1], &paTests[iTest].OutVal.ar32[1]) 6079 && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[2], &paTests[iTest].OutVal.ar32[2]) 6080 && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[3], &paTests[iTest].OutVal.ar32[3]); 6081 if ( uMxCsrOut != paTests[iTest].fMxcsrOut 6095 6082 || !fValsIdentical) 6096 6083 RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s'%s'%s in2=%s\n" … … 6101 6088 FormatR32(&paTests[iTest].InVal1.ar32[2]), FormatR32(&paTests[iTest].InVal1.ar32[3]), 6102 6089 FormatR32(&paTests[iTest].r32Val2), 6103 iVar ? " " : "", Res.MXCSR,6104 FormatR32(&Res. uResult.ar32[0]), FormatR32(&Res.uResult.ar32[1]),6105 FormatR32(&Res. uResult.ar32[2]), FormatR32(&Res.uResult.ar32[3]),6090 iVar ? " " : "", uMxCsrOut, 6091 FormatR32(&Res.ar32[0]), FormatR32(&Res.ar32[1]), 6092 FormatR32(&Res.ar32[2]), FormatR32(&Res.ar32[3]), 6106 6093 iVar ? " " : "", paTests[iTest].fMxcsrOut, 6107 6094 FormatR32(&paTests[iTest].OutVal.ar32[0]), FormatR32(&paTests[iTest].OutVal.ar32[1]), 6108 6095 FormatR32(&paTests[iTest].OutVal.ar32[2]), FormatR32(&paTests[iTest].OutVal.ar32[3]), 6109 MxcsrDiff( Res.MXCSR, paTests[iTest].fMxcsrOut),6096 MxcsrDiff(uMxCsrOut, paTests[iTest].fMxcsrOut), 6110 6097 !fValsIdentical ? " - val" : "", 6111 6098 FormatMxcsr(paTests[iTest].fMxcsrIn) ); … … 6147 6134 }; 6148 6135 6149 X86FXSTATE State;6150 RT_ZERO(State);6151 6136 uint32_t cMinNormalPairs = (cTests - 144) / 4; 6152 6137 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R64); iFn++) … … 6180 6165 for (uint8_t iFz = 0; iFz < 2; iFz++) 6181 6166 { 6182 State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK) 6183 | (iRounding << X86_MXCSR_RC_SHIFT) 6184 | (iDaz ? X86_MXCSR_DAZ : 0) 6185 | (iFz ? X86_MXCSR_FZ : 0) 6186 | X86_MXCSR_XCPT_MASK; 6187 IEMSSERESULT ResM; RT_ZERO(ResM); 6188 pfn(&State, &ResM, &TestData.InVal1, &TestData.r64Val2); 6189 TestData.fMxcsrIn = State.MXCSR; 6190 TestData.fMxcsrOut = ResM.MXCSR; 6191 TestData.OutVal = ResM.uResult; 6167 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 6168 | (iRounding << X86_MXCSR_RC_SHIFT) 6169 | (iDaz ? X86_MXCSR_DAZ : 0) 6170 | (iFz ? X86_MXCSR_FZ : 0) 6171 | X86_MXCSR_XCPT_MASK; 6172 uint32_t uMxCsrOutM = pfn(uMxCsrIn, &TestData.OutVal, &TestData.InVal1, &TestData.r64Val2); 6173 TestData.fMxcsrIn = uMxCsrIn; 6174 TestData.fMxcsrOut = uMxCsrOutM; 6192 6175 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6193 6176 6194 State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK; 6195 IEMSSERESULT ResU; RT_ZERO(ResU); 6196 pfn(&State, &ResU, &TestData.InVal1, &TestData.r64Val2); 6197 TestData.fMxcsrIn = State.MXCSR; 6198 TestData.fMxcsrOut = ResU.MXCSR; 6199 TestData.OutVal = ResU.uResult; 6177 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 6178 uint32_t uMxCsrOutU = pfn(uMxCsrIn, &TestData.OutVal, &TestData.InVal1, &TestData.r64Val2); 6179 TestData.fMxcsrIn = uMxCsrIn; 6180 TestData.fMxcsrOut = uMxCsrOutU; 6200 6181 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6201 6182 6202 uint16_t fXcpt = ( ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;6183 uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS; 6203 6184 if (fXcpt) 6204 6185 { 6205 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt; 6206 IEMSSERESULT Res1; RT_ZERO(Res1); 6207 pfn(&State, &Res1, &TestData.InVal1, &TestData.r64Val2); 6208 TestData.fMxcsrIn = State.MXCSR; 6209 TestData.fMxcsrOut = Res1.MXCSR; 6210 TestData.OutVal = Res1.uResult; 6186 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 6187 uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.InVal1, &TestData.r64Val2); 6188 TestData.fMxcsrIn = uMxCsrIn; 6189 TestData.fMxcsrOut = uMxCsrOut1; 6211 6190 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6212 6191 6213 if ((( Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR& X86_MXCSR_XCPT_FLAGS))6192 if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS)) 6214 6193 { 6215 fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS; 6216 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 6217 IEMSSERESULT Res2; RT_ZERO(Res2); 6218 pfn(&State, &Res2, &TestData.InVal1, &TestData.r64Val2); 6219 TestData.fMxcsrIn = State.MXCSR; 6220 TestData.fMxcsrOut = Res2.MXCSR; 6221 TestData.OutVal = Res2.uResult; 6194 fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS; 6195 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 6196 uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.InVal1, &TestData.r64Val2); 6197 TestData.fMxcsrIn = uMxCsrIn; 6198 TestData.fMxcsrOut = uMxCsrOut2; 6222 6199 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6223 6200 } … … 6226 6203 if (fUnmasked & fXcpt) 6227 6204 { 6228 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 6229 IEMSSERESULT Res3; RT_ZERO(Res3); 6230 pfn(&State, &Res3, &TestData.InVal1, &TestData.r64Val2); 6231 TestData.fMxcsrIn = State.MXCSR; 6232 TestData.fMxcsrOut = Res3.MXCSR; 6233 TestData.OutVal = Res3.uResult; 6205 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 6206 uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.InVal1, &TestData.r64Val2); 6207 TestData.fMxcsrIn = uMxCsrIn; 6208 TestData.fMxcsrOut = uMxCsrOut3; 6234 6209 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6235 6210 } … … 6247 6222 static void SseBinaryU128R64Test(void) 6248 6223 { 6249 X86FXSTATE State;6250 RT_ZERO(State);6251 6224 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R64); iFn++) 6252 6225 { … … 6263 6236 for (uint32_t iTest = 0; iTest < cTests; iTest++) 6264 6237 { 6265 IEMSSERESULTRes; RT_ZERO(Res);6266 6267 State.MXCSR= paTests[iTest].fMxcsrIn;6268 pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].r64Val2);6269 if ( Res.MXCSR!= paTests[iTest].fMxcsrOut6270 || !RTFLOAT64U_ARE_IDENTICAL(&Res. uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])6271 || !RTFLOAT64U_ARE_IDENTICAL(&Res. uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))6238 X86XMMREG Res; RT_ZERO(Res); 6239 6240 uint32_t uMxCsrIn = paTests[iTest].fMxcsrIn; 6241 uint32_t uMxCsrOut = pfn(uMxCsrIn, &Res, &paTests[iTest].InVal1, &paTests[iTest].r64Val2); 6242 if ( uMxCsrOut != paTests[iTest].fMxcsrOut 6243 || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0]) 6244 || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1])) 6272 6245 RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s in2=%s\n" 6273 6246 "%s -> mxcsr=%#08x %s'%s\n" … … 6276 6249 FormatR64(&paTests[iTest].InVal1.ar64[0]), FormatR64(&paTests[iTest].InVal1.ar64[1]), 6277 6250 FormatR64(&paTests[iTest].r64Val2), 6278 iVar ? " " : "", Res.MXCSR,6279 FormatR64(&Res. uResult.ar64[0]), FormatR64(&Res.uResult.ar64[1]),6251 iVar ? " " : "", uMxCsrOut, 6252 FormatR64(&Res.ar64[0]), FormatR64(&Res.ar64[1]), 6280 6253 iVar ? " " : "", paTests[iTest].fMxcsrOut, 6281 6254 FormatR64(&paTests[iTest].OutVal.ar64[0]), FormatR64(&paTests[iTest].OutVal.ar64[1]), 6282 MxcsrDiff( Res.MXCSR, paTests[iTest].fMxcsrOut),6283 ( !RTFLOAT64U_ARE_IDENTICAL(&Res. uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])6284 || !RTFLOAT64U_ARE_IDENTICAL(&Res. uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))6255 MxcsrDiff(uMxCsrOut, paTests[iTest].fMxcsrOut), 6256 ( !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0]) 6257 || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1])) 6285 6258 ? " - val" : "", 6286 6259 FormatMxcsr(paTests[iTest].fMxcsrIn) ); … … 6316 6289 }; 6317 6290 6318 X86FXSTATE State;6319 RT_ZERO(State);6320 6291 uint32_t cMinNormalPairs = (cTests - 144) / 4; 6321 6292 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI32R64); iFn++) … … 6346 6317 for (uint8_t iFz = 0; iFz < 2; iFz++) 6347 6318 { 6348 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)6349 | (iRounding << X86_MXCSR_RC_SHIFT)6350 | (iDaz ? X86_MXCSR_DAZ : 0)6351 | (iFz ? X86_MXCSR_FZ : 0)6352 | X86_MXCSR_XCPT_MASK;6319 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 6320 | (iRounding << X86_MXCSR_RC_SHIFT) 6321 | (iDaz ? X86_MXCSR_DAZ : 0) 6322 | (iFz ? X86_MXCSR_FZ : 0) 6323 | X86_MXCSR_XCPT_MASK; 6353 6324 uint32_t fMxcsrM; int32_t i32OutM; 6354 pfn(&State, &fMxcsrM, &i32OutM, &TestData.r64ValIn.u);6355 TestData.fMxcsrIn = State.MXCSR;6325 fMxcsrM = pfn(uMxCsrIn, &i32OutM, &TestData.r64ValIn.u); 6326 TestData.fMxcsrIn = uMxCsrIn; 6356 6327 TestData.fMxcsrOut = fMxcsrM; 6357 6328 TestData.i32ValOut = i32OutM; 6358 6329 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6359 6330 6360 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;6331 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 6361 6332 uint32_t fMxcsrU; int32_t i32OutU; 6362 pfn(&State, &fMxcsrU, &i32OutU, &TestData.r64ValIn.u);6363 TestData.fMxcsrIn = State.MXCSR;6333 fMxcsrU = pfn(uMxCsrIn, &i32OutU, &TestData.r64ValIn.u); 6334 TestData.fMxcsrIn = uMxCsrIn; 6364 6335 TestData.fMxcsrOut = fMxcsrU; 6365 6336 TestData.i32ValOut = i32OutU; … … 6369 6340 if (fXcpt) 6370 6341 { 6371 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;6342 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 6372 6343 uint32_t fMxcsr1; int32_t i32Out1; 6373 pfn(&State, &fMxcsr1, &i32Out1, &TestData.r64ValIn.u);6374 TestData.fMxcsrIn = State.MXCSR;6344 fMxcsr1 = pfn(uMxCsrIn, &i32Out1, &TestData.r64ValIn.u); 6345 TestData.fMxcsrIn = uMxCsrIn; 6375 6346 TestData.fMxcsrOut = fMxcsr1; 6376 6347 TestData.i32ValOut = i32Out1; … … 6380 6351 { 6381 6352 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS; 6382 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);6353 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 6383 6354 uint32_t fMxcsr2; int32_t i32Out2; 6384 pfn(&State, &fMxcsr2, &i32Out2, &TestData.r64ValIn.u);6385 TestData.fMxcsrIn = State.MXCSR;6355 fMxcsr2 = pfn(uMxCsrIn, &i32Out2, &TestData.r64ValIn.u); 6356 TestData.fMxcsrIn = uMxCsrIn; 6386 6357 TestData.fMxcsrOut = fMxcsr2; 6387 6358 TestData.i32ValOut = i32Out2; … … 6392 6363 if (fUnmasked & fXcpt) 6393 6364 { 6394 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);6365 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 6395 6366 uint32_t fMxcsr3; int32_t i32Out3; 6396 pfn(&State, &fMxcsr3, &i32Out3, &TestData.r64ValIn.u);6397 TestData.fMxcsrIn = State.MXCSR;6367 fMxcsr3 = pfn(uMxCsrIn, &i32Out3, &TestData.r64ValIn.u); 6368 TestData.fMxcsrIn = uMxCsrIn; 6398 6369 TestData.fMxcsrOut = fMxcsr3; 6399 6370 TestData.i32ValOut = i32Out3; … … 6429 6400 for (uint32_t iTest = 0; iTest < cTests; iTest++) 6430 6401 { 6431 uint32_t fMxcsr = 0;6432 6402 int32_t i32Dst = 0; 6433 6403 6434 State.MXCSR = paTests[iTest].fMxcsrIn; 6435 pfn(&State, &fMxcsr, &i32Dst, &paTests[iTest].r64ValIn.u); 6404 uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &i32Dst, &paTests[iTest].r64ValIn.u); 6436 6405 if ( fMxcsr != paTests[iTest].fMxcsrOut 6437 6406 || i32Dst != paTests[iTest].i32ValOut) … … 6478 6447 }; 6479 6448 6480 X86FXSTATE State;6481 RT_ZERO(State);6482 6449 uint32_t cMinNormalPairs = (cTests - 144) / 4; 6483 6450 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI64R64); iFn++) … … 6508 6475 for (uint8_t iFz = 0; iFz < 2; iFz++) 6509 6476 { 6510 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)6511 | (iRounding << X86_MXCSR_RC_SHIFT)6512 | (iDaz ? X86_MXCSR_DAZ : 0)6513 | (iFz ? X86_MXCSR_FZ : 0)6514 | X86_MXCSR_XCPT_MASK;6477 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 6478 | (iRounding << X86_MXCSR_RC_SHIFT) 6479 | (iDaz ? X86_MXCSR_DAZ : 0) 6480 | (iFz ? X86_MXCSR_FZ : 0) 6481 | X86_MXCSR_XCPT_MASK; 6515 6482 uint32_t fMxcsrM; int64_t i64OutM; 6516 pfn(&State, &fMxcsrM, &i64OutM, &TestData.r64ValIn.u);6517 TestData.fMxcsrIn = State.MXCSR;6483 fMxcsrM = pfn(uMxCsrIn, &i64OutM, &TestData.r64ValIn.u); 6484 TestData.fMxcsrIn = uMxCsrIn; 6518 6485 TestData.fMxcsrOut = fMxcsrM; 6519 6486 TestData.i64ValOut = i64OutM; 6520 6487 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6521 6488 6522 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;6489 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 6523 6490 uint32_t fMxcsrU; int64_t i64OutU; 6524 pfn(&State, &fMxcsrU, &i64OutU, &TestData.r64ValIn.u);6525 TestData.fMxcsrIn = State.MXCSR;6491 fMxcsrU =pfn(uMxCsrIn, &i64OutU, &TestData.r64ValIn.u); 6492 TestData.fMxcsrIn = uMxCsrIn; 6526 6493 TestData.fMxcsrOut = fMxcsrU; 6527 6494 TestData.i64ValOut = i64OutU; … … 6531 6498 if (fXcpt) 6532 6499 { 6533 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;6500 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 6534 6501 uint32_t fMxcsr1; int64_t i64Out1; 6535 pfn(&State, &fMxcsr1, &i64Out1, &TestData.r64ValIn.u);6536 TestData.fMxcsrIn = State.MXCSR;6502 fMxcsr1 = pfn(uMxCsrIn, &i64Out1, &TestData.r64ValIn.u); 6503 TestData.fMxcsrIn = uMxCsrIn; 6537 6504 TestData.fMxcsrOut = fMxcsr1; 6538 6505 TestData.i64ValOut = i64Out1; … … 6542 6509 { 6543 6510 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS; 6544 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);6511 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 6545 6512 uint32_t fMxcsr2; int64_t i64Out2; 6546 pfn(&State, &fMxcsr2, &i64Out2, &TestData.r64ValIn.u);6547 TestData.fMxcsrIn = State.MXCSR;6513 fMxcsr2 = pfn(uMxCsrIn, &i64Out2, &TestData.r64ValIn.u); 6514 TestData.fMxcsrIn = uMxCsrIn; 6548 6515 TestData.fMxcsrOut = fMxcsr2; 6549 6516 TestData.i64ValOut = i64Out2; … … 6554 6521 if (fUnmasked & fXcpt) 6555 6522 { 6556 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);6523 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 6557 6524 uint32_t fMxcsr3; int64_t i64Out3; 6558 pfn(&State, &fMxcsr3, &i64Out3, &TestData.r64ValIn.u);6559 TestData.fMxcsrIn = State.MXCSR;6525 fMxcsr3 = pfn(uMxCsrIn, &i64Out3, &TestData.r64ValIn.u); 6526 TestData.fMxcsrIn = uMxCsrIn; 6560 6527 TestData.fMxcsrOut = fMxcsr3; 6561 6528 TestData.i64ValOut = i64Out3; … … 6591 6558 for (uint32_t iTest = 0; iTest < cTests; iTest++) 6592 6559 { 6593 uint32_t fMxcsr = 0;6594 6560 int64_t i64Dst = 0; 6595 6596 State.MXCSR = paTests[iTest].fMxcsrIn; 6597 pfn(&State, &fMxcsr, &i64Dst, &paTests[iTest].r64ValIn.u); 6561 uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &i64Dst, &paTests[iTest].r64ValIn.u); 6598 6562 if ( fMxcsr != paTests[iTest].fMxcsrOut 6599 6563 || i64Dst != paTests[iTest].i64ValOut) … … 6640 6604 }; 6641 6605 6642 X86FXSTATE State;6643 RT_ZERO(State);6644 6606 uint32_t cMinNormalPairs = (cTests - 144) / 4; 6645 6607 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI32R32); iFn++) … … 6670 6632 for (uint8_t iFz = 0; iFz < 2; iFz++) 6671 6633 { 6672 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)6673 | (iRounding << X86_MXCSR_RC_SHIFT)6674 | (iDaz ? X86_MXCSR_DAZ : 0)6675 | (iFz ? X86_MXCSR_FZ : 0)6676 | X86_MXCSR_XCPT_MASK;6634 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 6635 | (iRounding << X86_MXCSR_RC_SHIFT) 6636 | (iDaz ? X86_MXCSR_DAZ : 0) 6637 | (iFz ? X86_MXCSR_FZ : 0) 6638 | X86_MXCSR_XCPT_MASK; 6677 6639 uint32_t fMxcsrM; int32_t i32OutM; 6678 pfn(&State, &fMxcsrM, &i32OutM, &TestData.r32ValIn.u);6679 TestData.fMxcsrIn = State.MXCSR;6640 fMxcsrM = pfn(uMxCsrIn, &i32OutM, &TestData.r32ValIn.u); 6641 TestData.fMxcsrIn = uMxCsrIn; 6680 6642 TestData.fMxcsrOut = fMxcsrM; 6681 6643 TestData.i32ValOut = i32OutM; 6682 6644 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6683 6645 6684 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;6646 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 6685 6647 uint32_t fMxcsrU; int32_t i32OutU; 6686 pfn(&State, &fMxcsrU, &i32OutU, &TestData.r32ValIn.u);6687 TestData.fMxcsrIn = State.MXCSR;6648 fMxcsrU = pfn(uMxCsrIn, &i32OutU, &TestData.r32ValIn.u); 6649 TestData.fMxcsrIn = uMxCsrIn; 6688 6650 TestData.fMxcsrOut = fMxcsrU; 6689 6651 TestData.i32ValOut = i32OutU; … … 6693 6655 if (fXcpt) 6694 6656 { 6695 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;6657 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 6696 6658 uint32_t fMxcsr1; int32_t i32Out1; 6697 pfn(&State, &fMxcsr1, &i32Out1, &TestData.r32ValIn.u);6698 TestData.fMxcsrIn = State.MXCSR;6659 fMxcsr1 = pfn(uMxCsrIn, &i32Out1, &TestData.r32ValIn.u); 6660 TestData.fMxcsrIn = uMxCsrIn; 6699 6661 TestData.fMxcsrOut = fMxcsr1; 6700 6662 TestData.i32ValOut = i32Out1; … … 6704 6666 { 6705 6667 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS; 6706 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);6668 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 6707 6669 uint32_t fMxcsr2; int32_t i32Out2; 6708 pfn(&State, &fMxcsr2, &i32Out2, &TestData.r32ValIn.u);6709 TestData.fMxcsrIn = State.MXCSR;6670 fMxcsr2 = pfn(uMxCsrIn, &i32Out2, &TestData.r32ValIn.u); 6671 TestData.fMxcsrIn = uMxCsrIn; 6710 6672 TestData.fMxcsrOut = fMxcsr2; 6711 6673 TestData.i32ValOut = i32Out2; … … 6716 6678 if (fUnmasked & fXcpt) 6717 6679 { 6718 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);6680 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 6719 6681 uint32_t fMxcsr3; int32_t i32Out3; 6720 pfn(&State, &fMxcsr3, &i32Out3, &TestData.r32ValIn.u);6721 TestData.fMxcsrIn = State.MXCSR;6682 fMxcsr3 = pfn(uMxCsrIn, &i32Out3, &TestData.r32ValIn.u); 6683 TestData.fMxcsrIn = uMxCsrIn; 6722 6684 TestData.fMxcsrOut = fMxcsr3; 6723 6685 TestData.i32ValOut = i32Out3; … … 6753 6715 for (uint32_t iTest = 0; iTest < cTests; iTest++) 6754 6716 { 6755 uint32_t fMxcsr = 0;6756 6717 int32_t i32Dst = 0; 6757 6718 6758 State.MXCSR = paTests[iTest].fMxcsrIn; 6759 pfn(&State, &fMxcsr, &i32Dst, &paTests[iTest].r32ValIn.u); 6719 uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &i32Dst, &paTests[iTest].r32ValIn.u); 6760 6720 if ( fMxcsr != paTests[iTest].fMxcsrOut 6761 6721 || i32Dst != paTests[iTest].i32ValOut) … … 6832 6792 for (uint8_t iFz = 0; iFz < 2; iFz++) 6833 6793 { 6834 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)6835 | (iRounding << X86_MXCSR_RC_SHIFT)6836 | (iDaz ? X86_MXCSR_DAZ : 0)6837 | (iFz ? X86_MXCSR_FZ : 0)6838 | X86_MXCSR_XCPT_MASK;6794 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 6795 | (iRounding << X86_MXCSR_RC_SHIFT) 6796 | (iDaz ? X86_MXCSR_DAZ : 0) 6797 | (iFz ? X86_MXCSR_FZ : 0) 6798 | X86_MXCSR_XCPT_MASK; 6839 6799 uint32_t fMxcsrM; int64_t i64OutM; 6840 pfn(&State, &fMxcsrM, &i64OutM, &TestData.r32ValIn.u);6800 fMxcsrM = pfn(uMxCsrIn, &i64OutM, &TestData.r32ValIn.u); 6841 6801 TestData.fMxcsrIn = State.MXCSR; 6842 6802 TestData.fMxcsrOut = fMxcsrM; … … 6844 6804 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6845 6805 6846 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;6806 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 6847 6807 uint32_t fMxcsrU; int64_t i64OutU; 6848 pfn(&State, &fMxcsrU, &i64OutU, &TestData.r32ValIn.u);6808 fMxcsrU = pfn(uMxCsrIn, &i64OutU, &TestData.r32ValIn.u); 6849 6809 TestData.fMxcsrIn = State.MXCSR; 6850 6810 TestData.fMxcsrOut = fMxcsrU; … … 6855 6815 if (fXcpt) 6856 6816 { 6857 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;6817 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 6858 6818 uint32_t fMxcsr1; int64_t i64Out1; 6859 pfn(&State, &fMxcsr1, &i64Out1, &TestData.r32ValIn.u);6819 fMxcsr1 = pfn(uMxCsrIn, &i64Out1, &TestData.r32ValIn.u); 6860 6820 TestData.fMxcsrIn = State.MXCSR; 6861 6821 TestData.fMxcsrOut = fMxcsr1; … … 6866 6826 { 6867 6827 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS; 6868 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);6828 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 6869 6829 uint32_t fMxcsr2; int64_t i64Out2; 6870 pfn(&State, &fMxcsr2, &i64Out2, &TestData.r32ValIn.u);6830 fMxcsr2 = pfn(uMxCsrIn, &i64Out2, &TestData.r32ValIn.u); 6871 6831 TestData.fMxcsrIn = State.MXCSR; 6872 6832 TestData.fMxcsrOut = fMxcsr2; … … 6878 6838 if (fUnmasked & fXcpt) 6879 6839 { 6880 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);6840 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 6881 6841 uint32_t fMxcsr3; int64_t i64Out3; 6882 pfn(&State, &fMxcsr3, &i64Out3, &TestData.r32ValIn.u);6842 fMxcsr3 = pfn(uMxCsrIn, &i64Out3, &TestData.r32ValIn.u); 6883 6843 TestData.fMxcsrIn = State.MXCSR; 6884 6844 TestData.fMxcsrOut = fMxcsr3; … … 6915 6875 for (uint32_t iTest = 0; iTest < cTests; iTest++) 6916 6876 { 6917 uint32_t fMxcsr = 0;6918 6877 int64_t i64Dst = 0; 6919 6878 6920 State.MXCSR = paTests[iTest].fMxcsrIn; 6921 pfn(&State, &fMxcsr, &i64Dst, &paTests[iTest].r32ValIn.u); 6879 uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &i64Dst, &paTests[iTest].r32ValIn.u); 6922 6880 if ( fMxcsr != paTests[iTest].fMxcsrOut 6923 6881 || i64Dst != paTests[iTest].i64ValOut) … … 6964 6922 }; 6965 6923 6966 X86FXSTATE State;6967 RT_ZERO(State);6968 6924 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I32); iFn++) 6969 6925 { … … 6984 6940 for (uint8_t iFz = 0; iFz < 2; iFz++) 6985 6941 { 6986 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)6987 | (iRounding << X86_MXCSR_RC_SHIFT)6988 | (iDaz ? X86_MXCSR_DAZ : 0)6989 | (iFz ? X86_MXCSR_FZ : 0)6990 | X86_MXCSR_XCPT_MASK;6942 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 6943 | (iRounding << X86_MXCSR_RC_SHIFT) 6944 | (iDaz ? X86_MXCSR_DAZ : 0) 6945 | (iFz ? X86_MXCSR_FZ : 0) 6946 | X86_MXCSR_XCPT_MASK; 6991 6947 uint32_t fMxcsrM; RTFLOAT64U r64OutM; 6992 pfn(&State, &fMxcsrM, &r64OutM, &TestData.i32ValIn);6993 TestData.fMxcsrIn = State.MXCSR;6948 fMxcsrM = pfn(uMxCsrIn, &r64OutM, &TestData.i32ValIn); 6949 TestData.fMxcsrIn = uMxCsrIn; 6994 6950 TestData.fMxcsrOut = fMxcsrM; 6995 6951 TestData.r64ValOut = r64OutM; 6996 6952 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 6997 6953 6998 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;6954 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 6999 6955 uint32_t fMxcsrU; RTFLOAT64U r64OutU; 7000 pfn(&State, &fMxcsrU, &r64OutU, &TestData.i32ValIn);7001 TestData.fMxcsrIn = State.MXCSR;6956 fMxcsrU = pfn(uMxCsrIn, &r64OutU, &TestData.i32ValIn); 6957 TestData.fMxcsrIn = uMxCsrIn; 7002 6958 TestData.fMxcsrOut = fMxcsrU; 7003 6959 TestData.r64ValOut = r64OutU; … … 7007 6963 if (fXcpt) 7008 6964 { 7009 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;6965 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 7010 6966 uint32_t fMxcsr1; RTFLOAT64U r64Out1; 7011 pfn(&State, &fMxcsr1, &r64Out1, &TestData.i32ValIn);7012 TestData.fMxcsrIn = State.MXCSR;6967 fMxcsr1 = pfn(uMxCsrIn, &r64Out1, &TestData.i32ValIn); 6968 TestData.fMxcsrIn = uMxCsrIn; 7013 6969 TestData.fMxcsrOut = fMxcsr1; 7014 6970 TestData.r64ValOut = r64Out1; … … 7018 6974 { 7019 6975 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS; 7020 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);6976 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 7021 6977 uint32_t fMxcsr2; RTFLOAT64U r64Out2; 7022 pfn(&State, &fMxcsr2, &r64Out2, &TestData.i32ValIn);7023 TestData.fMxcsrIn = State.MXCSR;6978 fMxcsr2 = pfn(uMxCsrIn, &r64Out2, &TestData.i32ValIn); 6979 TestData.fMxcsrIn = uMxCsrIn; 7024 6980 TestData.fMxcsrOut = fMxcsr2; 7025 6981 TestData.r64ValOut = r64Out2; … … 7030 6986 if (fUnmasked & fXcpt) 7031 6987 { 7032 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);6988 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 7033 6989 uint32_t fMxcsr3; RTFLOAT64U r64Out3; 7034 pfn(&State, &fMxcsr3, &r64Out3, &TestData.i32ValIn);7035 TestData.fMxcsrIn = State.MXCSR;6990 fMxcsr3 = pfn(uMxCsrIn, &r64Out3, &TestData.i32ValIn); 6991 TestData.fMxcsrIn = uMxCsrIn; 7036 6992 TestData.fMxcsrOut = fMxcsr3; 7037 6993 TestData.r64ValOut = r64Out3; … … 7051 7007 static void SseBinaryR64I32Test(void) 7052 7008 { 7053 X86FXSTATE State;7054 RT_ZERO(State);7055 7009 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I32); iFn++) 7056 7010 { … … 7067 7021 for (uint32_t iTest = 0; iTest < cTests; iTest++) 7068 7022 { 7069 uint32_t fMxcsr = 0;7070 7023 RTFLOAT64U r64Dst; RT_ZERO(r64Dst); 7071 7024 7072 State.MXCSR = paTests[iTest].fMxcsrIn; 7073 pfn(&State, &fMxcsr, &r64Dst, &paTests[iTest].i32ValIn); 7025 uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &r64Dst, &paTests[iTest].i32ValIn); 7074 7026 if ( fMxcsr != paTests[iTest].fMxcsrOut 7075 7027 || !RTFLOAT64U_ARE_IDENTICAL(&r64Dst, &paTests[iTest].r64ValOut)) … … 7116 7068 }; 7117 7069 7118 X86FXSTATE State;7119 RT_ZERO(State);7120 7070 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I64); iFn++) 7121 7071 { … … 7136 7086 for (uint8_t iFz = 0; iFz < 2; iFz++) 7137 7087 { 7138 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)7139 | (iRounding << X86_MXCSR_RC_SHIFT)7140 | (iDaz ? X86_MXCSR_DAZ : 0)7141 | (iFz ? X86_MXCSR_FZ : 0)7142 | X86_MXCSR_XCPT_MASK;7088 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 7089 | (iRounding << X86_MXCSR_RC_SHIFT) 7090 | (iDaz ? X86_MXCSR_DAZ : 0) 7091 | (iFz ? X86_MXCSR_FZ : 0) 7092 | X86_MXCSR_XCPT_MASK; 7143 7093 uint32_t fMxcsrM; RTFLOAT64U r64OutM; 7144 pfn(&State, &fMxcsrM, &r64OutM, &TestData.i64ValIn);7145 TestData.fMxcsrIn = State.MXCSR;7094 fMxcsrM = pfn(uMxCsrIn, &r64OutM, &TestData.i64ValIn); 7095 TestData.fMxcsrIn = uMxCsrIn; 7146 7096 TestData.fMxcsrOut = fMxcsrM; 7147 7097 TestData.r64ValOut = r64OutM; 7148 7098 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 7149 7099 7150 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;7100 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 7151 7101 uint32_t fMxcsrU; RTFLOAT64U r64OutU; 7152 pfn(&State, &fMxcsrU, &r64OutU, &TestData.i64ValIn);7153 TestData.fMxcsrIn = State.MXCSR;7102 fMxcsrU = pfn(uMxCsrIn, &r64OutU, &TestData.i64ValIn); 7103 TestData.fMxcsrIn = uMxCsrIn; 7154 7104 TestData.fMxcsrOut = fMxcsrU; 7155 7105 TestData.r64ValOut = r64OutU; … … 7159 7109 if (fXcpt) 7160 7110 { 7161 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;7111 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 7162 7112 uint32_t fMxcsr1; RTFLOAT64U r64Out1; 7163 pfn(&State, &fMxcsr1, &r64Out1, &TestData.i64ValIn);7164 TestData.fMxcsrIn = State.MXCSR;7113 fMxcsr1 = pfn(uMxCsrIn, &r64Out1, &TestData.i64ValIn); 7114 TestData.fMxcsrIn = uMxCsrIn; 7165 7115 TestData.fMxcsrOut = fMxcsr1; 7166 7116 TestData.r64ValOut = r64Out1; … … 7170 7120 { 7171 7121 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS; 7172 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);7122 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 7173 7123 uint32_t fMxcsr2; RTFLOAT64U r64Out2; 7174 pfn(&State, &fMxcsr2, &r64Out2, &TestData.i64ValIn);7175 TestData.fMxcsrIn = State.MXCSR;7124 fMxcsr2 = pfn(uMxCsrIn, &r64Out2, &TestData.i64ValIn); 7125 TestData.fMxcsrIn = uMxCsrIn; 7176 7126 TestData.fMxcsrOut = fMxcsr2; 7177 7127 TestData.r64ValOut = r64Out2; … … 7182 7132 if (fUnmasked & fXcpt) 7183 7133 { 7184 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);7134 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 7185 7135 uint32_t fMxcsr3; RTFLOAT64U r64Out3; 7186 pfn(&State, &fMxcsr3, &r64Out3, &TestData.i64ValIn);7187 TestData.fMxcsrIn = State.MXCSR;7136 fMxcsr3 = pfn(uMxCsrIn, &r64Out3, &TestData.i64ValIn); 7137 TestData.fMxcsrIn = uMxCsrIn; 7188 7138 TestData.fMxcsrOut = fMxcsr3; 7189 7139 TestData.r64ValOut = r64Out3; … … 7203 7153 static void SseBinaryR64I64Test(void) 7204 7154 { 7205 X86FXSTATE State;7206 RT_ZERO(State);7207 7155 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I64); iFn++) 7208 7156 { … … 7219 7167 for (uint32_t iTest = 0; iTest < cTests; iTest++) 7220 7168 { 7221 uint32_t fMxcsr = 0;7222 7169 RTFLOAT64U r64Dst; RT_ZERO(r64Dst); 7223 7170 7224 State.MXCSR = paTests[iTest].fMxcsrIn; 7225 pfn(&State, &fMxcsr, &r64Dst, &paTests[iTest].i64ValIn); 7171 uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &r64Dst, &paTests[iTest].i64ValIn); 7226 7172 if ( fMxcsr != paTests[iTest].fMxcsrOut 7227 7173 || !RTFLOAT64U_ARE_IDENTICAL(&r64Dst, &paTests[iTest].r64ValOut)) … … 7268 7214 }; 7269 7215 7270 X86FXSTATE State;7271 RT_ZERO(State);7272 7216 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I32); iFn++) 7273 7217 { … … 7288 7232 for (uint8_t iFz = 0; iFz < 2; iFz++) 7289 7233 { 7290 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)7291 | (iRounding << X86_MXCSR_RC_SHIFT)7292 | (iDaz ? X86_MXCSR_DAZ : 0)7293 | (iFz ? X86_MXCSR_FZ : 0)7294 | X86_MXCSR_XCPT_MASK;7234 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 7235 | (iRounding << X86_MXCSR_RC_SHIFT) 7236 | (iDaz ? X86_MXCSR_DAZ : 0) 7237 | (iFz ? X86_MXCSR_FZ : 0) 7238 | X86_MXCSR_XCPT_MASK; 7295 7239 uint32_t fMxcsrM; RTFLOAT32U r32OutM; 7296 pfn(&State, &fMxcsrM, &r32OutM, &TestData.i32ValIn);7297 TestData.fMxcsrIn = State.MXCSR;7240 fMxcsrM = pfn(uMxCsrIn, &r32OutM, &TestData.i32ValIn); 7241 TestData.fMxcsrIn = uMxCsrIn; 7298 7242 TestData.fMxcsrOut = fMxcsrM; 7299 7243 TestData.r32ValOut = r32OutM; 7300 7244 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 7301 7245 7302 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;7246 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 7303 7247 uint32_t fMxcsrU; RTFLOAT32U r32OutU; 7304 pfn(&State, &fMxcsrU, &r32OutU, &TestData.i32ValIn);7305 TestData.fMxcsrIn = State.MXCSR;7248 fMxcsrU = pfn(uMxCsrIn, &r32OutU, &TestData.i32ValIn); 7249 TestData.fMxcsrIn = uMxCsrIn; 7306 7250 TestData.fMxcsrOut = fMxcsrU; 7307 7251 TestData.r32ValOut = r32OutU; … … 7311 7255 if (fXcpt) 7312 7256 { 7313 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;7257 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 7314 7258 uint32_t fMxcsr1; RTFLOAT32U r32Out1; 7315 pfn(&State, &fMxcsr1, &r32Out1, &TestData.i32ValIn);7316 TestData.fMxcsrIn = State.MXCSR;7259 fMxcsr1 = pfn(uMxCsrIn, &r32Out1, &TestData.i32ValIn); 7260 TestData.fMxcsrIn = uMxCsrIn; 7317 7261 TestData.fMxcsrOut = fMxcsr1; 7318 7262 TestData.r32ValOut = r32Out1; … … 7322 7266 { 7323 7267 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS; 7324 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);7268 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 7325 7269 uint32_t fMxcsr2; RTFLOAT32U r32Out2; 7326 pfn(&State, &fMxcsr2, &r32Out2, &TestData.i32ValIn);7327 TestData.fMxcsrIn = State.MXCSR;7270 fMxcsr2 = pfn(uMxCsrIn, &r32Out2, &TestData.i32ValIn); 7271 TestData.fMxcsrIn = uMxCsrIn; 7328 7272 TestData.fMxcsrOut = fMxcsr2; 7329 7273 TestData.r32ValOut = r32Out2; … … 7334 7278 if (fUnmasked & fXcpt) 7335 7279 { 7336 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);7280 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 7337 7281 uint32_t fMxcsr3; RTFLOAT32U r32Out3; 7338 pfn(&State, &fMxcsr3, &r32Out3, &TestData.i32ValIn);7339 TestData.fMxcsrIn = State.MXCSR;7282 fMxcsr3 = pfn(uMxCsrIn, &r32Out3, &TestData.i32ValIn); 7283 TestData.fMxcsrIn = uMxCsrIn; 7340 7284 TestData.fMxcsrOut = fMxcsr3; 7341 7285 TestData.r32ValOut = r32Out3; … … 7355 7299 static void SseBinaryR32I32Test(void) 7356 7300 { 7357 X86FXSTATE State;7358 RT_ZERO(State);7359 7301 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I32); iFn++) 7360 7302 { … … 7371 7313 for (uint32_t iTest = 0; iTest < cTests; iTest++) 7372 7314 { 7373 uint32_t fMxcsr = 0;7374 7315 RTFLOAT32U r32Dst; RT_ZERO(r32Dst); 7375 7316 7376 State.MXCSR = paTests[iTest].fMxcsrIn; 7377 pfn(&State, &fMxcsr, &r32Dst, &paTests[iTest].i32ValIn); 7317 uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &r32Dst, &paTests[iTest].i32ValIn); 7378 7318 if ( fMxcsr != paTests[iTest].fMxcsrOut 7379 7319 || !RTFLOAT32U_ARE_IDENTICAL(&r32Dst, &paTests[iTest].r32ValOut)) … … 7420 7360 }; 7421 7361 7422 X86FXSTATE State;7423 RT_ZERO(State);7424 7362 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I64); iFn++) 7425 7363 { … … 7440 7378 for (uint8_t iFz = 0; iFz < 2; iFz++) 7441 7379 { 7442 State.MXCSR= (fMxcsr & ~X86_MXCSR_RC_MASK)7443 | (iRounding << X86_MXCSR_RC_SHIFT)7444 | (iDaz ? X86_MXCSR_DAZ : 0)7445 | (iFz ? X86_MXCSR_FZ : 0)7446 | X86_MXCSR_XCPT_MASK;7380 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 7381 | (iRounding << X86_MXCSR_RC_SHIFT) 7382 | (iDaz ? X86_MXCSR_DAZ : 0) 7383 | (iFz ? X86_MXCSR_FZ : 0) 7384 | X86_MXCSR_XCPT_MASK; 7447 7385 uint32_t fMxcsrM; RTFLOAT32U r32OutM; 7448 pfn(&State, &fMxcsrM, &r32OutM, &TestData.i64ValIn);7449 TestData.fMxcsrIn = State.MXCSR;7386 fMxcsrM = pfn(uMxCsrIn, &r32OutM, &TestData.i64ValIn); 7387 TestData.fMxcsrIn = uMxCsrIn; 7450 7388 TestData.fMxcsrOut = fMxcsrM; 7451 7389 TestData.r32ValOut = r32OutM; 7452 7390 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 7453 7391 7454 State.MXCSR = State.MXCSR& ~X86_MXCSR_XCPT_MASK;7392 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 7455 7393 uint32_t fMxcsrU; RTFLOAT32U r32OutU; 7456 pfn(&State, &fMxcsrU, &r32OutU, &TestData.i64ValIn);7457 TestData.fMxcsrIn = State.MXCSR;7394 fMxcsrU = pfn(uMxCsrIn, &r32OutU, &TestData.i64ValIn); 7395 TestData.fMxcsrIn = uMxCsrIn; 7458 7396 TestData.fMxcsrOut = fMxcsrU; 7459 7397 TestData.r32ValOut = r32OutU; … … 7463 7401 if (fXcpt) 7464 7402 { 7465 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | fXcpt;7403 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 7466 7404 uint32_t fMxcsr1; RTFLOAT32U r32Out1; 7467 pfn(&State, &fMxcsr1, &r32Out1, &TestData.i64ValIn);7468 TestData.fMxcsrIn = State.MXCSR;7405 fMxcsr1 = pfn(uMxCsrIn, &r32Out1, &TestData.i64ValIn); 7406 TestData.fMxcsrIn = uMxCsrIn; 7469 7407 TestData.fMxcsrOut = fMxcsr1; 7470 7408 TestData.r32ValOut = r32Out1; … … 7474 7412 { 7475 7413 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS; 7476 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);7414 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 7477 7415 uint32_t fMxcsr2; RTFLOAT32U r32Out2; 7478 pfn(&State, &fMxcsr2, &r32Out2, &TestData.i64ValIn);7479 TestData.fMxcsrIn = State.MXCSR;7416 fMxcsr2 = pfn(uMxCsrIn, &r32Out2, &TestData.i64ValIn); 7417 TestData.fMxcsrIn = uMxCsrIn; 7480 7418 TestData.fMxcsrOut = fMxcsr2; 7481 7419 TestData.r32ValOut = r32Out2; … … 7486 7424 if (fUnmasked & fXcpt) 7487 7425 { 7488 State.MXCSR = (State.MXCSR& ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);7426 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 7489 7427 uint32_t fMxcsr3; RTFLOAT32U r32Out3; 7490 pfn(&State, &fMxcsr3, &r32Out3, &TestData.i64ValIn);7491 TestData.fMxcsrIn = State.MXCSR;7428 fMxcsr3 = pfn(uMxCsrIn, &r32Out3, &TestData.i64ValIn); 7429 TestData.fMxcsrIn = uMxCsrIn; 7492 7430 TestData.fMxcsrOut = fMxcsr3; 7493 7431 TestData.r32ValOut = r32Out3; … … 7507 7445 static void SseBinaryR32I64Test(void) 7508 7446 { 7509 X86FXSTATE State;7510 RT_ZERO(State);7511 7447 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I64); iFn++) 7512 7448 { … … 7523 7459 for (uint32_t iTest = 0; iTest < cTests; iTest++) 7524 7460 { 7525 uint32_t fMxcsr = 0;7526 7461 RTFLOAT32U r32Dst; RT_ZERO(r32Dst); 7527 7462 7528 State.MXCSR = paTests[iTest].fMxcsrIn; 7529 pfn(&State, &fMxcsr, &r32Dst, &paTests[iTest].i64ValIn); 7463 uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &r32Dst, &paTests[iTest].i64ValIn); 7530 7464 if ( fMxcsr != paTests[iTest].fMxcsrOut 7531 7465 || !RTFLOAT32U_ARE_IDENTICAL(&r32Dst, &paTests[iTest].r32ValOut)) … … 7624 7558 uint32_t fMxcsrM = fMxcsrIn; 7625 7559 uint32_t fEFlagsM = fEFlags; 7626 pfn(&fMxcsrM, &fEFlagsM, &ValIn1, &ValIn2);7560 fMxcsrM = pfn(fMxcsrIn, &fEFlagsM, &ValIn1, &ValIn2); 7627 7561 TestData.fMxcsrIn = fMxcsrIn; 7628 7562 TestData.fMxcsrOut = fMxcsrM; … … 7634 7568 uint32_t fMxcsrU = fMxcsrIn; 7635 7569 uint32_t fEFlagsU = fEFlags; 7636 pfn(&fMxcsrU, &fEFlagsU, &ValIn1, &ValIn2);7570 fMxcsrU = pfn(fMxcsrIn, &fEFlagsU, &ValIn1, &ValIn2); 7637 7571 TestData.fMxcsrIn = fMxcsrIn; 7638 7572 TestData.fMxcsrOut = fMxcsrU; … … 7647 7581 uint32_t fMxcsr1 = fMxcsrIn; 7648 7582 uint32_t fEFlags1 = fEFlags; 7649 pfn(&fMxcsr1, &fEFlags1, &ValIn1, &ValIn2);7583 fMxcsr1 = pfn(fMxcsrIn, &fEFlags1, &ValIn1, &ValIn2); 7650 7584 TestData.fMxcsrIn = fMxcsrIn; 7651 7585 TestData.fMxcsrOut = fMxcsr1; … … 7660 7594 uint32_t fMxcsr2 = fMxcsrIn; 7661 7595 uint32_t fEFlags2 = fEFlags; 7662 pfn(&fMxcsr2, &fEFlags2, &ValIn1, &ValIn2);7596 fMxcsr2 = pfn(fMxcsrIn, &fEFlags2, &ValIn1, &ValIn2); 7663 7597 TestData.fMxcsrIn = fMxcsrIn; 7664 7598 TestData.fMxcsrOut = fMxcsr2; … … 7674 7608 uint32_t fMxcsr3 = fMxcsrIn; 7675 7609 uint32_t fEFlags3 = fEFlags; 7676 pfn(&fMxcsr3, &fEFlags3, &ValIn1, &ValIn2);7610 fMxcsr3 = pfn(fMxcsrIn, &fEFlags3, &ValIn1, &ValIn2); 7677 7611 TestData.fMxcsrIn = fMxcsrIn; 7678 7612 TestData.fMxcsrOut = fMxcsr3; … … 7712 7646 ValIn1.ar32[0] = paTests[iTest].r32ValIn1; 7713 7647 ValIn2.ar32[0] = paTests[iTest].r32ValIn2; 7714 uint32_t fMxcsr = paTests[iTest].fMxcsrIn;7715 7648 uint32_t fEFlags = paTests[iTest].fEflIn; 7716 pfn(&fMxcsr, &fEFlags, &ValIn1, &ValIn2);7649 uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &fEFlags, &ValIn1, &ValIn2); 7717 7650 if ( fMxcsr != paTests[iTest].fMxcsrOut 7718 7651 || fEFlags != paTests[iTest].fEflOut) … … 7810 7743 uint32_t fMxcsrM = fMxcsrIn; 7811 7744 uint32_t fEFlagsM = fEFlags; 7812 pfn(&fMxcsrM, &fEFlagsM, &ValIn1, &ValIn2);7745 fMxcsrM = pfn(fMxcsrIn, &fEFlagsM, &ValIn1, &ValIn2); 7813 7746 TestData.fMxcsrIn = fMxcsrIn; 7814 7747 TestData.fMxcsrOut = fMxcsrM; … … 7820 7753 uint32_t fMxcsrU = fMxcsrIn; 7821 7754 uint32_t fEFlagsU = fEFlags; 7822 pfn(&fMxcsrU, &fEFlagsU, &ValIn1, &ValIn2);7755 fMxcsrU = pfn(fMxcsrIn, &fEFlagsU, &ValIn1, &ValIn2); 7823 7756 TestData.fMxcsrIn = fMxcsrIn; 7824 7757 TestData.fMxcsrOut = fMxcsrU; … … 7833 7766 uint32_t fMxcsr1 = fMxcsrIn; 7834 7767 uint32_t fEFlags1 = fEFlags; 7835 pfn(&fMxcsr1, &fEFlags1, &ValIn1, &ValIn2);7768 fMxcsr1 = pfn(fMxcsrIn, &fEFlags1, &ValIn1, &ValIn2); 7836 7769 TestData.fMxcsrIn = fMxcsrIn; 7837 7770 TestData.fMxcsrOut = fMxcsr1; … … 7846 7779 uint32_t fMxcsr2 = fMxcsrIn; 7847 7780 uint32_t fEFlags2 = fEFlags; 7848 pfn(&fMxcsr2, &fEFlags2, &ValIn1, &ValIn2);7781 fMxcsr2 = pfn(fMxcsrIn, &fEFlags2, &ValIn1, &ValIn2); 7849 7782 TestData.fMxcsrIn = fMxcsrIn; 7850 7783 TestData.fMxcsrOut = fMxcsr2; … … 7860 7793 uint32_t fMxcsr3 = fMxcsrIn; 7861 7794 uint32_t fEFlags3 = fEFlags; 7862 pfn(&fMxcsr3, &fEFlags3, &ValIn1, &ValIn2);7795 fMxcsr3 = pfn(fMxcsrIn, &fEFlags3, &ValIn1, &ValIn2); 7863 7796 TestData.fMxcsrIn = fMxcsrIn; 7864 7797 TestData.fMxcsrOut = fMxcsr3; … … 7898 7831 ValIn1.ar64[0] = paTests[iTest].r64ValIn1; 7899 7832 ValIn2.ar64[0] = paTests[iTest].r64ValIn2; 7900 uint32_t fMxcsr = paTests[iTest].fMxcsrIn;7901 7833 uint32_t fEFlags = paTests[iTest].fEflIn; 7902 pfn(&fMxcsr, &fEFlags, &ValIn1, &ValIn2);7834 uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &fEFlags, &ValIn1, &ValIn2); 7903 7835 if ( fMxcsr != paTests[iTest].fMxcsrOut 7904 7836 || fEFlags != paTests[iTest].fEflOut) … … 8355 8287 AssertReturn(GENERATE_BINARY_OPEN(&BinOut, papszNameFmts, g_aSseConvertXmmI32R32[iFn]), RTEXITCODE_FAILURE); 8356 8288 8357 X86FXSTATE State;8358 RT_ZERO(State);8359 8289 for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1) 8360 8290 { … … 8371 8301 for (uint8_t iFz = 0; iFz < 2; iFz++) 8372 8302 { 8373 State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK) 8374 | (iRounding << X86_MXCSR_RC_SHIFT) 8375 | (iDaz ? X86_MXCSR_DAZ : 0) 8376 | (iFz ? X86_MXCSR_FZ : 0) 8377 | X86_MXCSR_XCPT_MASK; 8378 IEMSSERESULT ResM; RT_ZERO(ResM); 8379 pfn(&State, &ResM, &ResM.uResult, &TestData.InVal); 8380 TestData.fMxcsrIn = State.MXCSR; 8381 TestData.fMxcsrOut = ResM.MXCSR; 8382 TestData.OutVal = ResM.uResult; 8303 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 8304 | (iRounding << X86_MXCSR_RC_SHIFT) 8305 | (iDaz ? X86_MXCSR_DAZ : 0) 8306 | (iFz ? X86_MXCSR_FZ : 0) 8307 | X86_MXCSR_XCPT_MASK; 8308 uint32_t uMxCsrOutM = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8309 TestData.fMxcsrIn = uMxCsrIn; 8310 TestData.fMxcsrOut = uMxCsrOutM; 8383 8311 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8384 8312 8385 State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK; 8386 IEMSSERESULT ResU; RT_ZERO(ResU); 8387 pfn(&State, &ResU, &ResU.uResult, &TestData.InVal); 8388 TestData.fMxcsrIn = State.MXCSR; 8389 TestData.fMxcsrOut = ResU.MXCSR; 8390 TestData.OutVal = ResU.uResult; 8313 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 8314 uint32_t uMxCsrOutU = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8315 TestData.fMxcsrIn = uMxCsrIn; 8316 TestData.fMxcsrOut = uMxCsrOutU; 8391 8317 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8392 8318 8393 uint16_t fXcpt = ( ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;8319 uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS; 8394 8320 if (fXcpt) 8395 8321 { 8396 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt; 8397 IEMSSERESULT Res1; RT_ZERO(Res1); 8398 pfn(&State, &Res1, &Res1.uResult, &TestData.InVal); 8399 TestData.fMxcsrIn = State.MXCSR; 8400 TestData.fMxcsrOut = Res1.MXCSR; 8401 TestData.OutVal = Res1.uResult; 8322 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 8323 uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8324 TestData.fMxcsrIn = uMxCsrIn; 8325 TestData.fMxcsrOut = uMxCsrOut1; 8402 8326 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8403 8327 8404 if ((( Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR& X86_MXCSR_XCPT_FLAGS))8328 if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS)) 8405 8329 { 8406 fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS; 8407 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 8408 IEMSSERESULT Res2; RT_ZERO(Res2); 8409 pfn(&State, &Res2, &Res2.uResult, &TestData.InVal); 8410 TestData.fMxcsrIn = State.MXCSR; 8411 TestData.fMxcsrOut = Res2.MXCSR; 8412 TestData.OutVal = Res2.uResult; 8330 fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS; 8331 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 8332 uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8333 TestData.fMxcsrIn = uMxCsrIn; 8334 TestData.fMxcsrOut = uMxCsrOut2; 8413 8335 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8414 8336 } … … 8417 8339 if (fUnmasked & fXcpt) 8418 8340 { 8419 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 8420 IEMSSERESULT Res3; RT_ZERO(Res3); 8421 pfn(&State, &Res3, &Res3.uResult, &TestData.InVal); 8422 TestData.fMxcsrIn = State.MXCSR; 8423 TestData.fMxcsrOut = Res3.MXCSR; 8424 TestData.OutVal = Res3.uResult; 8341 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 8342 uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8343 TestData.fMxcsrIn = uMxCsrIn; 8344 TestData.fMxcsrOut = uMxCsrOut3; 8425 8345 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8426 8346 } … … 8437 8357 static void SseConvertXmmI32R32Test(void) 8438 8358 { 8439 X86FXSTATE State;8440 RT_ZERO(State);8441 8442 8359 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmI32R32); iFn++) 8443 8360 { … … 8454 8371 for (uint32_t iTest = 0; iTest < cTests; iTest++) 8455 8372 { 8456 IEMSSERESULT Res; RT_ZERO(Res); 8457 8458 State.MXCSR = paTests[iTest].fMxcsrIn; 8459 pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal); 8460 if ( Res.MXCSR != paTests[iTest].fMxcsrOut 8461 || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[0], &paTests[iTest].OutVal.ar32[0]) 8462 || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[1], &paTests[iTest].OutVal.ar32[1]) 8463 || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[2], &paTests[iTest].OutVal.ar32[2]) 8464 || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[3], &paTests[iTest].OutVal.ar32[3])) 8373 X86XMMREG Res; RT_ZERO(Res); 8374 8375 uint32_t fMxCsr = pfn(paTests[iTest].fMxcsrIn, &Res, &Res, &paTests[iTest].InVal); 8376 if ( fMxCsr != paTests[iTest].fMxcsrOut 8377 || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[0], &paTests[iTest].OutVal.ar32[0]) 8378 || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[1], &paTests[iTest].OutVal.ar32[1]) 8379 || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[2], &paTests[iTest].OutVal.ar32[2]) 8380 || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[3], &paTests[iTest].OutVal.ar32[3])) 8465 8381 RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI32'%RI32'%RI32'%RI32 \n" 8466 8382 "%s -> mxcsr=%#08x %s'%s'%s'%s\n" … … 8469 8385 paTests[iTest].InVal.ai32[0], paTests[iTest].InVal.ai32[1], 8470 8386 paTests[iTest].InVal.ai32[2], paTests[iTest].InVal.ai32[3], 8471 iVar ? " " : "", Res.MXCSR,8472 FormatR32(&Res. uResult.ar32[0]), FormatR32(&Res.uResult.ar32[1]),8473 FormatR32(&Res. uResult.ar32[2]), FormatR32(&Res.uResult.ar32[3]),8387 iVar ? " " : "", fMxCsr, 8388 FormatR32(&Res.ar32[0]), FormatR32(&Res.ar32[1]), 8389 FormatR32(&Res.ar32[2]), FormatR32(&Res.ar32[3]), 8474 8390 iVar ? " " : "", paTests[iTest].fMxcsrOut, 8475 8391 FormatR32(&paTests[iTest].OutVal.ar32[0]), FormatR32(&paTests[iTest].OutVal.ar32[1]), 8476 8392 FormatR32(&paTests[iTest].OutVal.ar32[2]), FormatR32(&paTests[iTest].OutVal.ar32[3]), 8477 MxcsrDiff( Res.MXCSR, paTests[iTest].fMxcsrOut),8478 ( !RTFLOAT32U_ARE_IDENTICAL(&Res. uResult.ar32[0], &paTests[iTest].OutVal.ar32[0])8479 || !RTFLOAT32U_ARE_IDENTICAL(&Res. uResult.ar32[1], &paTests[iTest].OutVal.ar32[1])8480 || !RTFLOAT32U_ARE_IDENTICAL(&Res. uResult.ar32[2], &paTests[iTest].OutVal.ar32[2])8481 || !RTFLOAT32U_ARE_IDENTICAL(&Res. uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]))8393 MxcsrDiff(fMxCsr, paTests[iTest].fMxcsrOut), 8394 ( !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[0], &paTests[iTest].OutVal.ar32[0]) 8395 || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[1], &paTests[iTest].OutVal.ar32[1]) 8396 || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[2], &paTests[iTest].OutVal.ar32[2]) 8397 || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[3], &paTests[iTest].OutVal.ar32[3])) 8482 8398 ? " - val" : "", 8483 8399 FormatMxcsr(paTests[iTest].fMxcsrIn)); … … 8514 8430 }; 8515 8431 8516 X86FXSTATE State;8517 RT_ZERO(State);8518 8432 uint32_t cMinNormalPairs = (cTests - 144) / 4; 8519 8433 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR32I32); iFn++) … … 8550 8464 for (uint8_t iFz = 0; iFz < 2; iFz++) 8551 8465 { 8552 State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK) 8553 | (iRounding << X86_MXCSR_RC_SHIFT) 8554 | (iDaz ? X86_MXCSR_DAZ : 0) 8555 | (iFz ? X86_MXCSR_FZ : 0) 8556 | X86_MXCSR_XCPT_MASK; 8557 IEMSSERESULT ResM; RT_ZERO(ResM); 8558 pfn(&State, &ResM, &ResM.uResult, &TestData.InVal); 8559 TestData.fMxcsrIn = State.MXCSR; 8560 TestData.fMxcsrOut = ResM.MXCSR; 8561 TestData.OutVal = ResM.uResult; 8466 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 8467 | (iRounding << X86_MXCSR_RC_SHIFT) 8468 | (iDaz ? X86_MXCSR_DAZ : 0) 8469 | (iFz ? X86_MXCSR_FZ : 0) 8470 | X86_MXCSR_XCPT_MASK; 8471 uint32_t uMxCsrOutM = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8472 TestData.fMxcsrIn = uMxCsrIn; 8473 TestData.fMxcsrOut = uMxCsrOutM; 8562 8474 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8563 8475 8564 State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK; 8565 IEMSSERESULT ResU; RT_ZERO(ResU); 8566 pfn(&State, &ResU, &ResU.uResult, &TestData.InVal); 8567 TestData.fMxcsrIn = State.MXCSR; 8568 TestData.fMxcsrOut = ResU.MXCSR; 8569 TestData.OutVal = ResU.uResult; 8476 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 8477 uint32_t uMxCsrOutU = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8478 TestData.fMxcsrIn = uMxCsrIn; 8479 TestData.fMxcsrOut = uMxCsrOutU; 8570 8480 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8571 8481 8572 uint16_t fXcpt = ( ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;8482 uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS; 8573 8483 if (fXcpt) 8574 8484 { 8575 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt; 8576 IEMSSERESULT Res1; RT_ZERO(Res1); 8577 pfn(&State, &Res1, &Res1.uResult, &TestData.InVal); 8578 TestData.fMxcsrIn = State.MXCSR; 8579 TestData.fMxcsrOut = Res1.MXCSR; 8580 TestData.OutVal = Res1.uResult; 8485 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 8486 uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8487 TestData.fMxcsrIn = uMxCsrIn; 8488 TestData.fMxcsrOut = uMxCsrOut1; 8581 8489 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8582 8490 8583 if ((( Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR& X86_MXCSR_XCPT_FLAGS))8491 if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS)) 8584 8492 { 8585 fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS; 8586 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 8587 IEMSSERESULT Res2; RT_ZERO(Res2); 8588 pfn(&State, &Res2, &Res2.uResult, &TestData.InVal); 8589 TestData.fMxcsrIn = State.MXCSR; 8590 TestData.fMxcsrOut = Res2.MXCSR; 8591 TestData.OutVal = Res2.uResult; 8493 fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS; 8494 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 8495 uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8496 TestData.fMxcsrIn = uMxCsrIn; 8497 TestData.fMxcsrOut = uMxCsrOut2; 8592 8498 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8593 8499 } … … 8596 8502 if (fUnmasked & fXcpt) 8597 8503 { 8598 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 8599 IEMSSERESULT Res3; RT_ZERO(Res3); 8600 pfn(&State, &Res3, &Res3.uResult, &TestData.InVal); 8601 TestData.fMxcsrIn = State.MXCSR; 8602 TestData.fMxcsrOut = Res3.MXCSR; 8603 TestData.OutVal = Res3.uResult; 8504 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 8505 uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8506 TestData.fMxcsrIn = uMxCsrIn; 8507 TestData.fMxcsrOut = uMxCsrOut3; 8604 8508 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8605 8509 } … … 8616 8520 static void SseConvertXmmR32I32Test(void) 8617 8521 { 8618 X86FXSTATE State;8619 RT_ZERO(State);8620 8621 8522 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR32I32); iFn++) 8622 8523 { … … 8633 8534 for (uint32_t iTest = 0; iTest < cTests; iTest++) 8634 8535 { 8635 IEMSSERESULT Res; RT_ZERO(Res); 8636 8637 State.MXCSR = paTests[iTest].fMxcsrIn; 8638 pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal); 8639 if ( Res.MXCSR != paTests[iTest].fMxcsrOut 8640 || Res.uResult.ai32[0] != paTests[iTest].OutVal.ai32[0] 8641 || Res.uResult.ai32[1] != paTests[iTest].OutVal.ai32[1] 8642 || Res.uResult.ai32[2] != paTests[iTest].OutVal.ai32[2] 8643 || Res.uResult.ai32[3] != paTests[iTest].OutVal.ai32[3]) 8536 X86XMMREG Res; RT_ZERO(Res); 8537 8538 uint32_t fMxCsr = pfn(paTests[iTest].fMxcsrIn, &Res, &Res, &paTests[iTest].InVal); 8539 if ( fMxCsr != paTests[iTest].fMxcsrOut 8540 || Res.ai32[0] != paTests[iTest].OutVal.ai32[0] 8541 || Res.ai32[1] != paTests[iTest].OutVal.ai32[1] 8542 || Res.ai32[2] != paTests[iTest].OutVal.ai32[2] 8543 || Res.ai32[3] != paTests[iTest].OutVal.ai32[3]) 8644 8544 RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s'%s'%s \n" 8645 8545 "%s -> mxcsr=%#08x %RI32'%RI32'%RI32'%RI32\n" … … 8648 8548 FormatR32(&paTests[iTest].InVal.ar32[0]), FormatR32(&paTests[iTest].InVal.ar32[1]), 8649 8549 FormatR32(&paTests[iTest].InVal.ar32[2]), FormatR32(&paTests[iTest].InVal.ar32[3]), 8650 iVar ? " " : "", Res.MXCSR,8651 Res. uResult.ai32[0], Res.uResult.ai32[1],8652 Res. uResult.ai32[2], Res.uResult.ai32[3],8550 iVar ? " " : "", fMxCsr, 8551 Res.ai32[0], Res.ai32[1], 8552 Res.ai32[2], Res.ai32[3], 8653 8553 iVar ? " " : "", paTests[iTest].fMxcsrOut, 8654 8554 paTests[iTest].OutVal.ai32[0], paTests[iTest].OutVal.ai32[1], 8655 8555 paTests[iTest].OutVal.ai32[2], paTests[iTest].OutVal.ai32[3], 8656 MxcsrDiff( Res.MXCSR, paTests[iTest].fMxcsrOut),8657 ( Res. uResult.ai32[0] != paTests[iTest].OutVal.ai32[0]8658 || Res. uResult.ai32[1] != paTests[iTest].OutVal.ai32[1]8659 || Res. uResult.ai32[2] != paTests[iTest].OutVal.ai32[2]8660 || Res. uResult.ai32[3] != paTests[iTest].OutVal.ai32[3])8556 MxcsrDiff(fMxCsr, paTests[iTest].fMxcsrOut), 8557 ( Res.ai32[0] != paTests[iTest].OutVal.ai32[0] 8558 || Res.ai32[1] != paTests[iTest].OutVal.ai32[1] 8559 || Res.ai32[2] != paTests[iTest].OutVal.ai32[2] 8560 || Res.ai32[3] != paTests[iTest].OutVal.ai32[3]) 8661 8561 ? " - val" : "", 8662 8562 FormatMxcsr(paTests[iTest].fMxcsrIn)); … … 8701 8601 AssertReturn(GENERATE_BINARY_OPEN(&BinOut, papszNameFmts, g_aSseConvertXmmI32R64[iFn]), RTEXITCODE_FAILURE); 8702 8602 8703 X86FXSTATE State;8704 RT_ZERO(State);8705 8603 for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1) 8706 8604 { … … 8717 8615 for (uint8_t iFz = 0; iFz < 2; iFz++) 8718 8616 { 8719 State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK) 8720 | (iRounding << X86_MXCSR_RC_SHIFT) 8721 | (iDaz ? X86_MXCSR_DAZ : 0) 8722 | (iFz ? X86_MXCSR_FZ : 0) 8723 | X86_MXCSR_XCPT_MASK; 8724 IEMSSERESULT ResM; RT_ZERO(ResM); 8725 pfn(&State, &ResM, &ResM.uResult, &TestData.InVal); 8726 TestData.fMxcsrIn = State.MXCSR; 8727 TestData.fMxcsrOut = ResM.MXCSR; 8728 TestData.OutVal = ResM.uResult; 8617 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 8618 | (iRounding << X86_MXCSR_RC_SHIFT) 8619 | (iDaz ? X86_MXCSR_DAZ : 0) 8620 | (iFz ? X86_MXCSR_FZ : 0) 8621 | X86_MXCSR_XCPT_MASK; 8622 uint32_t uMxCsrOutM = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8623 TestData.fMxcsrIn = uMxCsrIn; 8624 TestData.fMxcsrOut = uMxCsrOutM; 8729 8625 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8730 8626 8731 State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK; 8732 IEMSSERESULT ResU; RT_ZERO(ResU); 8733 pfn(&State, &ResU, &ResU.uResult, &TestData.InVal); 8734 TestData.fMxcsrIn = State.MXCSR; 8735 TestData.fMxcsrOut = ResU.MXCSR; 8736 TestData.OutVal = ResU.uResult; 8627 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 8628 uint32_t uMxCsrOutU = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8629 TestData.fMxcsrIn = uMxCsrIn; 8630 TestData.fMxcsrOut = uMxCsrOutU; 8737 8631 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8738 8632 8739 uint16_t fXcpt = ( ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;8633 uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS; 8740 8634 if (fXcpt) 8741 8635 { 8742 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt; 8743 IEMSSERESULT Res1; RT_ZERO(Res1); 8744 pfn(&State, &Res1, &Res1.uResult, &TestData.InVal); 8745 TestData.fMxcsrIn = State.MXCSR; 8746 TestData.fMxcsrOut = Res1.MXCSR; 8747 TestData.OutVal = Res1.uResult; 8636 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 8637 uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8638 TestData.fMxcsrIn = uMxCsrIn; 8639 TestData.fMxcsrOut = uMxCsrOut1; 8748 8640 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8749 8641 8750 if ((( Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR& X86_MXCSR_XCPT_FLAGS))8642 if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS)) 8751 8643 { 8752 fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS; 8753 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 8754 IEMSSERESULT Res2; RT_ZERO(Res2); 8755 pfn(&State, &Res2, &Res2.uResult, &TestData.InVal); 8756 TestData.fMxcsrIn = State.MXCSR; 8757 TestData.fMxcsrOut = Res2.MXCSR; 8758 TestData.OutVal = Res2.uResult; 8644 fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS; 8645 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 8646 uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8647 TestData.fMxcsrIn = uMxCsrIn; 8648 TestData.fMxcsrOut = uMxCsrOut2; 8759 8649 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8760 8650 } … … 8763 8653 if (fUnmasked & fXcpt) 8764 8654 { 8765 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 8766 IEMSSERESULT Res3; RT_ZERO(Res3); 8767 pfn(&State, &Res3, &Res3.uResult, &TestData.InVal); 8768 TestData.fMxcsrIn = State.MXCSR; 8769 TestData.fMxcsrOut = Res3.MXCSR; 8770 TestData.OutVal = Res3.uResult; 8655 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 8656 uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8657 TestData.fMxcsrIn = uMxCsrIn; 8658 TestData.fMxcsrOut = uMxCsrOut3; 8771 8659 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8772 8660 } … … 8783 8671 static void SseConvertXmmI32R64Test(void) 8784 8672 { 8785 X86FXSTATE State;8786 RT_ZERO(State);8787 8788 8673 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmI32R64); iFn++) 8789 8674 { … … 8800 8685 for (uint32_t iTest = 0; iTest < cTests; iTest++) 8801 8686 { 8802 IEMSSERESULT Res; RT_ZERO(Res); 8803 8804 State.MXCSR = paTests[iTest].fMxcsrIn; 8805 pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal); 8806 if ( Res.MXCSR != paTests[iTest].fMxcsrOut 8807 || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0]) 8808 || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1])) 8687 X86XMMREG Res; RT_ZERO(Res); 8688 8689 uint32_t fMxCsr = pfn(paTests[iTest].fMxcsrIn, &Res, &Res, &paTests[iTest].InVal); 8690 if ( fMxCsr != paTests[iTest].fMxcsrOut 8691 || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0]) 8692 || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1])) 8809 8693 RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI32'%RI32'%RI32'%RI32 \n" 8810 8694 "%s -> mxcsr=%#08x %s'%s\n" … … 8813 8697 paTests[iTest].InVal.ai32[0], paTests[iTest].InVal.ai32[1], 8814 8698 paTests[iTest].InVal.ai32[2], paTests[iTest].InVal.ai32[3], 8815 iVar ? " " : "", Res.MXCSR,8816 FormatR64(&Res. uResult.ar64[0]), FormatR64(&Res.uResult.ar64[1]),8699 iVar ? " " : "", fMxCsr, 8700 FormatR64(&Res.ar64[0]), FormatR64(&Res.ar64[1]), 8817 8701 iVar ? " " : "", paTests[iTest].fMxcsrOut, 8818 8702 FormatR64(&paTests[iTest].OutVal.ar64[0]), FormatR64(&paTests[iTest].OutVal.ar64[1]), 8819 MxcsrDiff( Res.MXCSR, paTests[iTest].fMxcsrOut),8820 ( !RTFLOAT64U_ARE_IDENTICAL(&Res. uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])8821 || !RTFLOAT64U_ARE_IDENTICAL(&Res. uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))8703 MxcsrDiff(fMxCsr, paTests[iTest].fMxcsrOut), 8704 ( !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0]) 8705 || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1])) 8822 8706 ? " - val" : "", 8823 8707 FormatMxcsr(paTests[iTest].fMxcsrIn)); … … 8854 8738 }; 8855 8739 8856 X86FXSTATE State;8857 RT_ZERO(State);8858 8740 uint32_t cMinNormalPairs = (cTests - 144) / 4; 8859 8741 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR64I32); iFn++) … … 8886 8768 for (uint8_t iFz = 0; iFz < 2; iFz++) 8887 8769 { 8888 State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK) 8889 | (iRounding << X86_MXCSR_RC_SHIFT) 8890 | (iDaz ? X86_MXCSR_DAZ : 0) 8891 | (iFz ? X86_MXCSR_FZ : 0) 8892 | X86_MXCSR_XCPT_MASK; 8893 IEMSSERESULT ResM; RT_ZERO(ResM); 8894 pfn(&State, &ResM, &ResM.uResult, &TestData.InVal); 8895 TestData.fMxcsrIn = State.MXCSR; 8896 TestData.fMxcsrOut = ResM.MXCSR; 8897 TestData.OutVal = ResM.uResult; 8770 uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK) 8771 | (iRounding << X86_MXCSR_RC_SHIFT) 8772 | (iDaz ? X86_MXCSR_DAZ : 0) 8773 | (iFz ? X86_MXCSR_FZ : 0) 8774 | X86_MXCSR_XCPT_MASK; 8775 uint32_t uMxCsrOutM = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8776 TestData.fMxcsrIn = uMxCsrIn; 8777 TestData.fMxcsrOut = uMxCsrOutM; 8898 8778 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8899 8779 8900 State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK; 8901 IEMSSERESULT ResU; RT_ZERO(ResU); 8902 pfn(&State, &ResU, &ResU.uResult, &TestData.InVal); 8903 TestData.fMxcsrIn = State.MXCSR; 8904 TestData.fMxcsrOut = ResU.MXCSR; 8905 TestData.OutVal = ResU.uResult; 8780 uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK; 8781 uint32_t uMxCsrOutU = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8782 TestData.fMxcsrIn = uMxCsrIn; 8783 TestData.fMxcsrOut = uMxCsrOutU; 8906 8784 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8907 8785 8908 uint16_t fXcpt = ( ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;8786 uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS; 8909 8787 if (fXcpt) 8910 8788 { 8911 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt; 8912 IEMSSERESULT Res1; RT_ZERO(Res1); 8913 pfn(&State, &Res1, &Res1.uResult, &TestData.InVal); 8914 TestData.fMxcsrIn = State.MXCSR; 8915 TestData.fMxcsrOut = Res1.MXCSR; 8916 TestData.OutVal = Res1.uResult; 8789 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt; 8790 uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8791 TestData.fMxcsrIn = uMxCsrIn; 8792 TestData.fMxcsrOut = uMxCsrOut1; 8917 8793 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8918 8794 8919 if ((( Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR& X86_MXCSR_XCPT_FLAGS))8795 if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS)) 8920 8796 { 8921 fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS; 8922 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 8923 IEMSSERESULT Res2; RT_ZERO(Res2); 8924 pfn(&State, &Res2, &Res2.uResult, &TestData.InVal); 8925 TestData.fMxcsrIn = State.MXCSR; 8926 TestData.fMxcsrOut = Res2.MXCSR; 8927 TestData.OutVal = Res2.uResult; 8797 fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS; 8798 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT); 8799 uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8800 TestData.fMxcsrIn = uMxCsrIn; 8801 TestData.fMxcsrOut = uMxCsrOut2; 8928 8802 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8929 8803 } … … 8932 8806 if (fUnmasked & fXcpt) 8933 8807 { 8934 State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 8935 IEMSSERESULT Res3; RT_ZERO(Res3); 8936 pfn(&State, &Res3, &Res3.uResult, &TestData.InVal); 8937 TestData.fMxcsrIn = State.MXCSR; 8938 TestData.fMxcsrOut = Res3.MXCSR; 8939 TestData.OutVal = Res3.uResult; 8808 uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT); 8809 uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal); 8810 TestData.fMxcsrIn = uMxCsrIn; 8811 TestData.fMxcsrOut = uMxCsrOut3; 8940 8812 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData)); 8941 8813 } … … 8952 8824 static void SseConvertXmmR64I32Test(void) 8953 8825 { 8954 X86FXSTATE State;8955 RT_ZERO(State);8956 8957 8826 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR64I32); iFn++) 8958 8827 { … … 8969 8838 for (uint32_t iTest = 0; iTest < cTests; iTest++) 8970 8839 { 8971 IEMSSERESULT Res; RT_ZERO(Res); 8972 8973 State.MXCSR = paTests[iTest].fMxcsrIn; 8974 pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal); 8975 if ( Res.MXCSR != paTests[iTest].fMxcsrOut 8976 || Res.uResult.ai32[0] != paTests[iTest].OutVal.ai32[0] 8977 || Res.uResult.ai32[1] != paTests[iTest].OutVal.ai32[1] 8978 || Res.uResult.ai32[2] != paTests[iTest].OutVal.ai32[2] 8979 || Res.uResult.ai32[3] != paTests[iTest].OutVal.ai32[3]) 8840 X86XMMREG Res; RT_ZERO(Res); 8841 8842 uint32_t fMxCsr = pfn(paTests[iTest].fMxcsrIn, &Res, &Res, &paTests[iTest].InVal); 8843 if ( fMxCsr != paTests[iTest].fMxcsrOut 8844 || Res.ai32[0] != paTests[iTest].OutVal.ai32[0] 8845 || Res.ai32[1] != paTests[iTest].OutVal.ai32[1] 8846 || Res.ai32[2] != paTests[iTest].OutVal.ai32[2] 8847 || Res.ai32[3] != paTests[iTest].OutVal.ai32[3]) 8980 8848 RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s \n" 8981 8849 "%s -> mxcsr=%#08x %RI32'%RI32'%RI32'%RI32\n" … … 8983 8851 iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn, 8984 8852 FormatR64(&paTests[iTest].InVal.ar64[0]), FormatR64(&paTests[iTest].InVal.ar64[1]), 8985 iVar ? " " : "", Res.MXCSR,8986 Res. uResult.ai32[0], Res.uResult.ai32[1],8987 Res. uResult.ai32[2], Res.uResult.ai32[3],8853 iVar ? " " : "", fMxCsr, 8854 Res.ai32[0], Res.ai32[1], 8855 Res.ai32[2], Res.ai32[3], 8988 8856 iVar ? " " : "", paTests[iTest].fMxcsrOut, 8989 8857 paTests[iTest].OutVal.ai32[0], paTests[iTest].OutVal.ai32[1], 8990 8858 paTests[iTest].OutVal.ai32[2], paTests[iTest].OutVal.ai32[3], 8991 MxcsrDiff( Res.MXCSR, paTests[iTest].fMxcsrOut),8992 ( Res. uResult.ai32[0] != paTests[iTest].OutVal.ai32[0]8993 || Res. uResult.ai32[1] != paTests[iTest].OutVal.ai32[1]8994 || Res. uResult.ai32[2] != paTests[iTest].OutVal.ai32[2]8995 || Res. uResult.ai32[3] != paTests[iTest].OutVal.ai32[3])8859 MxcsrDiff(fMxCsr, paTests[iTest].fMxcsrOut), 8860 ( Res.ai32[0] != paTests[iTest].OutVal.ai32[0] 8861 || Res.ai32[1] != paTests[iTest].OutVal.ai32[1] 8862 || Res.ai32[2] != paTests[iTest].OutVal.ai32[2] 8863 || Res.ai32[3] != paTests[iTest].OutVal.ai32[3]) 8996 8864 ? " - val" : "", 8997 8865 FormatMxcsr(paTests[iTest].fMxcsrIn)); … … 9131 8999 static void SseConvertMmXmmTest(void) 9132 9000 { 9133 X86FXSTATE State;9134 RT_ZERO(State);9135 9136 9001 for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertMmXmm); iFn++) 9137 9002 { -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r104099 r104129 1078 1078 #define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ 1079 1079 do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0) 1080 #define IEM_MC_CALL_AVX_AIMPL_NEW_3(a_pfnAImpl, a0, a1, a2) \ 1081 do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0) 1080 1082 #define IEM_MC_CALL_AVX_AIMPL_4(a_pfnAImpl, a0, a1, a2, a3) \ 1081 1083 do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0)
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