Index: trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 104128)
+++ trunk/src/VBox/VMM/VMMAll/IEMAll.cpp	(revision 104129)
@@ -5483,41 +5483,4 @@
 }
 
-/** @}  */
-
-
-/** @name   SSE+AVX SIMD access and helpers.
- *
- * @{
- */
-/**
- * Stores a result in a SIMD XMM register, updates the MXCSR.
- *
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   pResult             The result to store.
- * @param   iXmmReg             Which SIMD XMM register to store the result in.
- */
-void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT
-{
-    PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
-    pFpuCtx->MXCSR |= pResult->MXCSR & X86_MXCSR_XCPT_FLAGS;
-
-    /* The result is only updated if there is no unmasked exception pending. */
-    if ((  ~((pFpuCtx->MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT)
-         & (pFpuCtx->MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0)
-        pVCpu->cpum.GstCtx.XState.x87.aXMM[iXmmReg] = pResult->uResult;
-}
-
-
-/**
- * Updates the MXCSR.
- *
- * @param   pVCpu               The cross context virtual CPU structure of the calling thread.
- * @param   fMxcsr              The new MXCSR value.
- */
-void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT
-{
-    PX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87;
-    pFpuCtx->MXCSR |= fMxcsr & X86_MXCSR_XCPT_FLAGS;
-}
 /** @}  */
 
Index: trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm	(revision 104128)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm	(revision 104129)
@@ -5,5 +5,5 @@
 
 ;
-; Copyright (C) 2011-2023 Oracle and/or its affiliates.
+; Copyright (C) 2011-2024 Oracle and/or its affiliates.
 ;
 ; This file is part of VirtualBox base platform packages, as
@@ -184,4 +184,13 @@
  %define T2_16      r10w
  %define T2_8       r10b
+
+ ;
+ ; Return value, same as T0 but to make it more obvious
+ ; that this is a return value.
+ ;
+ %define R0         rax
+ %define R0_32      eax
+ %define R0_16      ax
+ %define R0_8       al
 
 %else
@@ -4810,13 +4819,4 @@
 ; Need to move this as well somewhere better?
 ;
-struc IEMSSERESULT
-    .uResult      resd 4
-    .MXCSR        resd 1
-endstruc
-
-
-;;
-; Need to move this as well somewhere better?
-;
 struc IEMAVX128RESULT
     .uResult      resd 4
@@ -4836,14 +4836,14 @@
 ;;
 ; Initialize the SSE MXCSR register using the guest value partially to
-; account for rounding mode.
+; account for rounding mode, load the value from the given register.
 ;
 ; @uses     4 bytes of stack to save the original value, T0.
-; @param    1       Expression giving the address of the FXSTATE of the guest.
-;
-%macro SSE_LD_FXSTATE_MXCSR 1
+; @param    1       Expression giving the register holding the guest's MXCSR.
+;
+%macro SSE_LD_MXCSR 1
         sub     xSP, 4
 
         stmxcsr [xSP]
-        mov     T0_32, [%1 + X86FXSTATE.MXCSR]
+        mov     T0_32, %1
         and     T0_32, X86_MXCSR_FZ | X86_MXCSR_RC_MASK | X86_MXCSR_DAZ
         or      T0_32, X86_MXCSR_XCPT_MASK
@@ -4859,19 +4859,17 @@
 ;
 ; @uses     4 bytes of stack to save the content of MXCSR value, T0, T1.
-; @param    1       Expression giving the address where to return the MXCSR value.
-; @param    2       Expression giving the address of the FXSTATE of the guest.
+; @param    1       Expression giving the register to return the new guest's MXCSR value.
+; @param    2       Expression giving the register holding original guest's MXCSR value.
 ;
 ; @note Restores the stack pointer.
 ;
-%macro SSE_ST_FXSTATE_MXCSR 2
+%macro SSE_ST_MXCSR 2
         sub     xSP, 4
         stmxcsr [xSP]
-        mov     T0_32, [xSP]
+        mov     %1, [xSP]
         add     xSP, 4
         ; Merge the status bits into the original MXCSR value.
-        mov     T1_32, [%2 + X86FXSTATE.MXCSR]
-        and     T0_32, X86_MXCSR_XCPT_FLAGS
-        or      T0_32, T1_32
-        mov     [%1 + IEMSSERESULT.MXCSR], T0_32
+        and     %1, X86_MXCSR_XCPT_FLAGS
+        or      %1, %2
 
         ldmxcsr [xSP]
@@ -4936,6 +4934,7 @@
 ; @param    2       Flag whether the AVX variant of the instruction takes two or three operands, 0 to disable AVX variants
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the result including the MXCSR value.
+; @returns  R0_32   The new MXCSR value of the guest.
+; @param    A0      The guest's MXCSR register value to use.
+; @param    A1      Where to return the result.
 ; @param    A2      Pointer to the first media register size operand (input/output).
 ; @param    A3      Pointer to the second media register size operand (input).
@@ -4945,12 +4944,12 @@
         PROLOGUE_4_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
+        SSE_LD_MXCSR A0_32
 
         movdqu   xmm0, [A2]
         movdqu   xmm1, [A3]
         %1       xmm0, xmm1
-        movdqu   [A1 + IEMSSERESULT.uResult], xmm0
-
-        SSE_ST_FXSTATE_MXCSR A1, A0
+        movdqu   [A1], xmm0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_PROLOGUE
         EPILOGUE_4_ARGS
@@ -5062,6 +5061,7 @@
 ; @param    1       The instruction
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the result including the MXCSR value.
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0      The guest's MXCSR register value to use.
+; @param    A1      Where to return the result.
 ; @param    A2      Pointer to the first media register size operand (input/output).
 ; @param    A3      Pointer to the second single precision floating point value (input).
@@ -5071,12 +5071,12 @@
         PROLOGUE_4_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
+        SSE_LD_MXCSR A0_32
 
         movdqu   xmm0, [A2]
         movd     xmm1, [A3]
         %1       xmm0, xmm1
-        movdqu   [A1 + IEMSSERESULT.uResult], xmm0
-
-        SSE_ST_FXSTATE_MXCSR A1, A0
+        movdqu   [A1], xmm0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
         EPILOGUE_4_ARGS
@@ -5116,6 +5116,7 @@
 ; @param    1       The instruction
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the result including the MXCSR value.
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0      The guest's MXCSR register value to use.
+; @param    A1      Where to return the result.
 ; @param    A2      Pointer to the first media register size operand (input/output).
 ; @param    A3      Pointer to the second double precision floating point value (input).
@@ -5125,12 +5126,12 @@
         PROLOGUE_4_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
+        SSE_LD_MXCSR A0_32
 
         movdqu   xmm0, [A2]
         movq     xmm1, [A3]
         %1       xmm0, xmm1
-        movdqu   [A1 + IEMSSERESULT.uResult], xmm0
-
-        SSE_ST_FXSTATE_MXCSR A1, A0
+        movdqu   [A1], xmm0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
         EPILOGUE_4_ARGS
@@ -5169,6 +5170,7 @@
 ;           2       Whether the AVX256 result is 128-bit (0) or 256-bit (1).
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the result including the MXCSR value.
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Where to return the result.
 ; @param    A2      Pointer to the first media register size operand (input/output).
 ; @param    A3      Pointer to the second media register size operand (input).
@@ -5178,12 +5180,12 @@
         PROLOGUE_4_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
+        SSE_LD_MXCSR A0_32
 
         movdqu   xmm0, [A2]
         movdqu   xmm1, [A3]
         %1       xmm0, xmm1
-        movdqu   [A1 + IEMSSERESULT.uResult], xmm0
-
-        SSE_ST_FXSTATE_MXCSR A1, A0
+        movdqu   [A1], xmm0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
         EPILOGUE_4_ARGS
@@ -5978,45 +5980,20 @@
 
 ;;
-; Restores the SSE MXCSR register with the original value.
-;
-; @uses     4 bytes of stack to save the content of MXCSR value, T0, T1.
-; @param    1       Expression giving the address where to return the MXCSR value - only the MXCSR is stored, no IEMSSERESULT is used.
-; @param    2       Expression giving the address of the FXSTATE of the guest.
-;
-; @note Restores the stack pointer.
-;
-%macro SSE_ST_FXSTATE_MXCSR_ONLY 2
-        sub     xSP, 4
-        stmxcsr [xSP]
-        mov     T0_32, [xSP]
-        add     xSP, 4
-        ; Merge the status bits into the original MXCSR value.
-        mov     T1_32, [%2 + X86FXSTATE.MXCSR]
-        and     T0_32, X86_MXCSR_XCPT_FLAGS
-        or      T0_32, T1_32
-        mov     [%1], T0_32
-
-        ldmxcsr [xSP]
-        add     xSP, 4
-%endmacro
-
-
-;;
 ; cvttsd2si instruction - 32-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvttsd2si_i32_r64, 16
         PROLOGUE_4_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvttsd2si T0_32, [A3]
-        mov       dword [A2], T0_32
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvttsd2si T0_32, [A2]
+        mov       dword [A1], T0_32
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
         EPILOGUE_4_ARGS
@@ -6026,20 +6003,20 @@
 ; cvttsd2si instruction - 64-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvttsd2si_i64_r64, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvttsd2si T0, [A3]
-        mov       qword [A2], T0
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvttsd2si T0, [A2]
+        mov       qword [A1], T0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvttsd2si_i64_r64
 
@@ -6048,20 +6025,20 @@
 ; cvtsd2si instruction - 32-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvtsd2si_i32_r64, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvtsd2si  T0_32, [A3]
-        mov       dword [A2], T0_32
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvtsd2si  T0_32, [A2]
+        mov       dword [A1], T0_32
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvtsd2si_i32_r64
 
@@ -6069,20 +6046,20 @@
 ; cvtsd2si instruction - 64-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvtsd2si_i64_r64, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvtsd2si  T0, [A3]
-        mov       qword [A2], T0
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvtsd2si  T0, [A2]
+        mov       qword [A1], T0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvtsd2si_i64_r64
 
@@ -6091,20 +6068,20 @@
 ; cvttss2si instruction - 32-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvttss2si_i32_r32, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvttss2si T0_32, [A3]
-        mov       dword [A2], T0_32
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvttss2si T0_32, [A2]
+        mov       dword [A1], T0_32
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvttss2si_i32_r32
 
@@ -6112,20 +6089,20 @@
 ; cvttss2si instruction - 64-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvttss2si_i64_r32, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvttss2si T0, [A3]
-        mov       qword [A2], T0
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvttss2si T0, [A2]
+        mov       qword [A1], T0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvttss2si_i64_r32
 
@@ -6134,20 +6111,20 @@
 ; cvtss2si instruction - 32-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvtss2si_i32_r32, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvtss2si  T0_32, [A3]
-        mov       dword [A2], T0_32
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvtss2si  T0_32, [A2]
+        mov       dword [A1], T0_32
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvtss2si_i32_r32
 
@@ -6155,20 +6132,20 @@
 ; cvtss2si instruction - 64-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvtss2si_i64_r32, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvtss2si  T0, [A3]
-        mov       qword [A2], T0
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvtss2si  T0, [A2]
+        mov       qword [A1], T0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvtss2si_i64_r32
 
@@ -6177,20 +6154,20 @@
 ; cvtsi2ss instruction - 32-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvtsi2ss_r32_i32, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvtsi2ss  xmm0, dword [A3]
-        movd      dword [A2], xmm0
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvtsi2ss  xmm0, dword [A2]
+        movd      dword [A1], xmm0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvtsi2ss_r32_i32
 
@@ -6198,20 +6175,20 @@
 ; cvtsi2ss instruction - 64-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvtsi2ss_r32_i64, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvtsi2ss  xmm0, qword [A3]
-        movd      dword [A2], xmm0
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvtsi2ss  xmm0, qword [A2]
+        movd      dword [A1], xmm0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvtsi2ss_r32_i64
 
@@ -6220,20 +6197,20 @@
 ; cvtsi2sd instruction - 32-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvtsi2sd_r64_i32, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvtsi2sd  xmm0, dword [A3]
-        movq      [A2], xmm0
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvtsi2sd  xmm0, dword [A2]
+        movq      [A1], xmm0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvtsi2sd_r64_i32
 
@@ -6241,21 +6218,180 @@
 ; cvtsi2sd instruction - 64-bit variant.
 ;
-; @param    A0      FPU context (FXSTATE or XSAVEAREA).
-; @param    A1      Where to return the MXCSR value.
-; @param    A2      Pointer to the result operand (output).
-; @param    A3      Pointer to the second operand (input).
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use.
+; @param    A1      Pointer to the result operand (output).
+; @param    A2      Pointer to the second operand (input).
 ;
 BEGINPROC_FASTCALL iemAImpl_cvtsi2sd_r64_i64, 16
-        PROLOGUE_4_ARGS
+        PROLOGUE_3_ARGS
         IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR A0
-
-        cvtsi2sd  xmm0, qword [A3]
-        movq      [A2], xmm0
-
-        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        SSE_LD_MXCSR A0_32
+
+        cvtsi2sd  xmm0, qword [A2]
+        movq      [A1], xmm0
+
+        SSE_ST_MXCSR R0_32, A0_32
         IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
+        EPILOGUE_3_ARGS
 ENDPROC iemAImpl_cvtsi2sd_r64_i64
+
+
+;
+; UCOMISS (SSE)
+;
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use (input).
+; @param    A1      Pointer to the EFLAGS value (input/output).
+; @param    A2      Pointer to the first source operand (aka readonly destination).
+; @param    A3      Pointer to the second source operand.
+;
+BEGINPROC_FASTCALL  iemAImpl_ucomiss_u128, 16
+        PROLOGUE_4_ARGS
+        IEMIMPL_SSE_PROLOGUE
+        SSE_LD_MXCSR A0_32
+
+        movdqu  xmm0, [A2]
+        movdqu  xmm1, [A3]
+        ucomiss xmm0, xmm1
+        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+
+        SSE_ST_MXCSR R0_32, A0_32
+        IEMIMPL_SSE_EPILOGUE
+        EPILOGUE_4_ARGS
+ENDPROC             iemAImpl_ucomiss_u128
+
+BEGINPROC_FASTCALL  iemAImpl_vucomiss_u128, 16
+        PROLOGUE_4_ARGS
+        IEMIMPL_SSE_PROLOGUE
+        SSE_LD_MXCSR A0_32
+
+        movdqu  xmm0, [A2]
+        movdqu  xmm1, [A3]
+        vucomiss xmm0, xmm1
+        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+
+        SSE_ST_MXCSR R0_32, A0_32
+        IEMIMPL_SSE_EPILOGUE
+        EPILOGUE_3_ARGS
+ENDPROC             iemAImpl_vucomiss_u128
+
+
+;
+; UCOMISD (SSE)
+;
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use (input).
+; @param    A1      Pointer to the EFLAGS value (input/output).
+; @param    A2      Pointer to the first source operand (aka readonly destination).
+; @param    A3      Pointer to the second source operand.
+;
+BEGINPROC_FASTCALL  iemAImpl_ucomisd_u128, 16
+        PROLOGUE_4_ARGS
+        IEMIMPL_SSE_PROLOGUE
+        SSE_LD_MXCSR A0_32
+
+        movdqu  xmm0, [A2]
+        movdqu  xmm1, [A3]
+        ucomisd xmm0, xmm1
+        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+
+        SSE_ST_MXCSR R0_32, A0_32
+        IEMIMPL_SSE_EPILOGUE
+        EPILOGUE_4_ARGS
+ENDPROC             iemAImpl_ucomisd_u128
+
+BEGINPROC_FASTCALL  iemAImpl_vucomisd_u128, 16
+        PROLOGUE_4_ARGS
+        IEMIMPL_SSE_PROLOGUE
+        SSE_LD_MXCSR A0_32
+
+        movdqu  xmm0, [A2]
+        movdqu  xmm1, [A3]
+        vucomisd xmm0, xmm1
+        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+
+        SSE_ST_MXCSR R0_32, A0_32
+        IEMIMPL_SSE_EPILOGUE
+        EPILOGUE_4_ARGS
+ENDPROC             iemAImpl_vucomisd_u128
+
+;
+; COMISS (SSE)
+;
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use (input).
+; @param    A1      Pointer to the EFLAGS value (input/output).
+; @param    A2      Pointer to the first source operand (aka readonly destination).
+; @param    A3      Pointer to the second source operand.
+;
+BEGINPROC_FASTCALL  iemAImpl_comiss_u128, 16
+        PROLOGUE_4_ARGS
+        IEMIMPL_SSE_PROLOGUE
+        SSE_LD_MXCSR A0_32
+
+        movdqu  xmm0, [A2]
+        movdqu  xmm1, [A3]
+        comiss xmm0, xmm1
+        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+
+        SSE_ST_MXCSR R0_32, A0_32
+        IEMIMPL_SSE_EPILOGUE
+        EPILOGUE_4_ARGS
+ENDPROC             iemAImpl_comiss_u128
+
+BEGINPROC_FASTCALL  iemAImpl_vcomiss_u128, 16
+        PROLOGUE_4_ARGS
+        IEMIMPL_SSE_PROLOGUE
+        SSE_LD_MXCSR A0_32
+
+        movdqu  xmm0, [A2]
+        movdqu  xmm1, [A3]
+        vcomiss xmm0, xmm1
+        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+
+        SSE_ST_MXCSR R0_32, A0_32
+        IEMIMPL_SSE_EPILOGUE
+        EPILOGUE_4_ARGS
+ENDPROC             iemAImpl_vcomiss_u128
+
+
+;
+; COMISD (SSE)
+;
+; @return   R0_32   The new MXCSR value of the guest.
+; @param    A0_32   The guest's MXCSR register value to use (input).
+; @param    A1      Pointer to the EFLAGS value (input/output).
+; @param    A2      Pointer to the first source operand (aka readonly destination).
+; @param    A3      Pointer to the second source operand.
+;
+BEGINPROC_FASTCALL  iemAImpl_comisd_u128, 16
+        PROLOGUE_4_ARGS
+        IEMIMPL_SSE_PROLOGUE
+        SSE_LD_MXCSR A0_32
+
+        movdqu  xmm0, [A2]
+        movdqu  xmm1, [A3]
+        comisd xmm0, xmm1
+        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+
+        SSE_ST_MXCSR R0_32, A0_32
+        IEMIMPL_SSE_EPILOGUE
+        EPILOGUE_4_ARGS
+ENDPROC             iemAImpl_comisd_u128
+
+BEGINPROC_FASTCALL  iemAImpl_vcomisd_u128, 16
+        PROLOGUE_4_ARGS
+        IEMIMPL_SSE_PROLOGUE
+        SSE_LD_MXCSR A0_32
+
+        movdqu  xmm0, [A2]
+        movdqu  xmm1, [A3]
+        vcomisd xmm0, xmm1
+        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+
+        SSE_ST_MXCSR R0_32, A0_32
+        IEMIMPL_SSE_EPILOGUE
+        EPILOGUE_4_ARGS
+ENDPROC             iemAImpl_vcomisd_u128
 
 
@@ -6303,159 +6439,4 @@
         add     xSP, 4
 %endmacro
-
-
-;
-; UCOMISS (SSE)
-;
-; @param    A0      Pointer to the MXCSR value (input/output).
-; @param    A1      Pointer to the EFLAGS value (input/output).
-; @param    A2      Pointer to the first source operand (aka readonly destination).
-; @param    A3      Pointer to the second source operand.
-;
-BEGINPROC_FASTCALL  iemAImpl_ucomiss_u128, 16
-        PROLOGUE_4_ARGS
-        IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR_ONLY A0
-
-        movdqu  xmm0, [A2]
-        movdqu  xmm1, [A3]
-        ucomiss xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
-
-        SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0
-        IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
-ENDPROC             iemAImpl_ucomiss_u128
-
-BEGINPROC_FASTCALL  iemAImpl_vucomiss_u128, 16
-        PROLOGUE_4_ARGS
-        IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR_ONLY A0
-
-        movdqu  xmm0, [A2]
-        movdqu  xmm1, [A3]
-        vucomiss xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
-
-        SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0
-        IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
-ENDPROC             iemAImpl_vucomiss_u128
-
-
-;
-; UCOMISD (SSE)
-;
-; @param    A0      Pointer to the MXCSR value (input/output).
-; @param    A1      Pointer to the EFLAGS value (input/output).
-; @param    A2      Pointer to the first source operand (aka readonly destination).
-; @param    A3      Pointer to the second source operand.
-;
-BEGINPROC_FASTCALL  iemAImpl_ucomisd_u128, 16
-        PROLOGUE_4_ARGS
-        IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR_ONLY A0
-
-        movdqu  xmm0, [A2]
-        movdqu  xmm1, [A3]
-        ucomisd xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
-
-        SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0
-        IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
-ENDPROC             iemAImpl_ucomisd_u128
-
-BEGINPROC_FASTCALL  iemAImpl_vucomisd_u128, 16
-        PROLOGUE_4_ARGS
-        IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR_ONLY A0
-
-        movdqu  xmm0, [A2]
-        movdqu  xmm1, [A3]
-        vucomisd xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
-
-        SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0
-        IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
-ENDPROC             iemAImpl_vucomisd_u128
-
-;
-; COMISS (SSE)
-;
-; @param    A0      Pointer to the MXCSR value (input/output).
-; @param    A1      Pointer to the EFLAGS value (input/output).
-; @param    A2      Pointer to the first source operand (aka readonly destination).
-; @param    A3      Pointer to the second source operand.
-;
-BEGINPROC_FASTCALL  iemAImpl_comiss_u128, 16
-        PROLOGUE_4_ARGS
-        IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR_ONLY A0
-
-        movdqu  xmm0, [A2]
-        movdqu  xmm1, [A3]
-        comiss xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
-
-        SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0
-        IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
-ENDPROC             iemAImpl_comiss_u128
-
-BEGINPROC_FASTCALL  iemAImpl_vcomiss_u128, 16
-        PROLOGUE_4_ARGS
-        IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR_ONLY A0
-
-        movdqu  xmm0, [A2]
-        movdqu  xmm1, [A3]
-        vcomiss xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
-
-        SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0
-        IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
-ENDPROC             iemAImpl_vcomiss_u128
-
-
-;
-; COMISD (SSE)
-;
-; @param    A0      Pointer to the MXCSR value (input/output).
-; @param    A1      Pointer to the EFLAGS value (input/output).
-; @param    A2      Pointer to the first source operand (aka readonly destination).
-; @param    A3      Pointer to the second source operand.
-;
-BEGINPROC_FASTCALL  iemAImpl_comisd_u128, 16
-        PROLOGUE_4_ARGS
-        IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR_ONLY A0
-
-        movdqu  xmm0, [A2]
-        movdqu  xmm1, [A3]
-        comisd xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
-
-        SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0
-        IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
-ENDPROC             iemAImpl_comisd_u128
-
-BEGINPROC_FASTCALL  iemAImpl_vcomisd_u128, 16
-        PROLOGUE_4_ARGS
-        IEMIMPL_SSE_PROLOGUE
-        SSE_LD_FXSTATE_MXCSR_ONLY A0
-
-        movdqu  xmm0, [A2]
-        movdqu  xmm1, [A3]
-        vcomisd xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
-
-        SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0
-        IEMIMPL_SSE_EPILOGUE
-        EPILOGUE_4_ARGS
-ENDPROC             iemAImpl_vcomisd_u128
 
 
@@ -6846,2 +6827,3 @@
 IEMIMPL_ADX_32 adox, X86_EFL_OF
 IEMIMPL_ADX_64 adox, X86_EFL_OF
+
Index: trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp	(revision 104128)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp	(revision 104129)
@@ -5,5 +5,5 @@
 
 /*
- * Copyright (C) 2011-2023 Oracle and/or its affiliates.
+ * Copyright (C) 2011-2024 Oracle and/or its affiliates.
  *
  * This file is part of VirtualBox base platform packages, as
@@ -15828,10 +15828,10 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_addps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_addps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_addps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0])
+           | iemAImpl_addps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1])
+           | iemAImpl_addps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2])
+           | iemAImpl_addps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]);
 }
 #endif
@@ -15842,10 +15842,10 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_addss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
-{
-    pResult->MXCSR = iemAImpl_addps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);
-    pResult->uResult.ar32[1] = puSrc1->ar32[1];
-    pResult->uResult.ar32[2] = puSrc1->ar32[2];
-    pResult->uResult.ar32[3] = puSrc1->ar32[3];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
+{
+    pResult->ar32[1] = puSrc1->ar32[1];
+    pResult->ar32[2] = puSrc1->ar32[2];
+    pResult->ar32[3] = puSrc1->ar32[3];
+    return iemAImpl_addps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2);
 }
 #endif
@@ -15870,8 +15870,8 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_addpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_addpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0])
+           | iemAImpl_addpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]);
 }
 #endif
@@ -15882,8 +15882,8 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_addsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
-{
-    pResult->MXCSR = iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);
-    pResult->uResult.ar64[1] = puSrc1->ar64[1];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
+{
+    pResult->ar64[1] = puSrc1->ar64[1];
+    return iemAImpl_addpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2);
 }
 #endif
@@ -15908,10 +15908,10 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_mulps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_mulps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_mulps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0])
+           | iemAImpl_mulps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1])
+           | iemAImpl_mulps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2])
+           | iemAImpl_mulps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]);
 }
 #endif
@@ -15922,10 +15922,10 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_mulss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
-{
-    pResult->MXCSR = iemAImpl_mulps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);
-    pResult->uResult.ar32[1] = puSrc1->ar32[1];
-    pResult->uResult.ar32[2] = puSrc1->ar32[2];
-    pResult->uResult.ar32[3] = puSrc1->ar32[3];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_mulss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
+{
+    pResult->ar32[1] = puSrc1->ar32[1];
+    pResult->ar32[2] = puSrc1->ar32[2];
+    pResult->ar32[3] = puSrc1->ar32[3];
+    return iemAImpl_mulps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2);
 }
 #endif
@@ -15950,8 +15950,8 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_mulpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_mulpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_mulpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_mulpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_mulpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0])
+           | iemAImpl_mulpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]);
 }
 #endif
@@ -15962,8 +15962,8 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_mulsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
-{
-    pResult->MXCSR = iemAImpl_mulpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);
-    pResult->uResult.ar64[1] = puSrc1->ar64[1];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_mulsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
+{
+    pResult->ar64[1] = puSrc1->ar64[1];
+    return iemAImpl_mulpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2);
 }
 #endif
@@ -15988,10 +15988,10 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_subps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_subps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_subps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_subps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0])
+           | iemAImpl_subps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1])
+           | iemAImpl_subps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2])
+           | iemAImpl_subps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]);
 }
 #endif
@@ -16002,10 +16002,10 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_subss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
-{
-    pResult->MXCSR = iemAImpl_subps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);
-    pResult->uResult.ar32[1] = puSrc1->ar32[1];
-    pResult->uResult.ar32[2] = puSrc1->ar32[2];
-    pResult->uResult.ar32[3] = puSrc1->ar32[3];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_subss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
+{
+    pResult->ar32[1] = puSrc1->ar32[1];
+    pResult->ar32[2] = puSrc1->ar32[2];
+    pResult->ar32[3] = puSrc1->ar32[3];
+    return iemAImpl_subps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2);
 }
 #endif
@@ -16030,8 +16030,8 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_subpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_subpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_subpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0])
+           | iemAImpl_subpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]);
 }
 #endif
@@ -16042,8 +16042,8 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_subsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
-{
-    pResult->MXCSR = iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);
-    pResult->uResult.ar64[1] = puSrc1->ar64[1];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_subsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
+{
+    pResult->ar64[1] = puSrc1->ar64[1];
+    return iemAImpl_subpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2);
 }
 #endif
@@ -16082,10 +16082,10 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_minps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_minps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_minps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_minps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_minps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_minps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_minps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0])
+           | iemAImpl_minps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1])
+           | iemAImpl_minps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2])
+           | iemAImpl_minps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]);
 }
 #endif
@@ -16096,10 +16096,10 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_minss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
-{
-    pResult->MXCSR = iemAImpl_minps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);
-    pResult->uResult.ar32[1] = puSrc1->ar32[1];
-    pResult->uResult.ar32[2] = puSrc1->ar32[2];
-    pResult->uResult.ar32[3] = puSrc1->ar32[3];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_minss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
+{
+    pResult->ar32[1] = puSrc1->ar32[1];
+    pResult->ar32[2] = puSrc1->ar32[2];
+    pResult->ar32[3] = puSrc1->ar32[3];
+    return iemAImpl_minps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2);
 }
 #endif
@@ -16138,8 +16138,8 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_minpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_minpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_minpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_minpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_minpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0])
+           | iemAImpl_minpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]);
 }
 #endif
@@ -16150,8 +16150,8 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_minsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
-{
-    pResult->MXCSR = iemAImpl_minpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);
-    pResult->uResult.ar64[1] = puSrc1->ar64[1];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_minsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
+{
+    pResult->ar64[1] = puSrc1->ar64[1];
+    return iemAImpl_minpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2);
 }
 #endif
@@ -16196,10 +16196,10 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_divps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_divps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_divps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_divps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_divps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_divps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_divps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0])
+           | iemAImpl_divps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1])
+           | iemAImpl_divps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2])
+           | iemAImpl_divps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]);
 }
 #endif
@@ -16210,10 +16210,10 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_divss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
-{
-    pResult->MXCSR = iemAImpl_divps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);
-    pResult->uResult.ar32[1] = puSrc1->ar32[1];
-    pResult->uResult.ar32[2] = puSrc1->ar32[2];
-    pResult->uResult.ar32[3] = puSrc1->ar32[3];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_divss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
+{
+    pResult->ar32[1] = puSrc1->ar32[1];
+    pResult->ar32[2] = puSrc1->ar32[2];
+    pResult->ar32[3] = puSrc1->ar32[3];
+    return iemAImpl_divps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2);
 }
 #endif
@@ -16258,8 +16258,8 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_divpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_divpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_divpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_divpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_divpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0])
+           | iemAImpl_divpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]);
 }
 #endif
@@ -16270,8 +16270,8 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_divsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
-{
-    pResult->MXCSR = iemAImpl_divpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);
-    pResult->uResult.ar64[1] = puSrc1->ar64[1];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_divsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
+{
+    pResult->ar64[1] = puSrc1->ar64[1];
+    return iemAImpl_divpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2);
 }
 #endif
@@ -16310,10 +16310,10 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_maxps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_maxps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_maxps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_maxps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_maxps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_maxps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_maxps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0])
+           | iemAImpl_maxps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1])
+           | iemAImpl_maxps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2])
+           | iemAImpl_maxps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]);
 }
 #endif
@@ -16324,10 +16324,10 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_maxss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
-{
-    pResult->MXCSR = iemAImpl_maxps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], pr32Src2);
-    pResult->uResult.ar32[1] = puSrc1->ar32[1];
-    pResult->uResult.ar32[2] = puSrc1->ar32[2];
-    pResult->uResult.ar32[3] = puSrc1->ar32[3];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_maxss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
+{
+    pResult->ar32[1] = puSrc1->ar32[1];
+    pResult->ar32[2] = puSrc1->ar32[2];
+    pResult->ar32[3] = puSrc1->ar32[3];
+    return iemAImpl_maxps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], pr32Src2);
 }
 #endif
@@ -16366,8 +16366,8 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_maxpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_maxpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_maxpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_maxpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_maxpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0])
+           | iemAImpl_maxpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]);
 }
 #endif
@@ -16378,8 +16378,8 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_maxsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
-{
-    pResult->MXCSR = iemAImpl_maxpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], pr64Src2);
-    pResult->uResult.ar64[1] = puSrc1->ar64[1];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_maxsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
+{
+    pResult->ar64[1] = puSrc1->ar64[1];
+    return iemAImpl_maxpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], pr64Src2);
 }
 #endif
@@ -16401,8 +16401,8 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtss2sd_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
-{
-    pResult->MXCSR = iemAImpl_cvtss2sd_u128_r32_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, pr32Src2);
-    pResult->uResult.ar64[1] = puSrc1->ar64[1];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtss2sd_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
+{
+    pResult->ar64[1] = puSrc1->ar64[1];
+    return iemAImpl_cvtss2sd_u128_r32_worker(&pResult->ar64[0], uMxCsrIn, pr32Src2);
 }
 #endif
@@ -16424,10 +16424,10 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtsd2ss_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
-{
-    pResult->MXCSR = iemAImpl_cvtsd2ss_u128_r64_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, pr64Src2);
-    pResult->uResult.ar32[1] = puSrc1->ar32[1];
-    pResult->uResult.ar32[2] = puSrc1->ar32[2];
-    pResult->uResult.ar32[3] = puSrc1->ar32[3];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsd2ss_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
+{
+    pResult->ar32[1] = puSrc1->ar32[1];
+    pResult->ar32[2] = puSrc1->ar32[2];
+    pResult->ar32[3] = puSrc1->ar32[3];
+    return iemAImpl_cvtsd2ss_u128_r64_worker(&pResult->ar32[0], uMxCsrIn, pr64Src2);
 }
 #endif
@@ -16438,10 +16438,10 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_haddps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_addps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc1->ar32[1]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc1->ar32[3]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc2->ar32[0], &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc2->ar32[2], &puSrc2->ar32[3]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_haddps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_addps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc1->ar32[1])
+           | iemAImpl_addps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[2], &puSrc1->ar32[3])
+           | iemAImpl_addps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc2->ar32[0], &puSrc2->ar32[1])
+           | iemAImpl_addps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc2->ar32[2], &puSrc2->ar32[3]);
 }
 #endif
@@ -16452,8 +16452,8 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_haddpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc1->ar64[1]);
-    pResult->MXCSR |= iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc2->ar64[0], &puSrc2->ar64[1]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_haddpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_addpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc1->ar64[1])
+           | iemAImpl_addpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc2->ar64[0], &puSrc2->ar64[1]);
 }
 #endif
@@ -16464,10 +16464,10 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_hsubps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_subps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc1->ar32[1]);
-    pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc1->ar32[3]);
-    pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc2->ar32[0], &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc2->ar32[2], &puSrc2->ar32[3]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_hsubps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_subps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc1->ar32[1])
+           | iemAImpl_subps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[2], &puSrc1->ar32[3])
+           | iemAImpl_subps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc2->ar32[0], &puSrc2->ar32[1])
+           | iemAImpl_subps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc2->ar32[2], &puSrc2->ar32[3]);
 }
 #endif
@@ -16478,8 +16478,8 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_hsubpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    pResult->MXCSR  = iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc1->ar64[1]);
-    pResult->MXCSR |= iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc2->ar64[0], &puSrc2->ar64[1]);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_hsubpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return   iemAImpl_subpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc1->ar64[1])
+           | iemAImpl_subpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc2->ar64[0], &puSrc2->ar64[1]);
 }
 #endif
@@ -16514,12 +16514,12 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_sqrtps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sqrtps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_sqrtps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_sqrtps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_sqrtps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_sqrtps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc2->ar32[3]);
+    return   iemAImpl_sqrtps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc2->ar32[0])
+           | iemAImpl_sqrtps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc2->ar32[1])
+           | iemAImpl_sqrtps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc2->ar32[2])
+           | iemAImpl_sqrtps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc2->ar32[3]);
 }
 #endif
@@ -16530,10 +16530,10 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_sqrtss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
-{
-    pResult->MXCSR = iemAImpl_sqrtps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, pr32Src2);
-    pResult->uResult.ar32[1] = puSrc1->ar32[1];
-    pResult->uResult.ar32[2] = puSrc1->ar32[2];
-    pResult->uResult.ar32[3] = puSrc1->ar32[3];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sqrtss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
+{
+    pResult->ar32[1] = puSrc1->ar32[1];
+    pResult->ar32[2] = puSrc1->ar32[2];
+    pResult->ar32[3] = puSrc1->ar32[3];
+    return iemAImpl_sqrtps_u128_worker(&pResult->ar32[0], uMxCsrIn, pr32Src2);
 }
 #endif
@@ -16568,10 +16568,10 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_sqrtpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sqrtpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_sqrtpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_sqrtpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc2->ar64[1]);
+    return   iemAImpl_sqrtpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc2->ar64[0])
+           | iemAImpl_sqrtpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc2->ar64[1]);
 }
 #endif
@@ -16582,8 +16582,8 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_sqrtsd_u128_r64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
-{
-    pResult->MXCSR = iemAImpl_sqrtpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, pr64Src2);
-    pResult->uResult.ar64[1] = puSrc1->ar64[1];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sqrtsd_u128_r64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2))
+{
+    pResult->ar64[1] = puSrc1->ar64[1];
+    return iemAImpl_sqrtpd_u128_worker(&pResult->ar64[0], uMxCsrIn, pr64Src2);
 }
 #endif
@@ -16618,12 +16618,12 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_rsqrtps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_rsqrtps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_rsqrt_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_rsqrt_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_rsqrt_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_rsqrt_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc2->ar32[3]);
+    return   iemAImpl_rsqrt_worker(&pResult->ar32[0], uMxCsrIn, &puSrc2->ar32[0])
+           | iemAImpl_rsqrt_worker(&pResult->ar32[1], uMxCsrIn, &puSrc2->ar32[1])
+           | iemAImpl_rsqrt_worker(&pResult->ar32[2], uMxCsrIn, &puSrc2->ar32[2])
+           | iemAImpl_rsqrt_worker(&pResult->ar32[3], uMxCsrIn, &puSrc2->ar32[3]);
 }
 
@@ -16632,10 +16632,10 @@
  * RSQRTSS
  */
-IEM_DECL_IMPL_DEF(void, iemAImpl_rsqrtss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
-{
-    pResult->MXCSR = iemAImpl_rsqrt_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, pr32Src2);
-    pResult->uResult.ar32[1] = puSrc1->ar32[1];
-    pResult->uResult.ar32[2] = puSrc1->ar32[2];
-    pResult->uResult.ar32[3] = puSrc1->ar32[3];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_rsqrtss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
+{
+    pResult->ar32[1] = puSrc1->ar32[1];
+    pResult->ar32[2] = puSrc1->ar32[2];
+    pResult->ar32[3] = puSrc1->ar32[3];
+    return iemAImpl_rsqrt_worker(&pResult->ar32[0], uMxCsrIn, pr32Src2);
 }
 #endif
@@ -16665,12 +16665,12 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_rcpps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_rcpps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_rcp_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_rcp_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_rcp_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_rcp_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc2->ar32[3]);
+    return   iemAImpl_rcp_worker(&pResult->ar32[0], uMxCsrIn, &puSrc2->ar32[0])
+           | iemAImpl_rcp_worker(&pResult->ar32[1], uMxCsrIn, &puSrc2->ar32[1])
+           | iemAImpl_rcp_worker(&pResult->ar32[2], uMxCsrIn, &puSrc2->ar32[2])
+           | iemAImpl_rcp_worker(&pResult->ar32[3], uMxCsrIn, &puSrc2->ar32[3]);
 }
 
@@ -16679,10 +16679,10 @@
  * RCPSS
  */
-IEM_DECL_IMPL_DEF(void, iemAImpl_rcpss_u128_r32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
-{
-    pResult->MXCSR = iemAImpl_rcp_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, pr32Src2);
-    pResult->uResult.ar32[1] = puSrc1->ar32[1];
-    pResult->uResult.ar32[2] = puSrc1->ar32[2];
-    pResult->uResult.ar32[3] = puSrc1->ar32[3];
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_rcpss_u128_r32,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2))
+{
+    pResult->ar32[1] = puSrc1->ar32[1];
+    pResult->ar32[2] = puSrc1->ar32[2];
+    pResult->ar32[3] = puSrc1->ar32[3];
+    return iemAImpl_rcp_worker(&pResult->ar32[0], uMxCsrIn, pr32Src2);
 }
 #endif
@@ -16693,12 +16693,12 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_addsubps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addsubps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_subps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_subps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_addps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+    return   iemAImpl_subps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc1->ar32[0], &puSrc2->ar32[0])
+           | iemAImpl_addps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc1->ar32[1], &puSrc2->ar32[1])
+           | iemAImpl_subps_u128_worker(&pResult->ar32[2], uMxCsrIn, &puSrc1->ar32[2], &puSrc2->ar32[2])
+           | iemAImpl_addps_u128_worker(&pResult->ar32[3], uMxCsrIn, &puSrc1->ar32[3], &puSrc2->ar32[3]);
 }
 #endif
@@ -16709,10 +16709,10 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_addsubpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_addsubpd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_subpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_addpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+    return   iemAImpl_subpd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc1->ar64[0], &puSrc2->ar64[0])
+           | iemAImpl_addpd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc1->ar64[1], &puSrc2->ar64[1]);
 }
 #endif
@@ -16734,12 +16734,12 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtpd2ps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtpd2ps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_cvtpd2ps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_cvtpd2ps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc2->ar64[1]);
-    pResult->uResult.au32[2] = 0;
-    pResult->uResult.au32[3] = 0;
+    pResult->au32[2] = 0;
+    pResult->au32[3] = 0;
+    return   iemAImpl_cvtpd2ps_u128_worker(&pResult->ar32[0], uMxCsrIn, &puSrc2->ar64[0])
+           | iemAImpl_cvtpd2ps_u128_worker(&pResult->ar32[1], uMxCsrIn, &puSrc2->ar64[1]);
 }
 #endif
@@ -16761,10 +16761,10 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtps2pd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtps2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_cvtps2pd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_cvtps2pd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc2->ar32[1]);
+    return   iemAImpl_cvtps2pd_u128_worker(&pResult->ar64[0], uMxCsrIn, &puSrc2->ar32[0])
+           | iemAImpl_cvtps2pd_u128_worker(&pResult->ar64[1], uMxCsrIn, &puSrc2->ar32[1]);
 }
 #endif
@@ -16783,12 +16783,12 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtdq2ps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtdq2ps_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_cvtdq2ps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, puSrc2->ai32[0]);
-    pResult->MXCSR |= iemAImpl_cvtdq2ps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, puSrc2->ai32[1]);
-    pResult->MXCSR |= iemAImpl_cvtdq2ps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, puSrc2->ai32[2]);
-    pResult->MXCSR |= iemAImpl_cvtdq2ps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, puSrc2->ai32[3]);
+    return   iemAImpl_cvtdq2ps_u128_worker(&pResult->ar32[0], uMxCsrIn, puSrc2->ai32[0])
+           | iemAImpl_cvtdq2ps_u128_worker(&pResult->ar32[1], uMxCsrIn, puSrc2->ai32[1])
+           | iemAImpl_cvtdq2ps_u128_worker(&pResult->ar32[2], uMxCsrIn, puSrc2->ai32[2])
+           | iemAImpl_cvtdq2ps_u128_worker(&pResult->ar32[3], uMxCsrIn, puSrc2->ai32[3]);
 }
 #endif
@@ -16810,12 +16810,12 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtps2dq_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtps2dq_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_cvtps2dq_u128_worker(&pResult->uResult.ai32[0], pFpuState->MXCSR, &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_cvtps2dq_u128_worker(&pResult->uResult.ai32[1], pFpuState->MXCSR, &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_cvtps2dq_u128_worker(&pResult->uResult.ai32[2], pFpuState->MXCSR, &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_cvtps2dq_u128_worker(&pResult->uResult.ai32[3], pFpuState->MXCSR, &puSrc2->ar32[3]);
+    return   iemAImpl_cvtps2dq_u128_worker(&pResult->ai32[0], uMxCsrIn, &puSrc2->ar32[0])
+           | iemAImpl_cvtps2dq_u128_worker(&pResult->ai32[1], uMxCsrIn, &puSrc2->ar32[1])
+           | iemAImpl_cvtps2dq_u128_worker(&pResult->ai32[2], uMxCsrIn, &puSrc2->ar32[2])
+           | iemAImpl_cvtps2dq_u128_worker(&pResult->ai32[3], uMxCsrIn, &puSrc2->ar32[3]);
 }
 #endif
@@ -16838,12 +16838,12 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvttps2dq_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttps2dq_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_cvttps2dq_u128_worker(&pResult->uResult.ai32[0], pFpuState->MXCSR, &puSrc2->ar32[0]);
-    pResult->MXCSR |= iemAImpl_cvttps2dq_u128_worker(&pResult->uResult.ai32[1], pFpuState->MXCSR, &puSrc2->ar32[1]);
-    pResult->MXCSR |= iemAImpl_cvttps2dq_u128_worker(&pResult->uResult.ai32[2], pFpuState->MXCSR, &puSrc2->ar32[2]);
-    pResult->MXCSR |= iemAImpl_cvttps2dq_u128_worker(&pResult->uResult.ai32[3], pFpuState->MXCSR, &puSrc2->ar32[3]);
+    return   iemAImpl_cvttps2dq_u128_worker(&pResult->ai32[0], uMxCsrIn, &puSrc2->ar32[0])
+           | iemAImpl_cvttps2dq_u128_worker(&pResult->ai32[1], uMxCsrIn, &puSrc2->ar32[1])
+           | iemAImpl_cvttps2dq_u128_worker(&pResult->ai32[2], uMxCsrIn, &puSrc2->ar32[2])
+           | iemAImpl_cvttps2dq_u128_worker(&pResult->ai32[3], uMxCsrIn, &puSrc2->ar32[3]);
 }
 #endif
@@ -16866,11 +16866,11 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvttpd2dq_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttpd2dq_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_cvttpd2dq_u128_worker(&pResult->uResult.ai32[0], pFpuState->MXCSR, &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_cvttpd2dq_u128_worker(&pResult->uResult.ai32[1], pFpuState->MXCSR, &puSrc2->ar64[1]);
-    pResult->uResult.au64[1] = 0;
+    pResult->au64[1] = 0;
+    return   iemAImpl_cvttpd2dq_u128_worker(&pResult->ai32[0], uMxCsrIn, &puSrc2->ar64[0])
+           | iemAImpl_cvttpd2dq_u128_worker(&pResult->ai32[1], uMxCsrIn, &puSrc2->ar64[1]);
 }
 #endif
@@ -16889,10 +16889,10 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtdq2pd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtdq2pd_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_cvtdq2pd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, puSrc2->ai32[0]);
-    pResult->MXCSR |= iemAImpl_cvtdq2pd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, puSrc2->ai32[1]);
+    return   iemAImpl_cvtdq2pd_u128_worker(&pResult->ar64[0], uMxCsrIn, puSrc2->ai32[0])
+           | iemAImpl_cvtdq2pd_u128_worker(&pResult->ar64[1], uMxCsrIn, puSrc2->ai32[1]);
 }
 #endif
@@ -16914,11 +16914,11 @@
 
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtpd2dq_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtpd2dq_u128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     RT_NOREF(puSrc1);
 
-    pResult->MXCSR  = iemAImpl_cvtpd2dq_u128_worker(&pResult->uResult.ai32[0], pFpuState->MXCSR, &puSrc2->ar64[0]);
-    pResult->MXCSR |= iemAImpl_cvtpd2dq_u128_worker(&pResult->uResult.ai32[1], pFpuState->MXCSR, &puSrc2->ar64[1]);
-    pResult->uResult.au64[1] = 0;
+    pResult->au64[1] = 0;
+    return   iemAImpl_cvtpd2dq_u128_worker(&pResult->ai32[0], uMxCsrIn, &puSrc2->ar64[0])
+           | iemAImpl_cvtpd2dq_u128_worker(&pResult->ai32[1], uMxCsrIn, &puSrc2->ar64[1]);
 }
 #endif
@@ -18232,27 +18232,27 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvttsd2si_i32_r64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint64_t *pu64Src))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttsd2si_i32_r64,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint64_t *pu64Src))
 {
     RTFLOAT64U r64Src;
 
     r64Src.u = *pu64Src;
-    iemSsePrepareValueR64(&r64Src, pFpuState->MXCSR, &r64Src); /* The de-normal flag is not set. */
-
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    iemSsePrepareValueR64(&r64Src, uMxCsrIn, &r64Src); /* The de-normal flag is not set. */
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     *pi32Dst = f64_to_i32_r_minMag(iemFpSoftF64FromIprt(&r64Src), true /*exact*/, &SoftState);
-    *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvttsd2si_i64_r64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint64_t *pu64Src))
+    return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttsd2si_i64_r64,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint64_t *pu64Src))
 {
     RTFLOAT64U r64Src;
 
     r64Src.u = *pu64Src;
-    iemSsePrepareValueR64(&r64Src, pFpuState->MXCSR, &r64Src); /* The de-normal flag is not set. */
-
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    iemSsePrepareValueR64(&r64Src, uMxCsrIn, &r64Src); /* The de-normal flag is not set. */
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     *pi64Dst = f64_to_i64_r_minMag(iemFpSoftF64FromIprt(&r64Src), true /*exact*/, &SoftState);
-    *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
+    return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
 }
 #endif
@@ -18263,27 +18263,27 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtsd2si_i32_r64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint64_t *pu64Src))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsd2si_i32_r64,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint64_t *pu64Src))
 {
     RTFLOAT64U r64Src;
 
     r64Src.u = *pu64Src;
-    iemSsePrepareValueR64(&r64Src, pFpuState->MXCSR, &r64Src); /* The de-normal flag is not set. */
-
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    iemSsePrepareValueR64(&r64Src, uMxCsrIn, &r64Src); /* The de-normal flag is not set. */
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     *pi32Dst = f64_to_i32(iemFpSoftF64FromIprt(&r64Src), SoftState.roundingMode, true /*exact*/, &SoftState);
-    *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtsd2si_i64_r64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint64_t *pu64Src))
+    return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsd2si_i64_r64,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint64_t *pu64Src))
 {
     RTFLOAT64U r64Src;
 
     r64Src.u = *pu64Src;
-    iemSsePrepareValueR64(&r64Src, pFpuState->MXCSR, &r64Src); /* The de-normal flag is not set. */
-
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    iemSsePrepareValueR64(&r64Src, uMxCsrIn, &r64Src); /* The de-normal flag is not set. */
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     *pi64Dst = f64_to_i64(iemFpSoftF64FromIprt(&r64Src), SoftState.roundingMode, true /*exact*/, &SoftState);
-    *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
+    return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
 }
 #endif
@@ -18294,27 +18294,27 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvttss2si_i32_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttss2si_i32_r32,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint32_t *pu32Src))
 {
     RTFLOAT32U r32Src;
 
     r32Src.u = *pu32Src;
-    iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */
-
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    iemSsePrepareValueR32(&r32Src, uMxCsrIn, &r32Src); /* The de-normal flag is not set. */
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     *pi32Dst = f32_to_i32_r_minMag(iemFpSoftF32FromIprt(&r32Src), true /*exact*/, &SoftState);
-    *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvttss2si_i64_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src))
+    return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvttss2si_i64_r32,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint32_t *pu32Src))
 {
     RTFLOAT32U r32Src;
 
     r32Src.u = *pu32Src;
-    iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */
-
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    iemSsePrepareValueR32(&r32Src, uMxCsrIn, &r32Src); /* The de-normal flag is not set. */
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     *pi64Dst = f32_to_i64_r_minMag(iemFpSoftF32FromIprt(&r32Src), true /*exact*/, &SoftState);
-    *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
+    return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
 }
 #endif
@@ -18325,27 +18325,27 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtss2si_i32_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtss2si_i32_r32,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint32_t *pu32Src))
 {
     RTFLOAT32U r32Src;
 
     r32Src.u = *pu32Src;
-    iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */
-
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    iemSsePrepareValueR32(&r32Src, uMxCsrIn, &r32Src); /* The de-normal flag is not set. */
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     *pi32Dst = f32_to_i32(iemFpSoftF32FromIprt(&r32Src), SoftState.roundingMode, true /*exact*/, &SoftState);
-    *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtss2si_i64_r32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src))
+    return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtss2si_i64_r32,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint32_t *pu32Src))
 {
     RTFLOAT32U r32Src;
 
     r32Src.u = *pu32Src;
-    iemSsePrepareValueR32(&r32Src, pFpuState->MXCSR, &r32Src); /* The de-normal flag is not set. */
-
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    iemSsePrepareValueR32(&r32Src, uMxCsrIn, &r32Src); /* The de-normal flag is not set. */
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     *pi64Dst = f32_to_i64(iemFpSoftF32FromIprt(&r32Src), SoftState.roundingMode, true /*exact*/, &SoftState);
-    *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
+    return uMxCsrIn | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
 }
 #endif
@@ -18356,17 +18356,17 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtsi2sd_r64_i32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t *pi32Src))
-{
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsi2sd_r64_i32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src))
+{
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     float64_t r64Res = i32_to_f64(*pi32Src, &SoftState);
-    *pfMxcsr = iemSseSoftStateAndR64ToMxcsrAndIprtResult(&SoftState, r64Res, pr64Dst, pFpuState->MXCSR);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtsi2sd_r64_i64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t *pi64Src))
-{
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    return iemSseSoftStateAndR64ToMxcsrAndIprtResult(&SoftState, r64Res, pr64Dst, uMxCsrIn);
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsi2sd_r64_i64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src))
+{
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     float64_t r64Res = i64_to_f64(*pi64Src, &SoftState);
-    *pfMxcsr = iemSseSoftStateAndR64ToMxcsrAndIprtResult(&SoftState, r64Res, pr64Dst, pFpuState->MXCSR);
+    return iemSseSoftStateAndR64ToMxcsrAndIprtResult(&SoftState, r64Res, pr64Dst, uMxCsrIn);
 }
 #endif
@@ -18377,17 +18377,17 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtsi2ss_r32_i32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t *pi32Src))
-{
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsi2ss_r32_i32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src))
+{
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     float32_t r32Res = i32_to_f32(*pi32Src, &SoftState);
-    *pfMxcsr = iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Res, pr32Dst, pFpuState->MXCSR);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_cvtsi2ss_r32_i64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t *pi64Src))
-{
-    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    return iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Res, pr32Dst, uMxCsrIn);
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cvtsi2ss_r32_i64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src))
+{
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
     float32_t r32Res = i64_to_f32(*pi64Src, &SoftState);
-    *pfMxcsr = iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Res, pr32Dst, pFpuState->MXCSR);
+    return iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Res, pr32Dst, uMxCsrIn);
 }
 #endif
@@ -18398,5 +18398,5 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_ucomiss_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_ucomiss_u128,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS;
@@ -18404,5 +18404,5 @@
     if (RTFLOAT32U_IS_SIGNALLING_NAN(&puSrc1->ar32[0]) || RTFLOAT32U_IS_SIGNALLING_NAN(&puSrc2->ar32[0]))
     {
-        *pfMxcsr   |= X86_MXCSR_IE;
+        uMxCsrIn   |= X86_MXCSR_IE;
         fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */
     }
@@ -18414,9 +18414,9 @@
     else
     {
-        softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(*pfMxcsr);
+        softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
 
         RTFLOAT32U r32Src1, r32Src2;
-        uint32_t fDe  = iemSsePrepareValueR32(&r32Src1, *pfMxcsr, &puSrc1->ar32[0]);
-                 fDe |= iemSsePrepareValueR32(&r32Src2, *pfMxcsr, &puSrc2->ar32[0]);
+        uint32_t fDe  = iemSsePrepareValueR32(&r32Src1, uMxCsrIn, &puSrc1->ar32[0]);
+                 fDe |= iemSsePrepareValueR32(&r32Src2, uMxCsrIn, &puSrc2->ar32[0]);
 
         float32_t f32Src1 = iemFpSoftF32FromIprt(&r32Src1);
@@ -18428,14 +18428,15 @@
         /* else:                         GREATER_THAN 000 */
 
-        *pfMxcsr |= fDe;
+        uMxCsrIn |= fDe;
     }
 
     *pfEFlags = fEFlagsNew;
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_vucomiss_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    iemAImpl_ucomiss_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2);
+    return uMxCsrIn;
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vucomiss_u128_fallback,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return iemAImpl_ucomiss_u128(uMxCsrIn, pfEFlags, puSrc1, puSrc2);
 }
 
@@ -18445,5 +18446,5 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_ucomisd_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_ucomisd_u128,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS;
@@ -18451,5 +18452,5 @@
     if (RTFLOAT64U_IS_SIGNALLING_NAN(&puSrc1->ar64[0]) || RTFLOAT64U_IS_SIGNALLING_NAN(&puSrc2->ar64[0]))
     {
-        *pfMxcsr   |= X86_MXCSR_IE;
+        uMxCsrIn   |= X86_MXCSR_IE;
         fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */
     }
@@ -18461,9 +18462,9 @@
     else
     {
-        softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(*pfMxcsr);
+        softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
 
         RTFLOAT64U r64Src1, r64Src2;
-        uint32_t fDe = iemSsePrepareValueR64(&r64Src1, *pfMxcsr, &puSrc1->ar64[0])
-                     | iemSsePrepareValueR64(&r64Src2, *pfMxcsr, &puSrc2->ar64[0]);
+        uint32_t fDe = iemSsePrepareValueR64(&r64Src1, uMxCsrIn, &puSrc1->ar64[0])
+                     | iemSsePrepareValueR64(&r64Src2, uMxCsrIn, &puSrc2->ar64[0]);
 
         float64_t f64Src1 = iemFpSoftF64FromIprt(&r64Src1);
@@ -18475,14 +18476,15 @@
         /* else:                         GREATER_THAN 000 */
 
-        *pfMxcsr |= fDe;
+        uMxCsrIn |= fDe;
     }
 
     *pfEFlags = fEFlagsNew;
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_vucomisd_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    iemAImpl_ucomisd_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2);
+    return uMxCsrIn;
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vucomisd_u128_fallback,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return iemAImpl_ucomisd_u128(uMxCsrIn, pfEFlags, puSrc1, puSrc2);
 }
 
@@ -18492,5 +18494,5 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_comiss_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_comiss_u128,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS;
@@ -18499,14 +18501,14 @@
         || RTFLOAT32U_IS_QUIET_NAN(&puSrc1->ar32[0]) || RTFLOAT32U_IS_QUIET_NAN(&puSrc2->ar32[0]))
     {
-        *pfMxcsr   |= X86_MXCSR_IE;
+        uMxCsrIn   |= X86_MXCSR_IE;
         fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */
     }
     else
     {
-        softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(*pfMxcsr);
+        softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
 
         RTFLOAT32U r32Src1, r32Src2;
-        uint32_t fDe = iemSsePrepareValueR32(&r32Src1, *pfMxcsr, &puSrc1->ar32[0])
-                     | iemSsePrepareValueR32(&r32Src2, *pfMxcsr, &puSrc2->ar32[0]);
+        uint32_t fDe = iemSsePrepareValueR32(&r32Src1, uMxCsrIn, &puSrc1->ar32[0])
+                     | iemSsePrepareValueR32(&r32Src2, uMxCsrIn, &puSrc2->ar32[0]);
 
         float32_t f32Src1 = iemFpSoftF32FromIprt(&r32Src1);
@@ -18518,15 +18520,16 @@
         /* else:                         GREATER_THAN 000 */
 
-        *pfMxcsr |= fDe;
+        uMxCsrIn |= fDe;
     }
 
     *pfEFlags = fEFlagsNew;
-}
-#endif
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_vcomiss_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    iemAImpl_comiss_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2);
+    return uMxCsrIn;
+}
+#endif
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcomiss_u128_fallback,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return iemAImpl_comiss_u128(uMxCsrIn, pfEFlags, puSrc1, puSrc2);
 }
 
@@ -18536,5 +18539,5 @@
  */
 #ifdef IEM_WITHOUT_ASSEMBLY
-IEM_DECL_IMPL_DEF(void, iemAImpl_comisd_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_comisd_u128,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
 {
     uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS;
@@ -18543,14 +18546,14 @@
         || RTFLOAT64U_IS_QUIET_NAN(&puSrc1->ar64[0]) || RTFLOAT64U_IS_QUIET_NAN(&puSrc2->ar64[0]))
     {
-        *pfMxcsr   |= X86_MXCSR_IE;
+        uMxCsrIn   |= X86_MXCSR_IE;
         fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */
     }
     else
     {
-        softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(*pfMxcsr);
+        softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(uMxCsrIn);
 
         RTFLOAT64U r64Src1, r64Src2;
-        uint32_t fDe  = iemSsePrepareValueR64(&r64Src1, *pfMxcsr, &puSrc1->ar64[0]);
-                 fDe |= iemSsePrepareValueR64(&r64Src2, *pfMxcsr, &puSrc2->ar64[0]);
+        uint32_t fDe  = iemSsePrepareValueR64(&r64Src1, uMxCsrIn, &puSrc1->ar64[0]);
+                 fDe |= iemSsePrepareValueR64(&r64Src2, uMxCsrIn, &puSrc2->ar64[0]);
 
         float64_t f64Src1 = iemFpSoftF64FromIprt(&r64Src1);
@@ -18562,14 +18565,15 @@
         /* else:                         GREATER_THAN 000 */
 
-        *pfMxcsr |= fDe;
+        uMxCsrIn |= fDe;
     }
 
     *pfEFlags = fEFlagsNew;
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_vcomisd_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
-{
-    iemAImpl_comisd_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2);
+    return uMxCsrIn;
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_vcomisd_u128_fallback,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    return iemAImpl_comisd_u128(uMxCsrIn, pfEFlags, puSrc1, puSrc2);
 }
 
Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py	(revision 104128)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py	(revision 104129)
@@ -2995,4 +2995,5 @@
     'IEM_MC_CALL_AVX_AIMPL_2':                                   (McBlock.parseMcCallAvxAImpl,      True,  True,  g_fNativeSimd),
     'IEM_MC_CALL_AVX_AIMPL_3':                                   (McBlock.parseMcCallAvxAImpl,      True,  True,  g_fNativeSimd),
+    'IEM_MC_CALL_AVX_AIMPL_NEW_3':                               (McBlock.parseMcCallAvxAImpl,      True,  True,  False, ),
     'IEM_MC_CALL_CIMPL_0':                                       (McBlock.parseMcCallCImpl,         True,  True,  False, ),
     'IEM_MC_CALL_CIMPL_1':                                       (McBlock.parseMcCallCImpl,         True,  True,  False, ),
@@ -3055,5 +3056,5 @@
     'IEM_MC_FETCH_MEM_I16':                                      (McBlock.parseMcGeneric,           True,  True,  False, ),
     'IEM_MC_FETCH_MEM_I32':                                      (McBlock.parseMcGeneric,           True,  True,  False, ),
-    'IEM_MC_FETCH_MEM_I64':                                      (McBlock.parseMcGeneric,           True,  True,  False, ),
+    'IEM_MC_FETCH_MEM_I64':                                      (McBlock.parseMcGeneric,           True,  True,  False,  ),
     'IEM_MC_FETCH_MEM_R32':                                      (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
     'IEM_MC_FETCH_MEM_R64':                                      (McBlock.parseMcGeneric,           True,  True,  g_fNativeSimd),
Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h	(revision 104128)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h	(revision 104129)
@@ -654,6 +654,6 @@
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
-        IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
+        IEM_MC_LOCAL(X86XMMREG,             SseRes);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    pSseRes,        SseRes,     0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc1,                      1);
         IEM_MC_ARG(PCX86XMMREG,             pSrc2,                      2);
@@ -675,7 +675,7 @@
          */
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
-        IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
+        IEM_MC_LOCAL(X86XMMREG,             SseRes);
         IEM_MC_LOCAL(X86XMMREG,             uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    pSseRes,        SseRes,     0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc1,                      1);
         IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,   pSrc2, uSrc2,               2);
@@ -718,6 +718,6 @@
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
-        IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
-        IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
+        IEM_MC_LOCAL(X86XMMREG,             SseRes);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    pSseRes,        SseRes,     0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc1,                      1);
         IEM_MC_ARG(PCRTFLOAT32U,            pSrc2,                      2);
@@ -739,7 +739,7 @@
          */
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
-        IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
+        IEM_MC_LOCAL(X86XMMREG,             SseRes);
         IEM_MC_LOCAL(RTFLOAT32U,            r32Src2);
-        IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    pSseRes,        SseRes,     0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc1,                      1);
         IEM_MC_ARG_LOCAL_REF(PCRTFLOAT32U,  pr32Src2,       r32Src2,    2);
@@ -782,6 +782,6 @@
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
-        IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
+        IEM_MC_LOCAL(X86XMMREG,             SseRes);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    pSseRes,        SseRes,     0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc1,                      1);
         IEM_MC_ARG(PCX86XMMREG,             pSrc2,                      2);
@@ -803,7 +803,7 @@
          */
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
-        IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
+        IEM_MC_LOCAL(X86XMMREG,             SseRes);
         IEM_MC_LOCAL(X86XMMREG,             uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    pSseRes,        SseRes,     0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc1,                      1);
         IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,   pSrc2, uSrc2,               2);
@@ -846,6 +846,6 @@
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
-        IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
-        IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
+        IEM_MC_LOCAL(X86XMMREG,             SseRes);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    pSseRes,        SseRes,     0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc1,                      1);
         IEM_MC_ARG(PCRTFLOAT64U,            pSrc2,                      2);
@@ -867,7 +867,7 @@
          */
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
-        IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
+        IEM_MC_LOCAL(X86XMMREG,             SseRes);
         IEM_MC_LOCAL(RTFLOAT64U,            r64Src2);
-        IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    pSseRes,        SseRes,     0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc1,                      1);
         IEM_MC_ARG_LOCAL_REF(PCRTFLOAT64U,  pr64Src2,       r64Src2,    2);
@@ -970,6 +970,6 @@
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse3);
-        IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
-        IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
+        IEM_MC_LOCAL(X86XMMREG,             SseRes);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    pSseRes,        SseRes,     0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc1,                      1);
         IEM_MC_ARG(PCX86XMMREG,             pSrc2,                      2);
@@ -991,7 +991,7 @@
          */
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
-        IEM_MC_LOCAL(IEMSSERESULT,          SseRes);
+        IEM_MC_LOCAL(X86XMMREG,             SseRes);
         IEM_MC_LOCAL(X86XMMREG,             uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PIEMSSERESULT, pSseRes,        SseRes,     0);
+        IEM_MC_ARG_LOCAL_REF(PX86XMMREG,    pSseRes,        SseRes,     0);
         IEM_MC_ARG(PCX86XMMREG,             pSrc1,                      1);
         IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,   pSrc2, uSrc2,               2);
@@ -3614,17 +3614,14 @@
             /* XMM, greg64 */
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
-            IEM_MC_LOCAL(uint32_t,    fMxcsr);
             IEM_MC_LOCAL(RTFLOAT32U,  r32Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,    pfMxcsr, fMxcsr,  0);
-            IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U,   pr32Dst, r32Dst,  1);
-            IEM_MC_ARG(const int64_t *,         pi64Src,          2);
+            IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U,   pr32Dst, r32Dst,  0);
+            IEM_MC_ARG(const int64_t *,         pi64Src,          1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_GREG_I64_CONST(pi64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2ss_r32_i64, pfMxcsr, pr32Dst, pi64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i64, pr32Dst, pi64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -3641,19 +3638,16 @@
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,   fMxcsr);
             IEM_MC_LOCAL(RTFLOAT32U, r32Dst);
             IEM_MC_LOCAL(int64_t,    i64Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U,       pr32Dst, r32Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const int64_t *,   pi64Src, i64Src,     2);
+            IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U,       pr32Dst, r32Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const int64_t *,   pi64Src, i64Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_I64(i64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2ss_r32_i64, pfMxcsr, pr32Dst, pi64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i64, pr32Dst, pi64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -3672,17 +3666,14 @@
             /* greg, XMM */
             IEM_MC_BEGIN(0, 0);
-            IEM_MC_LOCAL(uint32_t,   fMxcsr);
             IEM_MC_LOCAL(RTFLOAT32U, r32Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,  pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U, pr32Dst, r32Dst,     1);
-            IEM_MC_ARG(const int32_t *,       pi32Src,             2);
+            IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U, pr32Dst, r32Dst,     0);
+            IEM_MC_ARG(const int32_t *,       pi32Src,             1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_GREG_I32_CONST(pi32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2ss_r32_i32, pfMxcsr, pr32Dst, pi32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i32, pr32Dst, pi32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -3699,19 +3690,16 @@
             IEM_MC_BEGIN(0, 0);
             IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,   fMxcsr);
             IEM_MC_LOCAL(RTFLOAT32U, r32Dst);
             IEM_MC_LOCAL(int32_t,    i32Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,       pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U,      pr32Dst, r32Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const int32_t *,  pi32Src, i32Src,     2);
+            IEM_MC_ARG_LOCAL_REF(PRTFLOAT32U,      pr32Dst, r32Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const int32_t *,  pi32Src, i32Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_I32(i32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2ss_r32_i32, pfMxcsr, pr32Dst, pi32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i32, pr32Dst, pi32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -3739,17 +3727,14 @@
             /* XMM, greg64 */
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
-            IEM_MC_LOCAL(uint32_t,    fMxcsr);
             IEM_MC_LOCAL(RTFLOAT64U,  r64Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,    pfMxcsr, fMxcsr,  0);
-            IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U,   pr64Dst, r64Dst,  1);
-            IEM_MC_ARG(const int64_t *,         pi64Src,          2);
+            IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U,   pr64Dst, r64Dst,  0);
+            IEM_MC_ARG(const int64_t *,         pi64Src,          1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_GREG_I64_CONST(pi64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2sd_r64_i64, pfMxcsr, pr64Dst, pi64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i64, pr64Dst, pi64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -3766,19 +3751,16 @@
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,   fMxcsr);
             IEM_MC_LOCAL(RTFLOAT64U, r64Dst);
             IEM_MC_LOCAL(int64_t,    i64Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U,       pr64Dst, r64Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const int64_t *,   pi64Src, i64Src,     2);
+            IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U,       pr64Dst, r64Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const int64_t *,   pi64Src, i64Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_I64(i64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2sd_r64_i64, pfMxcsr, pr64Dst, pi64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i64, pr64Dst, pi64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -3797,17 +3779,14 @@
             /* XMM, greg32 */
             IEM_MC_BEGIN(0, 0);
-            IEM_MC_LOCAL(uint32_t,   fMxcsr);
             IEM_MC_LOCAL(RTFLOAT64U, r64Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,  pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Dst, r64Dst,     1);
-            IEM_MC_ARG(const int32_t *,       pi32Src,             2);
+            IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U, pr64Dst, r64Dst,     0);
+            IEM_MC_ARG(const int32_t *,       pi32Src,             1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_GREG_I32_CONST(pi32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2sd_r64_i32, pfMxcsr, pr64Dst, pi32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i32, pr64Dst, pi32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -3824,19 +3803,16 @@
             IEM_MC_BEGIN(0, 0);
             IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,   fMxcsr);
             IEM_MC_LOCAL(RTFLOAT64U, r64Dst);
             IEM_MC_LOCAL(int32_t,    i32Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,       pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U,      pr64Dst, r64Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const int32_t *,  pi32Src, i32Src,     2);
+            IEM_MC_ARG_LOCAL_REF(PRTFLOAT64U,      pr64Dst, r64Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const int32_t *,  pi32Src, i32Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_I32(i32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsi2sd_r64_i32, pfMxcsr, pr64Dst, pi32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i32, pr64Dst, pi32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4081,17 +4057,14 @@
             /* greg64, XMM */
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int64_t *,  pi64Dst, i64Dst,     1);
-            IEM_MC_ARG(const uint32_t *,     pu32Src,             2);
+            IEM_MC_ARG_LOCAL_REF(int64_t *,  pi64Dst, i64Dst,     0);
+            IEM_MC_ARG(const uint32_t *,     pu32Src,             1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i64_r32, pi64Dst, pu32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4108,19 +4081,16 @@
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
             IEM_MC_LOCAL(uint32_t,  u32Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int64_t *,         pi64Dst, i64Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const uint32_t *,  pu32Src, u32Src,     2);
+            IEM_MC_ARG_LOCAL_REF(int64_t *,         pi64Dst, i64Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const uint32_t *,  pu32Src, u32Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i64_r32, pi64Dst, pu32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4139,17 +4109,14 @@
             /* greg, XMM */
             IEM_MC_BEGIN(0, 0);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int32_t *,  pi32Dst, i32Dst,     1);
-            IEM_MC_ARG(const uint32_t *,     pu32Src,             2);
+            IEM_MC_ARG_LOCAL_REF(int32_t *,  pi32Dst, i32Dst,     0);
+            IEM_MC_ARG(const uint32_t *,     pu32Src,             1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i32_r32, pi32Dst, pu32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4166,19 +4133,16 @@
             IEM_MC_BEGIN(0, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
             IEM_MC_LOCAL(uint32_t,  u32Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int32_t *,         pi32Dst, i32Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const uint32_t *,  pu32Src, u32Src,     2);
+            IEM_MC_ARG_LOCAL_REF(int32_t *,         pi32Dst, i32Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const uint32_t *,  pu32Src, u32Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i32_r32, pi32Dst, pu32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4206,17 +4170,14 @@
             /* greg64, XMM */
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int64_t *,  pi64Dst, i64Dst,     1);
-            IEM_MC_ARG(const uint64_t *,     pu64Src,             2);
+            IEM_MC_ARG_LOCAL_REF(int64_t *,  pi64Dst, i64Dst,     0);
+            IEM_MC_ARG(const uint64_t *,     pu64Src,             1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttsd2si_i64_r64, pfMxcsr, pi64Dst, pu64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i64_r64, pi64Dst, pu64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4233,19 +4194,16 @@
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
             IEM_MC_LOCAL(uint64_t,  u64Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int64_t *,         pi64Dst, i64Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const uint64_t *,  pu64Src, u64Src,     2);
+            IEM_MC_ARG_LOCAL_REF(int64_t *,         pi64Dst, i64Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const uint64_t *,  pu64Src, u64Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttsd2si_i64_r64, pfMxcsr, pi64Dst, pu64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i64_r64, pi64Dst, pu64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4264,17 +4222,14 @@
             /* greg, XMM */
             IEM_MC_BEGIN(0, 0);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int32_t *,  pi32Dst, i32Dst,     1);
-            IEM_MC_ARG(const uint64_t *,     pu64Src,             2);
+            IEM_MC_ARG_LOCAL_REF(int32_t *,  pi32Dst, i32Dst,     0);
+            IEM_MC_ARG(const uint64_t *,     pu64Src,             1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttsd2si_i32_r64, pfMxcsr, pi32Dst, pu64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i32_r64, pi32Dst, pu64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4291,19 +4246,16 @@
             IEM_MC_BEGIN(0, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
             IEM_MC_LOCAL(uint64_t,  u64Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int32_t *,         pi32Dst, i32Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const uint64_t *,  pu64Src, u64Src,     2);
+            IEM_MC_ARG_LOCAL_REF(int32_t *,         pi32Dst, i32Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const uint64_t *,  pu64Src, u64Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvttsd2si_i32_r64, pfMxcsr, pi32Dst, pu64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i32_r64, pi32Dst, pu64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4469,17 +4421,14 @@
             /* greg64, XMM */
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int64_t *,  pi64Dst, i64Dst,     1);
-            IEM_MC_ARG(const uint32_t *,     pu32Src,             2);
+            IEM_MC_ARG_LOCAL_REF(int64_t *,  pi64Dst, i64Dst,     0);
+            IEM_MC_ARG(const uint32_t *,     pu32Src,             1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i64_r32, pi64Dst, pu32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4496,19 +4445,16 @@
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
             IEM_MC_LOCAL(uint32_t,  u32Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int64_t *,         pi64Dst, i64Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const uint32_t *,  pu32Src, u32Src,     2);
+            IEM_MC_ARG_LOCAL_REF(int64_t *,         pi64Dst, i64Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const uint32_t *,  pu32Src, u32Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i64_r32, pfMxcsr, pi64Dst, pu32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i64_r32, pi64Dst, pu32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4527,17 +4473,14 @@
             /* greg, XMM */
             IEM_MC_BEGIN(0, 0);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int32_t *,  pi32Dst, i32Dst,     1);
-            IEM_MC_ARG(const uint32_t *,     pu32Src,             2);
+            IEM_MC_ARG_LOCAL_REF(int32_t *,  pi32Dst, i32Dst,     0);
+            IEM_MC_ARG(const uint32_t *,     pu32Src,             1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i32_r32,  pi32Dst, pu32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4554,19 +4497,16 @@
             IEM_MC_BEGIN(0, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
             IEM_MC_LOCAL(uint32_t,  u32Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int32_t *,         pi32Dst, i32Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const uint32_t *,  pu32Src, u32Src,     2);
+            IEM_MC_ARG_LOCAL_REF(int32_t *,         pi32Dst, i32Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const uint32_t *,  pu32Src, u32Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtss2si_i32_r32, pfMxcsr, pi32Dst, pu32Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i32_r32, pi32Dst, pu32Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4594,17 +4534,14 @@
             /* greg64, XMM */
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int64_t *,  pi64Dst, i64Dst,     1);
-            IEM_MC_ARG(const uint64_t *,     pu64Src,             2);
+            IEM_MC_ARG_LOCAL_REF(int64_t *,  pi64Dst, i64Dst,     0);
+            IEM_MC_ARG(const uint64_t *,     pu64Src,             1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i64_r64, pfMxcsr, pi64Dst, pu64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i64_r64, pi64Dst, pu64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4621,10 +4558,8 @@
             IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int64_t,   i64Dst);
             IEM_MC_LOCAL(uint64_t,  u64Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int64_t *,         pi64Dst, i64Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const uint64_t *,  pu64Src, u64Src,     2);
+            IEM_MC_ARG_LOCAL_REF(int64_t *,         pi64Dst, i64Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const uint64_t *,  pu64Src, u64Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
@@ -4634,6 +4569,5 @@
 
             IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i64_r64, pfMxcsr, pi64Dst, pu64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i64_r64, pi64Dst, pu64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4652,17 +4586,14 @@
             /* greg32, XMM */
             IEM_MC_BEGIN(0, 0);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int32_t *,  pi32Dst, i32Dst,     1);
-            IEM_MC_ARG(const uint64_t *,     pu64Src,             2);
+            IEM_MC_ARG_LOCAL_REF(int32_t *,  pi32Dst, i32Dst,     0);
+            IEM_MC_ARG(const uint64_t *,     pu64Src,             1);
 
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i32_r64, pfMxcsr, pi32Dst, pu64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i32_r64, pi32Dst, pu64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4679,19 +4610,16 @@
             IEM_MC_BEGIN(0, 0);
             IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
-            IEM_MC_LOCAL(uint32_t,  fMxcsr);
             IEM_MC_LOCAL(int32_t,   i32Dst);
             IEM_MC_LOCAL(uint64_t,  u64Src);
-            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
-            IEM_MC_ARG_LOCAL_REF(int32_t *,         pi32Dst, i32Dst,     1);
-            IEM_MC_ARG_LOCAL_REF(const uint64_t *,  pu64Src, u64Src,     2);
+            IEM_MC_ARG_LOCAL_REF(int32_t *,         pi32Dst, i32Dst,     0);
+            IEM_MC_ARG_LOCAL_REF(const uint64_t *,  pu64Src, u64Src,     1);
 
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
             IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
             IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
-            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_2() is calling this but the tstIEMCheckMc testcase depends on it. */
 
             IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i32_r64, pfMxcsr, pi32Dst, pu64Src);
-            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i32_r64, pi32Dst, pu64Src);
             IEM_MC_IF_MXCSR_XCPT_PENDING() {
                 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4725,15 +4653,13 @@
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             3);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_PREPARE_SSE_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,      IEM_GET_MODRM_REG(pVCpu, bRm));
         IEM_MC_REF_XREG_XMM_CONST(puSrc2,      IEM_GET_MODRM_RM(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_ucomiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomiss_u128, pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4752,9 +4678,8 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
         IEM_MC_LOCAL(X86XMMREG,                 uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      3);
+        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      2);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
 
@@ -4766,7 +4691,6 @@
         IEM_MC_PREPARE_SSE_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,       IEM_GET_MODRM_REG(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_ucomiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomiss_u128, pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4799,15 +4723,13 @@
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             3);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_PREPARE_SSE_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,      IEM_GET_MODRM_REG(pVCpu, bRm));
         IEM_MC_REF_XREG_XMM_CONST(puSrc2,      IEM_GET_MODRM_RM(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_ucomisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomisd_u128, pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4826,9 +4748,8 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
         IEM_MC_LOCAL(X86XMMREG,                 uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      3);
+        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      2);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
 
@@ -4840,7 +4761,6 @@
         IEM_MC_PREPARE_SSE_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,       IEM_GET_MODRM_REG(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_ucomisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomisd_u128, pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4877,15 +4797,13 @@
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             3);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_PREPARE_SSE_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,      IEM_GET_MODRM_REG(pVCpu, bRm));
         IEM_MC_REF_XREG_XMM_CONST(puSrc2,      IEM_GET_MODRM_RM(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_comiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comiss_u128, pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4904,9 +4822,8 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
         IEM_MC_LOCAL(X86XMMREG,                 uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      3);
+        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      2);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
 
@@ -4918,7 +4835,6 @@
         IEM_MC_PREPARE_SSE_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,       IEM_GET_MODRM_REG(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_comiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comiss_u128, pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4951,15 +4867,13 @@
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse2);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             3);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             2);
         IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT();
         IEM_MC_PREPARE_SSE_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,      IEM_GET_MODRM_REG(pVCpu, bRm));
         IEM_MC_REF_XREG_XMM_CONST(puSrc2,      IEM_GET_MODRM_RM(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_comisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comisd_u128, pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -4978,9 +4892,8 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
         IEM_MC_LOCAL(X86XMMREG,                 uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      3);
+        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      2);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
 
@@ -4992,7 +4905,6 @@
         IEM_MC_PREPARE_SSE_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,       IEM_GET_MODRM_REG(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_comisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comisd_u128, pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h	(revision 104128)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap1.cpp.h	(revision 104129)
@@ -2296,16 +2296,14 @@
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             3);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             2);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
         IEM_MC_PREPARE_AVX_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,      IEM_GET_MODRM_REG(pVCpu, bRm));
         IEM_MC_REF_XREG_XMM_CONST(puSrc2,      IEM_GET_MODRM_RM(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
-                                 pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
+                                    pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -2324,9 +2322,8 @@
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
         IEM_MC_LOCAL(X86XMMREG,                 uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      3);
+        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      2);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
 
@@ -2338,8 +2335,7 @@
         IEM_MC_PREPARE_AVX_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,       IEM_GET_MODRM_REG(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
-                                 pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback),
+                                    pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -2372,16 +2368,14 @@
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             3);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             2);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
         IEM_MC_PREPARE_AVX_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,      IEM_GET_MODRM_REG(pVCpu, bRm));
         IEM_MC_REF_XREG_XMM_CONST(puSrc2,      IEM_GET_MODRM_RM(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
-                                 pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
+                                    pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -2400,9 +2394,8 @@
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
         IEM_MC_LOCAL(X86XMMREG,                 uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      3);
+        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      2);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
 
@@ -2414,8 +2407,7 @@
         IEM_MC_PREPARE_AVX_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,       IEM_GET_MODRM_REG(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
-                                 pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback),
+                                    pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -2451,16 +2443,14 @@
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             3);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             2);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
         IEM_MC_PREPARE_AVX_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,      IEM_GET_MODRM_REG(pVCpu, bRm));
         IEM_MC_REF_XREG_XMM_CONST(puSrc2,      IEM_GET_MODRM_RM(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
-                                 pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
+                                    pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -2479,9 +2469,8 @@
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
         IEM_MC_LOCAL(X86XMMREG,                 uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      3);
+        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      2);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
 
@@ -2493,8 +2482,7 @@
         IEM_MC_PREPARE_AVX_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,       IEM_GET_MODRM_REG(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
-                                 pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback),
+                                    pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -2527,16 +2515,14 @@
         IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV_EX(fAvx);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             3);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc2,             2);
         IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
         IEM_MC_PREPARE_AVX_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,      IEM_GET_MODRM_REG(pVCpu, bRm));
         IEM_MC_REF_XREG_XMM_CONST(puSrc2,      IEM_GET_MODRM_RM(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
-                                 pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
+                                    pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
@@ -2555,9 +2541,8 @@
         IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
         IEM_MC_LOCAL(uint32_t, fEFlags);
-        IEM_MC_ARG(uint32_t *,                  pfMxcsr,            0);
-        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   1);
-        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             2);
+        IEM_MC_ARG_LOCAL_REF(uint32_t *,        pEFlags, fEFlags,   0);
+        IEM_MC_ARG(PCX86XMMREG,                 puSrc1,             1);
         IEM_MC_LOCAL(X86XMMREG,                 uSrc2);
-        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      3);
+        IEM_MC_ARG_LOCAL_REF(PCX86XMMREG,       puSrc2, uSrc2,      2);
         IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
 
@@ -2569,8 +2554,7 @@
         IEM_MC_PREPARE_AVX_USAGE();
         IEM_MC_FETCH_EFLAGS(fEFlags);
-        IEM_MC_REF_MXCSR(pfMxcsr);
         IEM_MC_REF_XREG_XMM_CONST(puSrc1,       IEM_GET_MODRM_REG(pVCpu, bRm));
-        IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
-                                 pfMxcsr, pEFlags, puSrc1, puSrc2);
+        IEM_MC_CALL_AVX_AIMPL_NEW_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback),
+                                    pEFlags, puSrc1, puSrc2);
         IEM_MC_IF_MXCSR_XCPT_PENDING() {
             IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp	(revision 104128)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp	(revision 104129)
@@ -1081,5 +1081,5 @@
 #define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE()                                                 NOP()
 
-#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg)                                           IEM_LIVENESS_MXCSR_MODIFY() //; IEM_LIVENESS_XREG_CLOBBER(a_iXmmReg)
+#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg)                                           NOP() //IEM_LIVENESS_XREG_CLOBBER(a_iXmmReg)
 #define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr)                                                       IEM_LIVENESS_MXCSR_MODIFY()
 
@@ -1094,8 +1094,9 @@
 #define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1)                                             NOP()
 #define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2)                                         NOP()
-#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1)                                             NOP()
-#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2)                                         NOP()
+#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1)                                             IEM_LIVENESS_MXCSR_MODIFY()
+#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2)                                         IEM_LIVENESS_MXCSR_MODIFY()
 #define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a0, a1)                                             NOP()
 #define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a0, a1, a2)                                         NOP()
+#define IEM_MC_CALL_AVX_AIMPL_NEW_3(a_pfnAImpl, a0, a1, a2)                                     IEM_LIVENESS_MXCSR_MODIFY()
 
 #define IEM_LIVENESS_ONE_STATUS_EFLAG_INPUT(a_fBit) \
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h	(revision 104128)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h	(revision 104129)
@@ -1150,10 +1150,22 @@
 #ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
 #define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
-    off = iemNativeEmitSimdMaybeRaiseSseAvxSimdFpOrUdXcpt(pReNative, off)
+    off = iemNativeEmitSimdMaybeRaiseSseAvxSimdFpOrUdXcpt(pReNative, off, pCallEntry->idxInstr)
 
 /** Emits code for IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT. */
 DECL_INLINE_THROW(uint32_t)
-iemNativeEmitSimdMaybeRaiseSseAvxSimdFpOrUdXcpt(PIEMRECOMPILERSTATE pReNative, uint32_t off)
-{
+iemNativeEmitSimdMaybeRaiseSseAvxSimdFpOrUdXcpt(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr)
+{
+    /*
+     * Make sure we don't have any outstanding guest register writes as we may
+     * raise an \#UD or \#XF and all guest register must be up to date in CPUMCTX.
+     */
+    off = iemNativeRegFlushPendingWrites(pReNative, off);
+
+#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
+    off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
+#else
+    RT_NOREF(idxInstr);
+#endif
+
     uint8_t const idxLabelRaiseSseAvxFpRelated = iemNativeLabelCreate(pReNative, kIemNativeLabelType_RaiseSseAvxFpRelated);
     uint8_t const idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ReadOnly);
@@ -8550,41 +8562,4 @@
 
 
-#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
-    off = iemNativeEmitSimdSseUpdateMxcsr(pReNative, off, a_fMxcsr)
-
-/** Emits code for IEM_MC_SSE_UPDATE_MXCSR. */
-DECL_INLINE_THROW(uint32_t)
-iemNativeEmitSimdSseUpdateMxcsr(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxMxCsrVar)
-{
-    IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxMxCsrVar);
-    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxMxCsrVar, sizeof(uint32_t));
-
-    uint8_t const idxRegMxCsr    = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ForUpdate);
-    uint8_t const idxVarRegMxCsr = iemNativeVarRegisterAcquire(pReNative, idxMxCsrVar, &off, true /*fInitalized*/);
-    uint8_t const idxVarRegTmp   = iemNativeRegAllocTmp(pReNative, &off);
-
-    /** @todo r=aeichner I think it would be safe to spare the temporary register and trash
-     *                   the variable MXCSR register as it isn't used afterwards in the microcode block anyway.
-     *                   Needs verification though, so play it safe for now.
-     */
-    /* mov tmp, varmxcsr */
-    off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxVarRegTmp, idxVarRegMxCsr);
-    /* and tmp, X86_MXCSR_XCPT_FLAGS */
-    off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxVarRegTmp, X86_MXCSR_XCPT_FLAGS);
-    /* or mxcsr, tmp */
-    off = iemNativeEmitOrGpr32ByGpr(pReNative, off, idxRegMxCsr, idxVarRegTmp);
-
-    /* Writeback the MXCSR register value (there is no delayed writeback for such registers at the moment). */
-    off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxRegMxCsr, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.XState.x87.MXCSR));
-
-    /* Free but don't flush the MXCSR register. */
-    iemNativeRegFreeTmp(pReNative, idxRegMxCsr);
-    iemNativeVarRegisterRelease(pReNative, idxMxCsrVar);
-    iemNativeRegFreeTmp(pReNative, idxVarRegTmp);
-
-    return off;
-}
-
-
 #define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
     off = iemNativeEmitSimdSseStoreResult(pReNative, off, a_SseData, a_iXmmReg)
@@ -8592,27 +8567,15 @@
 /** Emits code for IEM_MC_STORE_SSE_RESULT. */
 DECL_INLINE_THROW(uint32_t)
-iemNativeEmitSimdSseStoreResult(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxSseDataVar, uint8_t iXReg)
-{
-    IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxSseDataVar);
-    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxSseDataVar, sizeof(IEMSSERESULT));
-
-    /** @todo r=aeichner We probably need to rework this MC statement and the users to make thing more efficient. */
-    uint8_t const idxSimdRegDst    = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg),
-                                                                             kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite);
-    uint8_t const idxRegMxCsr      = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ForUpdate);
-    uint8_t const idxVarRegResAddr = iemNativeRegAllocTmp(pReNative, &off);
-    uint8_t const idxRegTmp        = iemNativeRegAllocTmp(pReNative, &off);
-
-    off = iemNativeEmitLoadArgGregWithVarAddr(pReNative, off, idxVarRegResAddr, idxSseDataVar, false /*fFlushShadows*/);
-
-    /* Update MXCSR. */
-    off = iemNativeEmitLoadGprByGprU32(pReNative, off, idxRegTmp, idxVarRegResAddr, RT_UOFFSETOF_DYN(IEMSSERESULT, MXCSR));
-    /* tmp &= X86_MXCSR_XCPT_FLAGS. */
-    off = iemNativeEmitAndGpr32ByImm(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_FLAGS);
-    /* mxcsr |= tmp */
-    off = iemNativeEmitOrGpr32ByGpr(pReNative, off, idxRegMxCsr, idxRegTmp);
-
-    /* Writeback the MXCSR register value (there is no delayed writeback for such registers at the moment). */
-    off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxRegMxCsr, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.XState.x87.MXCSR));
+iemNativeEmitSimdSseStoreResult(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxSseRes, uint8_t iXReg)
+{
+    IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxSseRes);
+    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxSseRes, sizeof(X86XMMREG));
+
+    /* The ForUpdate is important as we might end up not writing the result value to the register in case of an unmasked exception. */
+    uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(iXReg),
+                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate);
+    uint8_t const idxVarRegRes  = iemNativeVarSimdRegisterAcquire(pReNative, idxSseRes, &off, true /*fInitalized*/);
+    uint8_t const idxRegMxCsr   = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr, kIemNativeGstRegUse_ReadOnly);
+    uint8_t const idxRegTmp     = iemNativeRegAllocTmp(pReNative, &off);
 
     /* Update the value if there is no unmasked exception. */
@@ -8631,12 +8594,11 @@
     uint32_t offFixup = off;
     off = iemNativeEmitJnzToFixed(pReNative, off, off);
-    AssertCompileMemberSize(IEMSSERESULT, uResult, sizeof(RTFLOAT128U));
-    off = iemNativeEmitLoadVecRegByGprU128(pReNative, off, idxSimdRegDst, idxVarRegResAddr, RT_UOFFSETOF_DYN(IEMSSERESULT, uResult));
+    off = iemNativeEmitSimdLoadVecRegFromVecRegU128(pReNative, off, idxSimdRegDst, idxVarRegRes);
     iemNativeFixupFixedJump(pReNative, offFixup, off);
 
     /* Free but don't flush the shadowed register. */
+    iemNativeVarRegisterRelease(pReNative, idxSseRes);
     iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst);
     iemNativeRegFreeTmp(pReNative, idxRegMxCsr);
-    iemNativeRegFreeTmp(pReNative, idxVarRegResAddr);
     iemNativeRegFreeTmp(pReNative, idxRegTmp);
 
@@ -8655,4 +8617,9 @@
 iemNativeEmitCallSseAImplCommon(PIEMRECOMPILERSTATE pReNative, uint32_t off, uintptr_t pfnAImpl, uint8_t cArgs)
 {
+    /* Grab the MXCSR register, it must not be call volatile or we end up freeing it when setting up the call below. */
+    uint8_t const  idxRegMxCsr = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr,
+                                                                 kIemNativeGstRegUse_ForUpdate, true /*fNoVolatileRegs*/);
+    AssertRelease(!(RT_BIT_32(idxRegMxCsr) & IEMNATIVE_CALL_VOLATILE_GREG_MASK));
+
     /*
      * Need to do the FPU preparation.
@@ -8663,10 +8630,11 @@
      * Do all the call setup and cleanup.
      */
-    off = iemNativeEmitCallCommon(pReNative, off, cArgs + IEM_SSE_AIMPL_HIDDEN_ARGS, IEM_SSE_AIMPL_HIDDEN_ARGS);
+    off = iemNativeEmitCallCommon(pReNative, off, cArgs + IEM_SSE_AIMPL_HIDDEN_ARGS, IEM_SSE_AIMPL_HIDDEN_ARGS, false /*fFlushPendingWrites*/);
 
     /*
-     * Load the XState::x87 pointer.
+     * Load the MXCSR register into the first argument and mask out the current exception flags.
      */
-    off = iemNativeEmitLeaGprByGstRegRef(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, kIemNativeGstRegRef_X87, 0 /*idxRegInClass*/);
+    off = iemNativeEmitLoadGprFromGpr32(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, idxRegMxCsr);
+    off = iemNativeEmitAndGpr32ByImm(pReNative, off, IEMNATIVE_CALL_ARG0_GREG, ~X86_MXCSR_XCPT_FLAGS);
 
     /*
@@ -8675,4 +8643,15 @@
     off = iemNativeEmitCallImm(pReNative, off, pfnAImpl);
 
+    /*
+     * The updated MXCSR is in the return register.
+     */
+    off = iemNativeEmitLoadGprFromGpr32(pReNative, off, idxRegMxCsr, IEMNATIVE_CALL_RET_GREG);
+
+#ifndef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
+    /* Writeback the MXCSR register value (there is no delayed writeback for such registers at the moment). */
+    off = iemNativeEmitStoreGprToVCpuU32(pReNative, off, idxRegMxCsr, RT_UOFFSETOF_DYN(VMCPU, cpum.GstCtx.XState.x87.MXCSR));
+#endif
+    iemNativeRegFreeTmp(pReNative, idxRegMxCsr);
+
     return off;
 }
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp	(revision 104128)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp	(revision 104129)
@@ -2640,5 +2640,7 @@
     uint8_t const idxHstReg = pReNative->Core.aidxGstRegShadows[enmGstReg];
 
-    Assert(enmGstReg >= kIemNativeGstReg_GprFirst && enmGstReg <= kIemNativeGstReg_GprLast);
+    Assert(   (   enmGstReg >= kIemNativeGstReg_GprFirst
+               && enmGstReg <= kIemNativeGstReg_GprLast)
+           || enmGstReg == kIemNativeGstReg_MxCsr);
     Assert(   idxHstReg != UINT8_MAX
            && pReNative->Core.bmGstRegShadowDirty & RT_BIT_64(enmGstReg));
@@ -3324,7 +3326,7 @@
         if (   (   enmIntendedUse == kIemNativeGstRegUse_ForFullWrite
                 || enmIntendedUse == kIemNativeGstRegUse_ForUpdate)
-            && enmGstReg >= kIemNativeGstReg_GprFirst
-            && enmGstReg <= kIemNativeGstReg_GprLast
-            )
+            && (   (   enmGstReg >= kIemNativeGstReg_GprFirst
+                    && enmGstReg <= kIemNativeGstReg_GprLast)
+                || enmGstReg == kIemNativeGstReg_MxCsr))
         {
 # ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
@@ -3356,7 +3358,7 @@
     if (   (   enmIntendedUse == kIemNativeGstRegUse_ForFullWrite
             || enmIntendedUse == kIemNativeGstRegUse_ForUpdate)
-        && enmGstReg >= kIemNativeGstReg_GprFirst
-        && enmGstReg <= kIemNativeGstReg_GprLast
-        )
+        && (   (   enmGstReg >= kIemNativeGstReg_GprFirst
+                && enmGstReg <= kIemNativeGstReg_GprLast)
+            || enmGstReg == kIemNativeGstReg_MxCsr))
     {
 # ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
Index: trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py	(revision 104128)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py	(revision 104129)
@@ -82,5 +82,4 @@
     'RTUINT128U':       (  128,   False, 'RTUINT128U',      ),
     'X86XMMREG':        (  128,   False, 'X86XMMREG',       ),
-    'IEMSSERESULT':     ( 128+32, False, 'IEMSSERESULT',    ),
     'IEMMEDIAF2XMMSRC': (  256,   False, 'IEMMEDIAF2XMMSRC',),
     'RTUINT256U':       (  256,   False, 'RTUINT256U',      ),
@@ -1898,4 +1897,5 @@
         'IEM_MC_CALL_AVX_AIMPL_4':                  '__aimpl_avx',
         'IEM_MC_CALL_AVX_AIMPL_5':                  '__aimpl_avx',
+        'IEM_MC_CALL_AVX_AIMPL_NEW_3':              '__aimpl_avx',
     };
     def analyzeAndAnnotateName(self, aoStmts: List[iai.McStmt]):
Index: trunk/src/VBox/VMM/include/IEMInternal.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMInternal.h	(revision 104128)
+++ trunk/src/VBox/VMM/include/IEMInternal.h	(revision 104129)
@@ -5,5 +5,5 @@
 
 /*
- * Copyright (C) 2011-2023 Oracle and/or its affiliates.
+ * Copyright (C) 2011-2024 Oracle and/or its affiliates.
  *
  * This file is part of VirtualBox base platform packages, as
@@ -3850,11 +3850,11 @@
 FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
 
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
 typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U64,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
 typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U32,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */
 typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I64U32,(uint32_t uMxCsrIn, int64_t *pi64Dst, const uint32_t *pu32Src)); /* pu32Src is a single precision floating point. */
 typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
 
@@ -3871,7 +3871,7 @@
 FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
 
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I32,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int32_t *pi32Src));
 typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R32I64,(uint32_t uMxCsrIn, PRTFLOAT32U pr32Dst, const int64_t *pi64Src));
 typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
 
@@ -3879,7 +3879,7 @@
 FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
 
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I32,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int32_t *pi32Src));
 typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2R64I64,(uint32_t uMxCsrIn, PRTFLOAT64U pr64Dst, const int64_t *pi64Src));
 typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
 
@@ -3888,5 +3888,5 @@
 
 
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLF2EFLMXCSR128,(uint32_t uMxCsrIn, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
 typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
 
@@ -4247,21 +4247,4 @@
  * @{ */
 /**
- * A SSE result.
- */
-typedef struct IEMSSERESULT
-{
-    /** The output value. */
-    X86XMMREG       uResult;
-    /** The output status. */
-    uint32_t        MXCSR;
-} IEMSSERESULT;
-AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
-/** Pointer to a SSE result. */
-typedef IEMSSERESULT *PIEMSSERESULT;
-/** Pointer to a const SSE result. */
-typedef IEMSSERESULT const *PCIEMSSERESULT;
-
-
-/**
  * A AVX128 result.
  */
@@ -4297,9 +4280,9 @@
 
 
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
 typedef FNIEMAIMPLFPSSEF2U128  *PFNIEMAIMPLFPSSEF2U128;
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R32,(uint32_t uMxCsrIn, PX86XMMREG Result, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
 typedef FNIEMAIMPLFPSSEF2U128R32  *PFNIEMAIMPLFPSSEF2U128R32;
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPSSEF2U128R64,(uint32_t uMxCsrIn, PX86XMMREG pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
 typedef FNIEMAIMPLFPSSEF2U128R64  *PFNIEMAIMPLFPSSEF2U128R64;
 
@@ -5479,5 +5462,4 @@
 /** @name SSE+AVX SIMD access and helpers.
  * @{ */
-void            iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
 void            iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
 /** @} */
Index: trunk/src/VBox/VMM/include/IEMMc.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMMc.h	(revision 104128)
+++ trunk/src/VBox/VMM/include/IEMMc.h	(revision 104129)
@@ -2960,9 +2960,11 @@
 
 /** Stores SSE SIMD result updating MXCSR. */
-#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
-    iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
-/** Updates MXCSR. */
-#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
-    iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
+#define IEM_MC_STORE_SSE_RESULT(a_Res, a_iXmmReg) \
+    do { \
+        PCX86FXSTATE pFpuCtx = &pVCpu->cpum.GstCtx.XState.x87; \
+        if ((  ~((pFpuCtx->MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
+             & (pFpuCtx->MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0) \
+            pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXmmReg)] = (a_Res); \
+    } while (0)
 
 /** Prepares for using the SSE state.
@@ -3024,5 +3026,6 @@
     do { \
         IEM_MC_PREPARE_SSE_USAGE(); \
-        a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
+        pVCpu->cpum.GstCtx.XState.x87.MXCSR = a_pfnAImpl(pVCpu->cpum.GstCtx.XState.x87.MXCSR & ~X86_MXCSR_XCPT_FLAGS, \
+                                                        (a0), (a1)); \
     } while (0)
 
@@ -3038,5 +3041,6 @@
     do { \
         IEM_MC_PREPARE_SSE_USAGE(); \
-        a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
+        pVCpu->cpum.GstCtx.XState.x87.MXCSR = a_pfnAImpl(pVCpu->cpum.GstCtx.XState.x87.MXCSR & ~X86_MXCSR_XCPT_FLAGS, \
+                                                         (a0), (a1), (a2)); \
     } while (0)
 
@@ -3071,4 +3075,26 @@
         IEM_MC_PREPARE_AVX_USAGE(); \
         a_pfnAImpl(&pVCpu->cpum.GstCtx.XState, (a1), (a2), (a3)); \
+    } while (0)
+
+/**
+ * Calls a AVX assembly implementation taking three visible arguments.
+ *
+ * @param   a_pfnAImpl      Pointer to the assembly SSE routine.
+ * @param   a0              The first extra argument.
+ * @param   a1              The second extra argument.
+ * @param   a2              The third extra argument.
+ *
+ * @note The and'ing with X86_MXCSR_XCPT_FLAGS is just a precaution as
+ *       the called helper should return an MXCSR with only new exception flags
+ *       added.
+ * @note This is temporarily required for the v(u)comis* stuff because
+ *       tstIEMAImpl will not compile otherwise, will be removed once the AVX
+ *       stuff is reworked, see @bugref{10641}
+ */
+#define IEM_MC_CALL_AVX_AIMPL_NEW_3(a_pfnAImpl, a0, a1, a2) \
+    do { \
+        IEM_MC_PREPARE_SSE_USAGE(); \
+        pVCpu->cpum.GstCtx.XState.x87.MXCSR |=   a_pfnAImpl(pVCpu->cpum.GstCtx.XState.x87.MXCSR, (a0), (a1), (a2)) \
+                                               & X86_MXCSR_XCPT_FLAGS; \
     } while (0)
 
Index: trunk/src/VBox/VMM/testcase/tstIEMAImpl.cpp
===================================================================
--- trunk/src/VBox/VMM/testcase/tstIEMAImpl.cpp	(revision 104128)
+++ trunk/src/VBox/VMM/testcase/tstIEMAImpl.cpp	(revision 104129)
@@ -5,5 +5,5 @@
 
 /*
- * Copyright (C) 2022-2023 Oracle and/or its affiliates.
+ * Copyright (C) 2022-2024 Oracle and/or its affiliates.
  *
  * This file is part of VirtualBox base platform packages, as
@@ -5594,6 +5594,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     uint32_t cMinNormalPairs       = (cTests - 144) / 4;
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32); iFn++)
@@ -5635,44 +5633,44 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResM; RT_ZERO(ResM);
-                        pfn(&State, &ResM, &TestData.InVal1, &TestData.InVal2);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResM.MXCSR;
-                        TestData.OutVal    = ResM.uResult;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
+                        X86XMMREG ResM; RT_ZERO(ResM);
+                        uint32_t uMxCsrOutM = pfn(uMxCsrIn, &ResM, &TestData.InVal1, &TestData.InVal2);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutM;
+                        TestData.OutVal    = ResM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResU; RT_ZERO(ResU);
-                        pfn(&State, &ResU, &TestData.InVal1, &TestData.InVal2);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResU.MXCSR;
-                        TestData.OutVal    = ResU.uResult;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
+                        X86XMMREG ResU; RT_ZERO(ResU);
+                        uint32_t uMxCsrOutU = pfn(uMxCsrIn, &ResU, &TestData.InVal1, &TestData.InVal2);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutU;
+                        TestData.OutVal    = ResU;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        uint16_t fXcpt = (ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
+                        uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS;
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
-                            IEMSSERESULT Res1; RT_ZERO(Res1);
-                            pfn(&State, &Res1, &TestData.InVal1, &TestData.InVal2);
-                            TestData.fMxcsrIn  = State.MXCSR;
-                            TestData.fMxcsrOut = Res1.MXCSR;
-                            TestData.OutVal    = Res1.uResult;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            X86XMMREG Res1; RT_ZERO(Res1);
+                            uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &Res1, &TestData.InVal1, &TestData.InVal2);
+                            TestData.fMxcsrIn  = uMxCsrIn;
+                            TestData.fMxcsrOut = uMxCsrOut1;
+                            TestData.OutVal    = Res1;
                             GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                            if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
+                            if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS))
                             {
-                                fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
-                                IEMSSERESULT Res2; RT_ZERO(Res2);
-                                pfn(&State, &Res2, &TestData.InVal1, &TestData.InVal2);
-                                TestData.fMxcsrIn  = State.MXCSR;
-                                TestData.fMxcsrOut = Res2.MXCSR;
-                                TestData.OutVal    = Res2.uResult;
+                                fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS;
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                X86XMMREG Res2; RT_ZERO(Res2);
+                                uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &Res2, &TestData.InVal1, &TestData.InVal2);
+                                TestData.fMxcsrIn  = uMxCsrIn;
+                                TestData.fMxcsrOut = uMxCsrOut2;
+                                TestData.OutVal    = Res2;
                                 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                             }
@@ -5681,10 +5679,10 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
-                                        IEMSSERESULT Res3; RT_ZERO(Res3);
-                                        pfn(&State, &Res3, &TestData.InVal1, &TestData.InVal2);
-                                        TestData.fMxcsrIn  = State.MXCSR;
-                                        TestData.fMxcsrOut = Res3.MXCSR;
-                                        TestData.OutVal    = Res3.uResult;
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        X86XMMREG Res3; RT_ZERO(Res3);
+                                        uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &Res3, &TestData.InVal1, &TestData.InVal2);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
+                                        TestData.fMxcsrOut = uMxCsrOut3;
+                                        TestData.OutVal    = Res3;
                                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                                     }
@@ -5701,6 +5699,4 @@
 static void SseBinaryR32Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32); iFn++)
     {
@@ -5717,13 +5713,12 @@
             for (uint32_t iTest = 0; iTest < cbTests / sizeof(paTests[0]); iTest++)
             {
-                IEMSSERESULT Res; RT_ZERO(Res);
-
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].InVal2);
-                bool fValsIdentical =    RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[0], &paTests[iTest].OutVal.ar32[0])
-                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[1], &paTests[iTest].OutVal.ar32[1])
-                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[2], &paTests[iTest].OutVal.ar32[2])
-                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]);
-                if (   Res.MXCSR != paTests[iTest].fMxcsrOut
+                X86XMMREG Res; RT_ZERO(Res);
+
+                uint32_t uMxCsrOut = pfn(paTests[iTest].fMxcsrIn, &Res, &paTests[iTest].InVal1, &paTests[iTest].InVal2);
+                bool fValsIdentical =    RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[0], &paTests[iTest].OutVal.ar32[0])
+                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[1], &paTests[iTest].OutVal.ar32[1])
+                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[2], &paTests[iTest].OutVal.ar32[2])
+                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[3], &paTests[iTest].OutVal.ar32[3]);
+                if (   uMxCsrOut != paTests[iTest].fMxcsrOut
                     || !fValsIdentical)
                     RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s'%s'%s in2=%s'%s'%s'%s\n"
@@ -5735,11 +5730,11 @@
                                  FormatR32(&paTests[iTest].InVal2.ar32[0]), FormatR32(&paTests[iTest].InVal2.ar32[1]),
                                  FormatR32(&paTests[iTest].InVal2.ar32[2]), FormatR32(&paTests[iTest].InVal2.ar32[3]),
-                                 iVar ? "  " : "", Res.MXCSR,
-                                 FormatR32(&Res.uResult.ar32[0]), FormatR32(&Res.uResult.ar32[1]),
-                                 FormatR32(&Res.uResult.ar32[2]), FormatR32(&Res.uResult.ar32[3]),
+                                 iVar ? "  " : "", uMxCsrOut,
+                                 FormatR32(&Res.ar32[0]), FormatR32(&Res.ar32[1]),
+                                 FormatR32(&Res.ar32[2]), FormatR32(&Res.ar32[3]),
                                  iVar ? "  " : "", paTests[iTest].fMxcsrOut,
                                  FormatR32(&paTests[iTest].OutVal.ar32[0]), FormatR32(&paTests[iTest].OutVal.ar32[1]),
                                  FormatR32(&paTests[iTest].OutVal.ar32[2]), FormatR32(&paTests[iTest].OutVal.ar32[3]),
-                                 MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
+                                 MxcsrDiff(uMxCsrOut, paTests[iTest].fMxcsrOut),
                                  !fValsIdentical ? " - val" : "",
                                  FormatMxcsr(paTests[iTest].fMxcsrIn) );
@@ -5786,6 +5781,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     uint32_t cMinNormalPairs       = (cTests - 144) / 4;
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64); iFn++)
@@ -5820,44 +5813,44 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResM; RT_ZERO(ResM);
-                        pfn(&State, &ResM, &TestData.InVal1, &TestData.InVal2);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResM.MXCSR;
-                        TestData.OutVal    = ResM.uResult;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
+                        X86XMMREG ResM; RT_ZERO(ResM);
+                        uint32_t uMxCsrOutM = pfn(uMxCsrIn, &ResM, &TestData.InVal1, &TestData.InVal2);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutM;
+                        TestData.OutVal    = ResM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResU; RT_ZERO(ResU);
-                        pfn(&State, &ResU, &TestData.InVal1, &TestData.InVal2);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResU.MXCSR;
-                        TestData.OutVal    = ResU.uResult;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
+                        X86XMMREG ResU; RT_ZERO(ResU);
+                        uint32_t uMxCsrOutU = pfn(uMxCsrIn, &ResU, &TestData.InVal1, &TestData.InVal2);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutU;
+                        TestData.OutVal    = ResU;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        uint16_t fXcpt = (ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
+                        uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS;
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
-                            IEMSSERESULT Res1; RT_ZERO(Res1);
-                            pfn(&State, &Res1, &TestData.InVal1, &TestData.InVal2);
-                            TestData.fMxcsrIn  = State.MXCSR;
-                            TestData.fMxcsrOut = Res1.MXCSR;
-                            TestData.OutVal    = Res1.uResult;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            X86XMMREG Res1; RT_ZERO(Res1);
+                            uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &Res1, &TestData.InVal1, &TestData.InVal2);
+                            TestData.fMxcsrIn  = uMxCsrIn;
+                            TestData.fMxcsrOut = uMxCsrOut1;
+                            TestData.OutVal    = Res1;
                             GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                            if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
+                            if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS))
                             {
-                                fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
-                                IEMSSERESULT Res2; RT_ZERO(Res2);
-                                pfn(&State, &Res2, &TestData.InVal1, &TestData.InVal2);
-                                TestData.fMxcsrIn  = State.MXCSR;
-                                TestData.fMxcsrOut = Res2.MXCSR;
-                                TestData.OutVal    = Res2.uResult;
+                                fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS;
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                X86XMMREG Res2; RT_ZERO(Res2);
+                                uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &Res2, &TestData.InVal1, &TestData.InVal2);
+                                TestData.fMxcsrIn  = uMxCsrIn;
+                                TestData.fMxcsrOut = uMxCsrOut2;
+                                TestData.OutVal    = Res2;
                                 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                             }
@@ -5866,10 +5859,10 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
-                                        IEMSSERESULT Res3; RT_ZERO(Res3);
-                                        pfn(&State, &Res3, &TestData.InVal1, &TestData.InVal2);
-                                        TestData.fMxcsrIn  = State.MXCSR;
-                                        TestData.fMxcsrOut = Res3.MXCSR;
-                                        TestData.OutVal    = Res3.uResult;
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        X86XMMREG Res3; RT_ZERO(Res3);
+                                        uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &Res3, &TestData.InVal1, &TestData.InVal2);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
+                                        TestData.fMxcsrOut = uMxCsrOut3;
+                                        TestData.OutVal    = Res3;
                                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                                     }
@@ -5887,6 +5880,4 @@
 static void SseBinaryR64Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64); iFn++)
     {
@@ -5903,11 +5894,11 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                IEMSSERESULT Res; RT_ZERO(Res);
-
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].InVal2);
-                if (   Res.MXCSR != paTests[iTest].fMxcsrOut
-                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
-                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
+                X86XMMREG Res; RT_ZERO(Res);
+
+                uint32_t uMxCsrIn = paTests[iTest].fMxcsrIn;
+                uint32_t uMxCsrOut = pfn(uMxCsrIn, &Res, &paTests[iTest].InVal1, &paTests[iTest].InVal2);
+                if (   uMxCsrOut != paTests[iTest].fMxcsrOut
+                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0])
+                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1]))
                     RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s in2=%s'%s\n"
                                           "%s               -> mxcsr=%#08x    %s'%s\n"
@@ -5916,11 +5907,11 @@
                                  FormatR64(&paTests[iTest].InVal1.ar64[0]), FormatR64(&paTests[iTest].InVal1.ar64[1]),
                                  FormatR64(&paTests[iTest].InVal2.ar64[0]), FormatR64(&paTests[iTest].InVal2.ar64[1]),
-                                 iVar ? "  " : "", Res.MXCSR,
-                                 FormatR64(&Res.uResult.ar64[0]), FormatR64(&Res.uResult.ar64[1]),
+                                 iVar ? "  " : "", uMxCsrOut,
+                                 FormatR64(&Res.ar64[0]), FormatR64(&Res.ar64[1]),
                                  iVar ? "  " : "", paTests[iTest].fMxcsrOut,
                                  FormatR64(&paTests[iTest].OutVal.ar64[0]), FormatR64(&paTests[iTest].OutVal.ar64[1]),
-                                 MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
-                                   (   !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
-                                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
+                                 MxcsrDiff(uMxCsrOut, paTests[iTest].fMxcsrOut),
+                                   (   !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0])
+                                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1]))
                                  ? " - val" : "",
                                  FormatMxcsr(paTests[iTest].fMxcsrIn) );
@@ -5963,6 +5954,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     uint32_t cMinNormalPairs       = (cTests - 144) / 4;
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R32); iFn++)
@@ -6002,44 +5991,44 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResM; RT_ZERO(ResM);
-                        pfn(&State, &ResM, &TestData.InVal1, &TestData.r32Val2);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResM.MXCSR;
-                        TestData.OutVal    = ResM.uResult;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
+                        X86XMMREG ResM; RT_ZERO(ResM);
+                        uint32_t uMxCsrOutM = pfn(uMxCsrIn, &ResM, &TestData.InVal1, &TestData.r32Val2);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutM;
+                        TestData.OutVal    = ResM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResU; RT_ZERO(ResU);
-                        pfn(&State, &ResU, &TestData.InVal1, &TestData.r32Val2);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResU.MXCSR;
-                        TestData.OutVal    = ResU.uResult;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
+                        X86XMMREG ResU; RT_ZERO(ResU);
+                        uint32_t uMxCsrOutU = pfn(uMxCsrIn, &ResU, &TestData.InVal1, &TestData.r32Val2);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutU;
+                        TestData.OutVal    = ResU;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        uint16_t fXcpt = (ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
+                        uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS;
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
-                            IEMSSERESULT Res1; RT_ZERO(Res1);
-                            pfn(&State, &Res1, &TestData.InVal1, &TestData.r32Val2);
-                            TestData.fMxcsrIn  = State.MXCSR;
-                            TestData.fMxcsrOut = Res1.MXCSR;
-                            TestData.OutVal    = Res1.uResult;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            X86XMMREG Res1; RT_ZERO(Res1);
+                            uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &Res1, &TestData.InVal1, &TestData.r32Val2);
+                            TestData.fMxcsrIn  = uMxCsrIn;
+                            TestData.fMxcsrOut = uMxCsrOut1;
+                            TestData.OutVal    = Res1;
                             GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                            if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
+                            if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS))
                             {
-                                fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
-                                IEMSSERESULT Res2; RT_ZERO(Res2);
-                                pfn(&State, &Res2, &TestData.InVal1, &TestData.r32Val2);
-                                TestData.fMxcsrIn  = State.MXCSR;
-                                TestData.fMxcsrOut = Res2.MXCSR;
-                                TestData.OutVal    = Res2.uResult;
+                                fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS;
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                X86XMMREG Res2; RT_ZERO(Res2);
+                                uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &Res2, &TestData.InVal1, &TestData.r32Val2);
+                                TestData.fMxcsrIn  = uMxCsrIn;
+                                TestData.fMxcsrOut = uMxCsrOut2;
+                                TestData.OutVal    = Res2;
                                 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                             }
@@ -6048,10 +6037,10 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
-                                        IEMSSERESULT Res3; RT_ZERO(Res3);
-                                        pfn(&State, &Res3, &TestData.InVal1, &TestData.r32Val2);
-                                        TestData.fMxcsrIn  = State.MXCSR;
-                                        TestData.fMxcsrOut = Res3.MXCSR;
-                                        TestData.OutVal    = Res3.uResult;
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        X86XMMREG Res3; RT_ZERO(Res3);
+                                        uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &Res3, &TestData.InVal1, &TestData.r32Val2);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
+                                        TestData.fMxcsrOut = uMxCsrOut3;
+                                        TestData.OutVal    = Res3;
                                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                                     }
@@ -6068,6 +6057,4 @@
 static void SseBinaryU128R32Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R32); iFn++)
     {
@@ -6084,13 +6071,13 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                IEMSSERESULT Res; RT_ZERO(Res);
-
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].r32Val2);
-                bool fValsIdentical =    RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[0], &paTests[iTest].OutVal.ar32[0])
-                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[1], &paTests[iTest].OutVal.ar32[1])
-                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[2], &paTests[iTest].OutVal.ar32[2])
-                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]);
-                if (   Res.MXCSR != paTests[iTest].fMxcsrOut
+                X86XMMREG Res; RT_ZERO(Res);
+
+                uint32_t uMxCsrIn = paTests[iTest].fMxcsrIn;
+                uint32_t uMxCsrOut = pfn(uMxCsrIn, &Res, &paTests[iTest].InVal1, &paTests[iTest].r32Val2);
+                bool fValsIdentical =    RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[0], &paTests[iTest].OutVal.ar32[0])
+                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[1], &paTests[iTest].OutVal.ar32[1])
+                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[2], &paTests[iTest].OutVal.ar32[2])
+                                      && RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[3], &paTests[iTest].OutVal.ar32[3]);
+                if (   uMxCsrOut != paTests[iTest].fMxcsrOut
                     || !fValsIdentical)
                     RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s'%s'%s in2=%s\n"
@@ -6101,11 +6088,11 @@
                                  FormatR32(&paTests[iTest].InVal1.ar32[2]), FormatR32(&paTests[iTest].InVal1.ar32[3]),
                                  FormatR32(&paTests[iTest].r32Val2),
-                                 iVar ? "  " : "", Res.MXCSR,
-                                 FormatR32(&Res.uResult.ar32[0]), FormatR32(&Res.uResult.ar32[1]),
-                                 FormatR32(&Res.uResult.ar32[2]), FormatR32(&Res.uResult.ar32[3]),
+                                 iVar ? "  " : "", uMxCsrOut,
+                                 FormatR32(&Res.ar32[0]), FormatR32(&Res.ar32[1]),
+                                 FormatR32(&Res.ar32[2]), FormatR32(&Res.ar32[3]),
                                  iVar ? "  " : "", paTests[iTest].fMxcsrOut,
                                  FormatR32(&paTests[iTest].OutVal.ar32[0]), FormatR32(&paTests[iTest].OutVal.ar32[1]),
                                  FormatR32(&paTests[iTest].OutVal.ar32[2]), FormatR32(&paTests[iTest].OutVal.ar32[3]),
-                                 MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
+                                 MxcsrDiff(uMxCsrOut, paTests[iTest].fMxcsrOut),
                                  !fValsIdentical ? " - val" : "",
                                  FormatMxcsr(paTests[iTest].fMxcsrIn) );
@@ -6147,6 +6134,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     uint32_t cMinNormalPairs       = (cTests - 144) / 4;
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R64); iFn++)
@@ -6180,44 +6165,36 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResM; RT_ZERO(ResM);
-                        pfn(&State, &ResM, &TestData.InVal1, &TestData.r64Val2);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResM.MXCSR;
-                        TestData.OutVal    = ResM.uResult;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrOutM = pfn(uMxCsrIn, &TestData.OutVal, &TestData.InVal1, &TestData.r64Val2);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResU; RT_ZERO(ResU);
-                        pfn(&State, &ResU, &TestData.InVal1, &TestData.r64Val2);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResU.MXCSR;
-                        TestData.OutVal    = ResU.uResult;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrOutU = pfn(uMxCsrIn, &TestData.OutVal, &TestData.InVal1, &TestData.r64Val2);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutU;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        uint16_t fXcpt = (ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
+                        uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS;
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
-                            IEMSSERESULT Res1; RT_ZERO(Res1);
-                            pfn(&State, &Res1, &TestData.InVal1, &TestData.r64Val2);
-                            TestData.fMxcsrIn  = State.MXCSR;
-                            TestData.fMxcsrOut = Res1.MXCSR;
-                            TestData.OutVal    = Res1.uResult;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.InVal1, &TestData.r64Val2);
+                            TestData.fMxcsrIn  = uMxCsrIn;
+                            TestData.fMxcsrOut = uMxCsrOut1;
                             GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                            if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
+                            if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS))
                             {
-                                fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
-                                IEMSSERESULT Res2; RT_ZERO(Res2);
-                                pfn(&State, &Res2, &TestData.InVal1, &TestData.r64Val2);
-                                TestData.fMxcsrIn  = State.MXCSR;
-                                TestData.fMxcsrOut = Res2.MXCSR;
-                                TestData.OutVal    = Res2.uResult;
+                                fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS;
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.InVal1, &TestData.r64Val2);
+                                TestData.fMxcsrIn  = uMxCsrIn;
+                                TestData.fMxcsrOut = uMxCsrOut2;
                                 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                             }
@@ -6226,10 +6203,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
-                                        IEMSSERESULT Res3; RT_ZERO(Res3);
-                                        pfn(&State, &Res3, &TestData.InVal1, &TestData.r64Val2);
-                                        TestData.fMxcsrIn  = State.MXCSR;
-                                        TestData.fMxcsrOut = Res3.MXCSR;
-                                        TestData.OutVal    = Res3.uResult;
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.InVal1, &TestData.r64Val2);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
+                                        TestData.fMxcsrOut = uMxCsrOut3;
                                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                                     }
@@ -6247,6 +6222,4 @@
 static void SseBinaryU128R64Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryU128R64); iFn++)
     {
@@ -6263,11 +6236,11 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                IEMSSERESULT Res; RT_ZERO(Res);
-
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &Res, &paTests[iTest].InVal1, &paTests[iTest].r64Val2);
-                if (   Res.MXCSR != paTests[iTest].fMxcsrOut
-                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
-                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
+                X86XMMREG Res; RT_ZERO(Res);
+
+                uint32_t uMxCsrIn = paTests[iTest].fMxcsrIn;
+                uint32_t uMxCsrOut = pfn(uMxCsrIn, &Res, &paTests[iTest].InVal1, &paTests[iTest].r64Val2);
+                if (   uMxCsrOut != paTests[iTest].fMxcsrOut
+                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0])
+                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1]))
                     RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s in2=%s\n"
                                           "%s               -> mxcsr=%#08x    %s'%s\n"
@@ -6276,11 +6249,11 @@
                                  FormatR64(&paTests[iTest].InVal1.ar64[0]), FormatR64(&paTests[iTest].InVal1.ar64[1]),
                                  FormatR64(&paTests[iTest].r64Val2),
-                                 iVar ? "  " : "", Res.MXCSR,
-                                 FormatR64(&Res.uResult.ar64[0]), FormatR64(&Res.uResult.ar64[1]),
+                                 iVar ? "  " : "", uMxCsrOut,
+                                 FormatR64(&Res.ar64[0]), FormatR64(&Res.ar64[1]),
                                  iVar ? "  " : "", paTests[iTest].fMxcsrOut,
                                  FormatR64(&paTests[iTest].OutVal.ar64[0]), FormatR64(&paTests[iTest].OutVal.ar64[1]),
-                                 MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
-                                   (   !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
-                                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
+                                 MxcsrDiff(uMxCsrOut, paTests[iTest].fMxcsrOut),
+                                   (   !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0])
+                                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1]))
                                  ? " - val" : "",
                                  FormatMxcsr(paTests[iTest].fMxcsrIn) );
@@ -6316,6 +6289,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     uint32_t cMinNormalPairs       = (cTests - 144) / 4;
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI32R64); iFn++)
@@ -6346,20 +6317,20 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrM; int32_t i32OutM;
-                        pfn(&State, &fMxcsrM, &i32OutM, &TestData.r64ValIn.u);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrM = pfn(uMxCsrIn, &i32OutM, &TestData.r64ValIn.u);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrM;
                         TestData.i32ValOut = i32OutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrU; int32_t i32OutU;
-                        pfn(&State, &fMxcsrU, &i32OutU, &TestData.r64ValIn.u);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrU = pfn(uMxCsrIn, &i32OutU, &TestData.r64ValIn.u);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrU;
                         TestData.i32ValOut = i32OutU;
@@ -6369,8 +6340,8 @@
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
                             uint32_t fMxcsr1; int32_t i32Out1;
-                            pfn(&State, &fMxcsr1, &i32Out1, &TestData.r64ValIn.u);
-                            TestData.fMxcsrIn  = State.MXCSR;
+                            fMxcsr1 = pfn(uMxCsrIn, &i32Out1, &TestData.r64ValIn.u);
+                            TestData.fMxcsrIn  = uMxCsrIn;
                             TestData.fMxcsrOut = fMxcsr1;
                             TestData.i32ValOut = i32Out1;
@@ -6380,8 +6351,8 @@
                             {
                                 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
                                 uint32_t fMxcsr2; int32_t i32Out2;
-                                pfn(&State, &fMxcsr2, &i32Out2, &TestData.r64ValIn.u);
-                                TestData.fMxcsrIn  = State.MXCSR;
+                                fMxcsr2 = pfn(uMxCsrIn, &i32Out2, &TestData.r64ValIn.u);
+                                TestData.fMxcsrIn  = uMxCsrIn;
                                 TestData.fMxcsrOut = fMxcsr2;
                                 TestData.i32ValOut = i32Out2;
@@ -6392,8 +6363,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
                                         uint32_t fMxcsr3; int32_t i32Out3;
-                                        pfn(&State, &fMxcsr3, &i32Out3, &TestData.r64ValIn.u);
-                                        TestData.fMxcsrIn  = State.MXCSR;
+                                        fMxcsr3 = pfn(uMxCsrIn, &i32Out3, &TestData.r64ValIn.u);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
                                         TestData.fMxcsrOut = fMxcsr3;
                                         TestData.i32ValOut = i32Out3;
@@ -6429,9 +6400,7 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                uint32_t fMxcsr = 0;
                 int32_t i32Dst = 0;
 
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &fMxcsr, &i32Dst, &paTests[iTest].r64ValIn.u);
+                uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &i32Dst, &paTests[iTest].r64ValIn.u);
                 if (   fMxcsr != paTests[iTest].fMxcsrOut
                     || i32Dst != paTests[iTest].i32ValOut)
@@ -6478,6 +6447,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     uint32_t cMinNormalPairs       = (cTests - 144) / 4;
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI64R64); iFn++)
@@ -6508,20 +6475,20 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrM; int64_t i64OutM;
-                        pfn(&State, &fMxcsrM, &i64OutM, &TestData.r64ValIn.u);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrM = pfn(uMxCsrIn, &i64OutM, &TestData.r64ValIn.u);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrM;
                         TestData.i64ValOut = i64OutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrU; int64_t i64OutU;
-                        pfn(&State, &fMxcsrU, &i64OutU, &TestData.r64ValIn.u);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrU =pfn(uMxCsrIn, &i64OutU, &TestData.r64ValIn.u);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrU;
                         TestData.i64ValOut = i64OutU;
@@ -6531,8 +6498,8 @@
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
                             uint32_t fMxcsr1; int64_t i64Out1;
-                            pfn(&State, &fMxcsr1, &i64Out1, &TestData.r64ValIn.u);
-                            TestData.fMxcsrIn  = State.MXCSR;
+                            fMxcsr1 = pfn(uMxCsrIn, &i64Out1, &TestData.r64ValIn.u);
+                            TestData.fMxcsrIn  = uMxCsrIn;
                             TestData.fMxcsrOut = fMxcsr1;
                             TestData.i64ValOut = i64Out1;
@@ -6542,8 +6509,8 @@
                             {
                                 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
                                 uint32_t fMxcsr2; int64_t i64Out2;
-                                pfn(&State, &fMxcsr2, &i64Out2, &TestData.r64ValIn.u);
-                                TestData.fMxcsrIn  = State.MXCSR;
+                                fMxcsr2 = pfn(uMxCsrIn, &i64Out2, &TestData.r64ValIn.u);
+                                TestData.fMxcsrIn  = uMxCsrIn;
                                 TestData.fMxcsrOut = fMxcsr2;
                                 TestData.i64ValOut = i64Out2;
@@ -6554,8 +6521,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
                                         uint32_t fMxcsr3; int64_t i64Out3;
-                                        pfn(&State, &fMxcsr3, &i64Out3, &TestData.r64ValIn.u);
-                                        TestData.fMxcsrIn  = State.MXCSR;
+                                        fMxcsr3 = pfn(uMxCsrIn, &i64Out3, &TestData.r64ValIn.u);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
                                         TestData.fMxcsrOut = fMxcsr3;
                                         TestData.i64ValOut = i64Out3;
@@ -6591,9 +6558,6 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                uint32_t fMxcsr = 0;
                 int64_t i64Dst = 0;
-
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &fMxcsr, &i64Dst, &paTests[iTest].r64ValIn.u);
+                uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &i64Dst, &paTests[iTest].r64ValIn.u);
                 if (   fMxcsr != paTests[iTest].fMxcsrOut
                     || i64Dst != paTests[iTest].i64ValOut)
@@ -6640,6 +6604,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     uint32_t cMinNormalPairs       = (cTests - 144) / 4;
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryI32R32); iFn++)
@@ -6670,20 +6632,20 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrM; int32_t i32OutM;
-                        pfn(&State, &fMxcsrM, &i32OutM, &TestData.r32ValIn.u);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrM = pfn(uMxCsrIn, &i32OutM, &TestData.r32ValIn.u);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrM;
                         TestData.i32ValOut = i32OutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrU; int32_t i32OutU;
-                        pfn(&State, &fMxcsrU, &i32OutU, &TestData.r32ValIn.u);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrU = pfn(uMxCsrIn, &i32OutU, &TestData.r32ValIn.u);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrU;
                         TestData.i32ValOut = i32OutU;
@@ -6693,8 +6655,8 @@
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
                             uint32_t fMxcsr1; int32_t i32Out1;
-                            pfn(&State, &fMxcsr1, &i32Out1, &TestData.r32ValIn.u);
-                            TestData.fMxcsrIn  = State.MXCSR;
+                            fMxcsr1 = pfn(uMxCsrIn, &i32Out1, &TestData.r32ValIn.u);
+                            TestData.fMxcsrIn  = uMxCsrIn;
                             TestData.fMxcsrOut = fMxcsr1;
                             TestData.i32ValOut = i32Out1;
@@ -6704,8 +6666,8 @@
                             {
                                 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
                                 uint32_t fMxcsr2; int32_t i32Out2;
-                                pfn(&State, &fMxcsr2, &i32Out2, &TestData.r32ValIn.u);
-                                TestData.fMxcsrIn  = State.MXCSR;
+                                fMxcsr2 = pfn(uMxCsrIn, &i32Out2, &TestData.r32ValIn.u);
+                                TestData.fMxcsrIn  = uMxCsrIn;
                                 TestData.fMxcsrOut = fMxcsr2;
                                 TestData.i32ValOut = i32Out2;
@@ -6716,8 +6678,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
                                         uint32_t fMxcsr3; int32_t i32Out3;
-                                        pfn(&State, &fMxcsr3, &i32Out3, &TestData.r32ValIn.u);
-                                        TestData.fMxcsrIn  = State.MXCSR;
+                                        fMxcsr3 = pfn(uMxCsrIn, &i32Out3, &TestData.r32ValIn.u);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
                                         TestData.fMxcsrOut = fMxcsr3;
                                         TestData.i32ValOut = i32Out3;
@@ -6753,9 +6715,7 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                uint32_t fMxcsr = 0;
                 int32_t i32Dst = 0;
 
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &fMxcsr, &i32Dst, &paTests[iTest].r32ValIn.u);
+                uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &i32Dst, &paTests[iTest].r32ValIn.u);
                 if (   fMxcsr != paTests[iTest].fMxcsrOut
                     || i32Dst != paTests[iTest].i32ValOut)
@@ -6832,11 +6792,11 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrM; int64_t i64OutM;
-                        pfn(&State, &fMxcsrM, &i64OutM, &TestData.r32ValIn.u);
+                        fMxcsrM = pfn(uMxCsrIn, &i64OutM, &TestData.r32ValIn.u);
                         TestData.fMxcsrIn  = State.MXCSR;
                         TestData.fMxcsrOut = fMxcsrM;
@@ -6844,7 +6804,7 @@
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrU; int64_t i64OutU;
-                        pfn(&State, &fMxcsrU, &i64OutU, &TestData.r32ValIn.u);
+                        fMxcsrU = pfn(uMxCsrIn, &i64OutU, &TestData.r32ValIn.u);
                         TestData.fMxcsrIn  = State.MXCSR;
                         TestData.fMxcsrOut = fMxcsrU;
@@ -6855,7 +6815,7 @@
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
                             uint32_t fMxcsr1; int64_t i64Out1;
-                            pfn(&State, &fMxcsr1, &i64Out1, &TestData.r32ValIn.u);
+                            fMxcsr1 = pfn(uMxCsrIn, &i64Out1, &TestData.r32ValIn.u);
                             TestData.fMxcsrIn  = State.MXCSR;
                             TestData.fMxcsrOut = fMxcsr1;
@@ -6866,7 +6826,7 @@
                             {
                                 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
                                 uint32_t fMxcsr2; int64_t i64Out2;
-                                pfn(&State, &fMxcsr2, &i64Out2, &TestData.r32ValIn.u);
+                                fMxcsr2 = pfn(uMxCsrIn, &i64Out2, &TestData.r32ValIn.u);
                                 TestData.fMxcsrIn  = State.MXCSR;
                                 TestData.fMxcsrOut = fMxcsr2;
@@ -6878,7 +6838,7 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
                                         uint32_t fMxcsr3; int64_t i64Out3;
-                                        pfn(&State, &fMxcsr3, &i64Out3, &TestData.r32ValIn.u);
+                                        fMxcsr3 = pfn(uMxCsrIn, &i64Out3, &TestData.r32ValIn.u);
                                         TestData.fMxcsrIn  = State.MXCSR;
                                         TestData.fMxcsrOut = fMxcsr3;
@@ -6915,9 +6875,7 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                uint32_t fMxcsr = 0;
                 int64_t i64Dst = 0;
 
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &fMxcsr, &i64Dst, &paTests[iTest].r32ValIn.u);
+                uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &i64Dst, &paTests[iTest].r32ValIn.u);
                 if (   fMxcsr != paTests[iTest].fMxcsrOut
                     || i64Dst != paTests[iTest].i64ValOut)
@@ -6964,6 +6922,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I32); iFn++)
     {
@@ -6984,20 +6940,20 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrM; RTFLOAT64U r64OutM;
-                        pfn(&State, &fMxcsrM, &r64OutM, &TestData.i32ValIn);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrM = pfn(uMxCsrIn, &r64OutM, &TestData.i32ValIn);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrM;
                         TestData.r64ValOut = r64OutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrU; RTFLOAT64U r64OutU;
-                        pfn(&State, &fMxcsrU, &r64OutU, &TestData.i32ValIn);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrU = pfn(uMxCsrIn, &r64OutU, &TestData.i32ValIn);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrU;
                         TestData.r64ValOut = r64OutU;
@@ -7007,8 +6963,8 @@
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
                             uint32_t fMxcsr1; RTFLOAT64U r64Out1;
-                            pfn(&State, &fMxcsr1, &r64Out1, &TestData.i32ValIn);
-                            TestData.fMxcsrIn  = State.MXCSR;
+                            fMxcsr1 = pfn(uMxCsrIn, &r64Out1, &TestData.i32ValIn);
+                            TestData.fMxcsrIn  = uMxCsrIn;
                             TestData.fMxcsrOut = fMxcsr1;
                             TestData.r64ValOut = r64Out1;
@@ -7018,8 +6974,8 @@
                             {
                                 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
                                 uint32_t fMxcsr2; RTFLOAT64U r64Out2;
-                                pfn(&State, &fMxcsr2, &r64Out2, &TestData.i32ValIn);
-                                TestData.fMxcsrIn  = State.MXCSR;
+                                fMxcsr2 = pfn(uMxCsrIn, &r64Out2, &TestData.i32ValIn);
+                                TestData.fMxcsrIn  = uMxCsrIn;
                                 TestData.fMxcsrOut = fMxcsr2;
                                 TestData.r64ValOut = r64Out2;
@@ -7030,8 +6986,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
                                         uint32_t fMxcsr3; RTFLOAT64U r64Out3;
-                                        pfn(&State, &fMxcsr3, &r64Out3, &TestData.i32ValIn);
-                                        TestData.fMxcsrIn  = State.MXCSR;
+                                        fMxcsr3 = pfn(uMxCsrIn, &r64Out3, &TestData.i32ValIn);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
                                         TestData.fMxcsrOut = fMxcsr3;
                                         TestData.r64ValOut = r64Out3;
@@ -7051,6 +7007,4 @@
 static void SseBinaryR64I32Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I32); iFn++)
     {
@@ -7067,9 +7021,7 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                uint32_t fMxcsr = 0;
                 RTFLOAT64U r64Dst; RT_ZERO(r64Dst);
 
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &fMxcsr, &r64Dst, &paTests[iTest].i32ValIn);
+                uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &r64Dst, &paTests[iTest].i32ValIn);
                 if (   fMxcsr != paTests[iTest].fMxcsrOut
                     || !RTFLOAT64U_ARE_IDENTICAL(&r64Dst, &paTests[iTest].r64ValOut))
@@ -7116,6 +7068,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I64); iFn++)
     {
@@ -7136,20 +7086,20 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrM; RTFLOAT64U r64OutM;
-                        pfn(&State, &fMxcsrM, &r64OutM, &TestData.i64ValIn);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrM = pfn(uMxCsrIn, &r64OutM, &TestData.i64ValIn);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrM;
                         TestData.r64ValOut = r64OutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrU; RTFLOAT64U r64OutU;
-                        pfn(&State, &fMxcsrU, &r64OutU, &TestData.i64ValIn);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrU = pfn(uMxCsrIn, &r64OutU, &TestData.i64ValIn);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrU;
                         TestData.r64ValOut = r64OutU;
@@ -7159,8 +7109,8 @@
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
                             uint32_t fMxcsr1; RTFLOAT64U r64Out1;
-                            pfn(&State, &fMxcsr1, &r64Out1, &TestData.i64ValIn);
-                            TestData.fMxcsrIn  = State.MXCSR;
+                            fMxcsr1 = pfn(uMxCsrIn, &r64Out1, &TestData.i64ValIn);
+                            TestData.fMxcsrIn  = uMxCsrIn;
                             TestData.fMxcsrOut = fMxcsr1;
                             TestData.r64ValOut = r64Out1;
@@ -7170,8 +7120,8 @@
                             {
                                 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
                                 uint32_t fMxcsr2; RTFLOAT64U r64Out2;
-                                pfn(&State, &fMxcsr2, &r64Out2, &TestData.i64ValIn);
-                                TestData.fMxcsrIn  = State.MXCSR;
+                                fMxcsr2 = pfn(uMxCsrIn, &r64Out2, &TestData.i64ValIn);
+                                TestData.fMxcsrIn  = uMxCsrIn;
                                 TestData.fMxcsrOut = fMxcsr2;
                                 TestData.r64ValOut = r64Out2;
@@ -7182,8 +7132,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
                                         uint32_t fMxcsr3; RTFLOAT64U r64Out3;
-                                        pfn(&State, &fMxcsr3, &r64Out3, &TestData.i64ValIn);
-                                        TestData.fMxcsrIn  = State.MXCSR;
+                                        fMxcsr3 = pfn(uMxCsrIn, &r64Out3, &TestData.i64ValIn);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
                                         TestData.fMxcsrOut = fMxcsr3;
                                         TestData.r64ValOut = r64Out3;
@@ -7203,6 +7153,4 @@
 static void SseBinaryR64I64Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR64I64); iFn++)
     {
@@ -7219,9 +7167,7 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                uint32_t fMxcsr = 0;
                 RTFLOAT64U r64Dst; RT_ZERO(r64Dst);
 
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &fMxcsr, &r64Dst, &paTests[iTest].i64ValIn);
+                uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &r64Dst, &paTests[iTest].i64ValIn);
                 if (   fMxcsr != paTests[iTest].fMxcsrOut
                     || !RTFLOAT64U_ARE_IDENTICAL(&r64Dst, &paTests[iTest].r64ValOut))
@@ -7268,6 +7214,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I32); iFn++)
     {
@@ -7288,20 +7232,20 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrM; RTFLOAT32U r32OutM;
-                        pfn(&State, &fMxcsrM, &r32OutM, &TestData.i32ValIn);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrM = pfn(uMxCsrIn, &r32OutM, &TestData.i32ValIn);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrM;
                         TestData.r32ValOut = r32OutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrU; RTFLOAT32U r32OutU;
-                        pfn(&State, &fMxcsrU, &r32OutU, &TestData.i32ValIn);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrU = pfn(uMxCsrIn, &r32OutU, &TestData.i32ValIn);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrU;
                         TestData.r32ValOut = r32OutU;
@@ -7311,8 +7255,8 @@
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
                             uint32_t fMxcsr1; RTFLOAT32U r32Out1;
-                            pfn(&State, &fMxcsr1, &r32Out1, &TestData.i32ValIn);
-                            TestData.fMxcsrIn  = State.MXCSR;
+                            fMxcsr1 = pfn(uMxCsrIn, &r32Out1, &TestData.i32ValIn);
+                            TestData.fMxcsrIn  = uMxCsrIn;
                             TestData.fMxcsrOut = fMxcsr1;
                             TestData.r32ValOut = r32Out1;
@@ -7322,8 +7266,8 @@
                             {
                                 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
                                 uint32_t fMxcsr2; RTFLOAT32U r32Out2;
-                                pfn(&State, &fMxcsr2, &r32Out2, &TestData.i32ValIn);
-                                TestData.fMxcsrIn  = State.MXCSR;
+                                fMxcsr2 = pfn(uMxCsrIn, &r32Out2, &TestData.i32ValIn);
+                                TestData.fMxcsrIn  = uMxCsrIn;
                                 TestData.fMxcsrOut = fMxcsr2;
                                 TestData.r32ValOut = r32Out2;
@@ -7334,8 +7278,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
                                         uint32_t fMxcsr3; RTFLOAT32U r32Out3;
-                                        pfn(&State, &fMxcsr3, &r32Out3, &TestData.i32ValIn);
-                                        TestData.fMxcsrIn  = State.MXCSR;
+                                        fMxcsr3 = pfn(uMxCsrIn, &r32Out3, &TestData.i32ValIn);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
                                         TestData.fMxcsrOut = fMxcsr3;
                                         TestData.r32ValOut = r32Out3;
@@ -7355,6 +7299,4 @@
 static void SseBinaryR32I32Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I32); iFn++)
     {
@@ -7371,9 +7313,7 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                uint32_t fMxcsr = 0;
                 RTFLOAT32U r32Dst; RT_ZERO(r32Dst);
 
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &fMxcsr, &r32Dst, &paTests[iTest].i32ValIn);
+                uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &r32Dst, &paTests[iTest].i32ValIn);
                 if (   fMxcsr != paTests[iTest].fMxcsrOut
                     || !RTFLOAT32U_ARE_IDENTICAL(&r32Dst, &paTests[iTest].r32ValOut))
@@ -7420,6 +7360,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I64); iFn++)
     {
@@ -7440,20 +7378,20 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrM; RTFLOAT32U r32OutM;
-                        pfn(&State, &fMxcsrM, &r32OutM, &TestData.i64ValIn);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrM = pfn(uMxCsrIn, &r32OutM, &TestData.i64ValIn);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrM;
                         TestData.r32ValOut = r32OutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
                         uint32_t fMxcsrU; RTFLOAT32U r32OutU;
-                        pfn(&State, &fMxcsrU, &r32OutU, &TestData.i64ValIn);
-                        TestData.fMxcsrIn  = State.MXCSR;
+                        fMxcsrU = pfn(uMxCsrIn, &r32OutU, &TestData.i64ValIn);
+                        TestData.fMxcsrIn  = uMxCsrIn;
                         TestData.fMxcsrOut = fMxcsrU;
                         TestData.r32ValOut = r32OutU;
@@ -7463,8 +7401,8 @@
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
                             uint32_t fMxcsr1; RTFLOAT32U r32Out1;
-                            pfn(&State, &fMxcsr1, &r32Out1, &TestData.i64ValIn);
-                            TestData.fMxcsrIn  = State.MXCSR;
+                            fMxcsr1 = pfn(uMxCsrIn, &r32Out1, &TestData.i64ValIn);
+                            TestData.fMxcsrIn  = uMxCsrIn;
                             TestData.fMxcsrOut = fMxcsr1;
                             TestData.r32ValOut = r32Out1;
@@ -7474,8 +7412,8 @@
                             {
                                 fXcpt |= fMxcsr1 & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
                                 uint32_t fMxcsr2; RTFLOAT32U r32Out2;
-                                pfn(&State, &fMxcsr2, &r32Out2, &TestData.i64ValIn);
-                                TestData.fMxcsrIn  = State.MXCSR;
+                                fMxcsr2 = pfn(uMxCsrIn, &r32Out2, &TestData.i64ValIn);
+                                TestData.fMxcsrIn  = uMxCsrIn;
                                 TestData.fMxcsrOut = fMxcsr2;
                                 TestData.r32ValOut = r32Out2;
@@ -7486,8 +7424,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
                                         uint32_t fMxcsr3; RTFLOAT32U r32Out3;
-                                        pfn(&State, &fMxcsr3, &r32Out3, &TestData.i64ValIn);
-                                        TestData.fMxcsrIn  = State.MXCSR;
+                                        fMxcsr3 = pfn(uMxCsrIn, &r32Out3, &TestData.i64ValIn);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
                                         TestData.fMxcsrOut = fMxcsr3;
                                         TestData.r32ValOut = r32Out3;
@@ -7507,6 +7445,4 @@
 static void SseBinaryR32I64Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseBinaryR32I64); iFn++)
     {
@@ -7523,9 +7459,7 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                uint32_t fMxcsr = 0;
                 RTFLOAT32U r32Dst; RT_ZERO(r32Dst);
 
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &fMxcsr, &r32Dst, &paTests[iTest].i64ValIn);
+                uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &r32Dst, &paTests[iTest].i64ValIn);
                 if (   fMxcsr != paTests[iTest].fMxcsrOut
                     || !RTFLOAT32U_ARE_IDENTICAL(&r32Dst, &paTests[iTest].r32ValOut))
@@ -7624,5 +7558,5 @@
                         uint32_t fMxcsrM  = fMxcsrIn;
                         uint32_t fEFlagsM = fEFlags;
-                        pfn(&fMxcsrM, &fEFlagsM, &ValIn1, &ValIn2);
+                        fMxcsrM = pfn(fMxcsrIn, &fEFlagsM, &ValIn1, &ValIn2);
                         TestData.fMxcsrIn   = fMxcsrIn;
                         TestData.fMxcsrOut  = fMxcsrM;
@@ -7634,5 +7568,5 @@
                         uint32_t fMxcsrU  = fMxcsrIn;
                         uint32_t fEFlagsU = fEFlags;
-                        pfn(&fMxcsrU, &fEFlagsU, &ValIn1, &ValIn2);
+                        fMxcsrU = pfn(fMxcsrIn, &fEFlagsU, &ValIn1, &ValIn2);
                         TestData.fMxcsrIn   = fMxcsrIn;
                         TestData.fMxcsrOut  = fMxcsrU;
@@ -7647,5 +7581,5 @@
                             uint32_t fMxcsr1  = fMxcsrIn;
                             uint32_t fEFlags1 = fEFlags;
-                            pfn(&fMxcsr1, &fEFlags1, &ValIn1, &ValIn2);
+                            fMxcsr1 = pfn(fMxcsrIn, &fEFlags1, &ValIn1, &ValIn2);
                             TestData.fMxcsrIn   = fMxcsrIn;
                             TestData.fMxcsrOut  = fMxcsr1;
@@ -7660,5 +7594,5 @@
                                 uint32_t fMxcsr2  = fMxcsrIn;
                                 uint32_t fEFlags2 = fEFlags;
-                                pfn(&fMxcsr2, &fEFlags2, &ValIn1, &ValIn2);
+                                fMxcsr2 = pfn(fMxcsrIn, &fEFlags2, &ValIn1, &ValIn2);
                                 TestData.fMxcsrIn   = fMxcsrIn;
                                 TestData.fMxcsrOut  = fMxcsr2;
@@ -7674,5 +7608,5 @@
                                         uint32_t fMxcsr3  = fMxcsrIn;
                                         uint32_t fEFlags3 = fEFlags;
-                                        pfn(&fMxcsr3, &fEFlags3, &ValIn1, &ValIn2);
+                                        fMxcsr3 = pfn(fMxcsrIn, &fEFlags3, &ValIn1, &ValIn2);
                                         TestData.fMxcsrIn   = fMxcsrIn;
                                         TestData.fMxcsrOut  = fMxcsr3;
@@ -7712,7 +7646,6 @@
                 ValIn1.ar32[0] = paTests[iTest].r32ValIn1;
                 ValIn2.ar32[0] = paTests[iTest].r32ValIn2;
-                uint32_t fMxcsr = paTests[iTest].fMxcsrIn;
                 uint32_t fEFlags = paTests[iTest].fEflIn;
-                pfn(&fMxcsr, &fEFlags, &ValIn1, &ValIn2);
+                uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &fEFlags, &ValIn1, &ValIn2);
                 if (   fMxcsr != paTests[iTest].fMxcsrOut
                     || fEFlags != paTests[iTest].fEflOut)
@@ -7810,5 +7743,5 @@
                         uint32_t fMxcsrM  = fMxcsrIn;
                         uint32_t fEFlagsM = fEFlags;
-                        pfn(&fMxcsrM, &fEFlagsM, &ValIn1, &ValIn2);
+                        fMxcsrM = pfn(fMxcsrIn, &fEFlagsM, &ValIn1, &ValIn2);
                         TestData.fMxcsrIn   = fMxcsrIn;
                         TestData.fMxcsrOut  = fMxcsrM;
@@ -7820,5 +7753,5 @@
                         uint32_t fMxcsrU  = fMxcsrIn;
                         uint32_t fEFlagsU = fEFlags;
-                        pfn(&fMxcsrU, &fEFlagsU, &ValIn1, &ValIn2);
+                        fMxcsrU = pfn(fMxcsrIn, &fEFlagsU, &ValIn1, &ValIn2);
                         TestData.fMxcsrIn   = fMxcsrIn;
                         TestData.fMxcsrOut  = fMxcsrU;
@@ -7833,5 +7766,5 @@
                             uint32_t fMxcsr1  = fMxcsrIn;
                             uint32_t fEFlags1 = fEFlags;
-                            pfn(&fMxcsr1, &fEFlags1, &ValIn1, &ValIn2);
+                            fMxcsr1 = pfn(fMxcsrIn, &fEFlags1, &ValIn1, &ValIn2);
                             TestData.fMxcsrIn   = fMxcsrIn;
                             TestData.fMxcsrOut  = fMxcsr1;
@@ -7846,5 +7779,5 @@
                                 uint32_t fMxcsr2  = fMxcsrIn;
                                 uint32_t fEFlags2 = fEFlags;
-                                pfn(&fMxcsr2, &fEFlags2, &ValIn1, &ValIn2);
+                                fMxcsr2 = pfn(fMxcsrIn, &fEFlags2, &ValIn1, &ValIn2);
                                 TestData.fMxcsrIn   = fMxcsrIn;
                                 TestData.fMxcsrOut  = fMxcsr2;
@@ -7860,5 +7793,5 @@
                                         uint32_t fMxcsr3  = fMxcsrIn;
                                         uint32_t fEFlags3 = fEFlags;
-                                        pfn(&fMxcsr3, &fEFlags3, &ValIn1, &ValIn2);
+                                        fMxcsr3 = pfn(fMxcsrIn, &fEFlags3, &ValIn1, &ValIn2);
                                         TestData.fMxcsrIn   = fMxcsrIn;
                                         TestData.fMxcsrOut  = fMxcsr3;
@@ -7898,7 +7831,6 @@
                 ValIn1.ar64[0] = paTests[iTest].r64ValIn1;
                 ValIn2.ar64[0] = paTests[iTest].r64ValIn2;
-                uint32_t fMxcsr = paTests[iTest].fMxcsrIn;
                 uint32_t fEFlags = paTests[iTest].fEflIn;
-                pfn(&fMxcsr, &fEFlags, &ValIn1, &ValIn2);
+                uint32_t fMxcsr = pfn(paTests[iTest].fMxcsrIn, &fEFlags, &ValIn1, &ValIn2);
                 if (   fMxcsr != paTests[iTest].fMxcsrOut
                     || fEFlags != paTests[iTest].fEflOut)
@@ -8355,6 +8287,4 @@
         AssertReturn(GENERATE_BINARY_OPEN(&BinOut, papszNameFmts, g_aSseConvertXmmI32R32[iFn]), RTEXITCODE_FAILURE);
 
-        X86FXSTATE State;
-        RT_ZERO(State);
         for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
         {
@@ -8371,44 +8301,36 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResM; RT_ZERO(ResM);
-                        pfn(&State, &ResM, &ResM.uResult, &TestData.InVal);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResM.MXCSR;
-                        TestData.OutVal    = ResM.uResult;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrOutM = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResU; RT_ZERO(ResU);
-                        pfn(&State, &ResU, &ResU.uResult, &TestData.InVal);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResU.MXCSR;
-                        TestData.OutVal    = ResU.uResult;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrOutU = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutU;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        uint16_t fXcpt = (ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
+                        uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS;
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
-                            IEMSSERESULT Res1; RT_ZERO(Res1);
-                            pfn(&State, &Res1, &Res1.uResult, &TestData.InVal);
-                            TestData.fMxcsrIn  = State.MXCSR;
-                            TestData.fMxcsrOut = Res1.MXCSR;
-                            TestData.OutVal    = Res1.uResult;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                            TestData.fMxcsrIn  = uMxCsrIn;
+                            TestData.fMxcsrOut = uMxCsrOut1;
                             GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                            if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
+                            if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS))
                             {
-                                fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
-                                IEMSSERESULT Res2; RT_ZERO(Res2);
-                                pfn(&State, &Res2, &Res2.uResult, &TestData.InVal);
-                                TestData.fMxcsrIn  = State.MXCSR;
-                                TestData.fMxcsrOut = Res2.MXCSR;
-                                TestData.OutVal    = Res2.uResult;
+                                fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS;
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                                TestData.fMxcsrIn  = uMxCsrIn;
+                                TestData.fMxcsrOut = uMxCsrOut2;
                                 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                             }
@@ -8417,10 +8339,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
-                                        IEMSSERESULT Res3; RT_ZERO(Res3);
-                                        pfn(&State, &Res3, &Res3.uResult, &TestData.InVal);
-                                        TestData.fMxcsrIn  = State.MXCSR;
-                                        TestData.fMxcsrOut = Res3.MXCSR;
-                                        TestData.OutVal    = Res3.uResult;
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
+                                        TestData.fMxcsrOut = uMxCsrOut3;
                                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                                     }
@@ -8437,7 +8357,4 @@
 static void SseConvertXmmI32R32Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
-
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmI32R32); iFn++)
     {
@@ -8454,13 +8371,12 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                IEMSSERESULT Res; RT_ZERO(Res);
-
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal);
-                if (   Res.MXCSR != paTests[iTest].fMxcsrOut
-                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[0], &paTests[iTest].OutVal.ar32[0])
-                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[1], &paTests[iTest].OutVal.ar32[1])
-                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[2], &paTests[iTest].OutVal.ar32[2])
-                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]))
+                X86XMMREG Res; RT_ZERO(Res);
+
+                uint32_t fMxCsr = pfn(paTests[iTest].fMxcsrIn, &Res, &Res, &paTests[iTest].InVal);
+                if (   fMxCsr != paTests[iTest].fMxcsrOut
+                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[0], &paTests[iTest].OutVal.ar32[0])
+                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[1], &paTests[iTest].OutVal.ar32[1])
+                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[2], &paTests[iTest].OutVal.ar32[2])
+                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[3], &paTests[iTest].OutVal.ar32[3]))
                     RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI32'%RI32'%RI32'%RI32 \n"
                                           "%s               -> mxcsr=%#08x    %s'%s'%s'%s\n"
@@ -8469,15 +8385,15 @@
                                  paTests[iTest].InVal.ai32[0], paTests[iTest].InVal.ai32[1],
                                  paTests[iTest].InVal.ai32[2], paTests[iTest].InVal.ai32[3],
-                                 iVar ? "  " : "", Res.MXCSR,
-                                 FormatR32(&Res.uResult.ar32[0]), FormatR32(&Res.uResult.ar32[1]),
-                                 FormatR32(&Res.uResult.ar32[2]), FormatR32(&Res.uResult.ar32[3]),
+                                 iVar ? "  " : "", fMxCsr,
+                                 FormatR32(&Res.ar32[0]), FormatR32(&Res.ar32[1]),
+                                 FormatR32(&Res.ar32[2]), FormatR32(&Res.ar32[3]),
                                  iVar ? "  " : "", paTests[iTest].fMxcsrOut,
                                  FormatR32(&paTests[iTest].OutVal.ar32[0]), FormatR32(&paTests[iTest].OutVal.ar32[1]),
                                  FormatR32(&paTests[iTest].OutVal.ar32[2]), FormatR32(&paTests[iTest].OutVal.ar32[3]),
-                                 MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
-                                   (   !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[0], &paTests[iTest].OutVal.ar32[0])
-                                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[1], &paTests[iTest].OutVal.ar32[1])
-                                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[2], &paTests[iTest].OutVal.ar32[2])
-                                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.uResult.ar32[3], &paTests[iTest].OutVal.ar32[3]))
+                                 MxcsrDiff(fMxCsr, paTests[iTest].fMxcsrOut),
+                                   (   !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[0], &paTests[iTest].OutVal.ar32[0])
+                                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[1], &paTests[iTest].OutVal.ar32[1])
+                                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[2], &paTests[iTest].OutVal.ar32[2])
+                                    || !RTFLOAT32U_ARE_IDENTICAL(&Res.ar32[3], &paTests[iTest].OutVal.ar32[3]))
                                  ? " - val" : "",
                                  FormatMxcsr(paTests[iTest].fMxcsrIn));
@@ -8514,6 +8430,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     uint32_t cMinNormalPairs       = (cTests - 144) / 4;
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR32I32); iFn++)
@@ -8550,44 +8464,36 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResM; RT_ZERO(ResM);
-                        pfn(&State, &ResM, &ResM.uResult, &TestData.InVal);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResM.MXCSR;
-                        TestData.OutVal    = ResM.uResult;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrOutM = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResU; RT_ZERO(ResU);
-                        pfn(&State, &ResU, &ResU.uResult, &TestData.InVal);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResU.MXCSR;
-                        TestData.OutVal    = ResU.uResult;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrOutU = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutU;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        uint16_t fXcpt = (ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
+                        uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS;
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
-                            IEMSSERESULT Res1; RT_ZERO(Res1);
-                            pfn(&State, &Res1, &Res1.uResult, &TestData.InVal);
-                            TestData.fMxcsrIn  = State.MXCSR;
-                            TestData.fMxcsrOut = Res1.MXCSR;
-                            TestData.OutVal    = Res1.uResult;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                            TestData.fMxcsrIn  = uMxCsrIn;
+                            TestData.fMxcsrOut = uMxCsrOut1;
                             GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                            if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
+                            if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS))
                             {
-                                fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
-                                IEMSSERESULT Res2; RT_ZERO(Res2);
-                                pfn(&State, &Res2, &Res2.uResult, &TestData.InVal);
-                                TestData.fMxcsrIn  = State.MXCSR;
-                                TestData.fMxcsrOut = Res2.MXCSR;
-                                TestData.OutVal    = Res2.uResult;
+                                fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS;
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                                TestData.fMxcsrIn  = uMxCsrIn;
+                                TestData.fMxcsrOut = uMxCsrOut2;
                                 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                             }
@@ -8596,10 +8502,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
-                                        IEMSSERESULT Res3; RT_ZERO(Res3);
-                                        pfn(&State, &Res3, &Res3.uResult, &TestData.InVal);
-                                        TestData.fMxcsrIn  = State.MXCSR;
-                                        TestData.fMxcsrOut = Res3.MXCSR;
-                                        TestData.OutVal    = Res3.uResult;
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
+                                        TestData.fMxcsrOut = uMxCsrOut3;
                                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                                     }
@@ -8616,7 +8520,4 @@
 static void SseConvertXmmR32I32Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
-
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR32I32); iFn++)
     {
@@ -8633,13 +8534,12 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                IEMSSERESULT Res; RT_ZERO(Res);
-
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal);
-                if (   Res.MXCSR != paTests[iTest].fMxcsrOut
-                    || Res.uResult.ai32[0] != paTests[iTest].OutVal.ai32[0]
-                    || Res.uResult.ai32[1] != paTests[iTest].OutVal.ai32[1]
-                    || Res.uResult.ai32[2] != paTests[iTest].OutVal.ai32[2]
-                    || Res.uResult.ai32[3] != paTests[iTest].OutVal.ai32[3])
+                X86XMMREG Res; RT_ZERO(Res);
+
+                uint32_t fMxCsr = pfn(paTests[iTest].fMxcsrIn, &Res, &Res, &paTests[iTest].InVal);
+                if (   fMxCsr != paTests[iTest].fMxcsrOut
+                    || Res.ai32[0] != paTests[iTest].OutVal.ai32[0]
+                    || Res.ai32[1] != paTests[iTest].OutVal.ai32[1]
+                    || Res.ai32[2] != paTests[iTest].OutVal.ai32[2]
+                    || Res.ai32[3] != paTests[iTest].OutVal.ai32[3])
                     RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s'%s'%s \n"
                                           "%s               -> mxcsr=%#08x    %RI32'%RI32'%RI32'%RI32\n"
@@ -8648,15 +8548,15 @@
                                  FormatR32(&paTests[iTest].InVal.ar32[0]), FormatR32(&paTests[iTest].InVal.ar32[1]),
                                  FormatR32(&paTests[iTest].InVal.ar32[2]), FormatR32(&paTests[iTest].InVal.ar32[3]),
-                                 iVar ? "  " : "", Res.MXCSR,
-                                 Res.uResult.ai32[0], Res.uResult.ai32[1],
-                                 Res.uResult.ai32[2], Res.uResult.ai32[3],
+                                 iVar ? "  " : "", fMxCsr,
+                                 Res.ai32[0], Res.ai32[1],
+                                 Res.ai32[2], Res.ai32[3],
                                  iVar ? "  " : "", paTests[iTest].fMxcsrOut,
                                  paTests[iTest].OutVal.ai32[0], paTests[iTest].OutVal.ai32[1],
                                  paTests[iTest].OutVal.ai32[2], paTests[iTest].OutVal.ai32[3],
-                                 MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
-                                   (   Res.uResult.ai32[0] != paTests[iTest].OutVal.ai32[0]
-                                    || Res.uResult.ai32[1] != paTests[iTest].OutVal.ai32[1]
-                                    || Res.uResult.ai32[2] != paTests[iTest].OutVal.ai32[2]
-                                    || Res.uResult.ai32[3] != paTests[iTest].OutVal.ai32[3])
+                                 MxcsrDiff(fMxCsr, paTests[iTest].fMxcsrOut),
+                                   (   Res.ai32[0] != paTests[iTest].OutVal.ai32[0]
+                                    || Res.ai32[1] != paTests[iTest].OutVal.ai32[1]
+                                    || Res.ai32[2] != paTests[iTest].OutVal.ai32[2]
+                                    || Res.ai32[3] != paTests[iTest].OutVal.ai32[3])
                                  ? " - val" : "",
                                  FormatMxcsr(paTests[iTest].fMxcsrIn));
@@ -8701,6 +8601,4 @@
         AssertReturn(GENERATE_BINARY_OPEN(&BinOut, papszNameFmts, g_aSseConvertXmmI32R64[iFn]), RTEXITCODE_FAILURE);
 
-        X86FXSTATE State;
-        RT_ZERO(State);
         for (uint32_t iTest = 0; iTest < cTests + RT_ELEMENTS(s_aSpecials); iTest += 1)
         {
@@ -8717,44 +8615,36 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResM; RT_ZERO(ResM);
-                        pfn(&State, &ResM, &ResM.uResult, &TestData.InVal);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResM.MXCSR;
-                        TestData.OutVal    = ResM.uResult;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrOutM = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResU; RT_ZERO(ResU);
-                        pfn(&State, &ResU, &ResU.uResult, &TestData.InVal);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResU.MXCSR;
-                        TestData.OutVal    = ResU.uResult;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrOutU = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutU;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        uint16_t fXcpt = (ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
+                        uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS;
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
-                            IEMSSERESULT Res1; RT_ZERO(Res1);
-                            pfn(&State, &Res1, &Res1.uResult, &TestData.InVal);
-                            TestData.fMxcsrIn  = State.MXCSR;
-                            TestData.fMxcsrOut = Res1.MXCSR;
-                            TestData.OutVal    = Res1.uResult;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                            TestData.fMxcsrIn  = uMxCsrIn;
+                            TestData.fMxcsrOut = uMxCsrOut1;
                             GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                            if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
+                            if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS))
                             {
-                                fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
-                                IEMSSERESULT Res2; RT_ZERO(Res2);
-                                pfn(&State, &Res2, &Res2.uResult, &TestData.InVal);
-                                TestData.fMxcsrIn  = State.MXCSR;
-                                TestData.fMxcsrOut = Res2.MXCSR;
-                                TestData.OutVal    = Res2.uResult;
+                                fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS;
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                                TestData.fMxcsrIn  = uMxCsrIn;
+                                TestData.fMxcsrOut = uMxCsrOut2;
                                 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                             }
@@ -8763,10 +8653,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
-                                        IEMSSERESULT Res3; RT_ZERO(Res3);
-                                        pfn(&State, &Res3, &Res3.uResult, &TestData.InVal);
-                                        TestData.fMxcsrIn  = State.MXCSR;
-                                        TestData.fMxcsrOut = Res3.MXCSR;
-                                        TestData.OutVal    = Res3.uResult;
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
+                                        TestData.fMxcsrOut = uMxCsrOut3;
                                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                                     }
@@ -8783,7 +8671,4 @@
 static void SseConvertXmmI32R64Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
-
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmI32R64); iFn++)
     {
@@ -8800,11 +8685,10 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                IEMSSERESULT Res; RT_ZERO(Res);
-
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal);
-                if (   Res.MXCSR != paTests[iTest].fMxcsrOut
-                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
-                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
+                X86XMMREG Res; RT_ZERO(Res);
+
+                uint32_t fMxCsr = pfn(paTests[iTest].fMxcsrIn, &Res, &Res, &paTests[iTest].InVal);
+                if (   fMxCsr != paTests[iTest].fMxcsrOut
+                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0])
+                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1]))
                     RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%RI32'%RI32'%RI32'%RI32 \n"
                                           "%s               -> mxcsr=%#08x    %s'%s\n"
@@ -8813,11 +8697,11 @@
                                  paTests[iTest].InVal.ai32[0], paTests[iTest].InVal.ai32[1],
                                  paTests[iTest].InVal.ai32[2], paTests[iTest].InVal.ai32[3],
-                                 iVar ? "  " : "", Res.MXCSR,
-                                 FormatR64(&Res.uResult.ar64[0]), FormatR64(&Res.uResult.ar64[1]),
+                                 iVar ? "  " : "", fMxCsr,
+                                 FormatR64(&Res.ar64[0]), FormatR64(&Res.ar64[1]),
                                  iVar ? "  " : "", paTests[iTest].fMxcsrOut,
                                  FormatR64(&paTests[iTest].OutVal.ar64[0]), FormatR64(&paTests[iTest].OutVal.ar64[1]),
-                                 MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
-                                   (   !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[0], &paTests[iTest].OutVal.ar64[0])
-                                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.uResult.ar64[1], &paTests[iTest].OutVal.ar64[1]))
+                                 MxcsrDiff(fMxCsr, paTests[iTest].fMxcsrOut),
+                                   (   !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[0], &paTests[iTest].OutVal.ar64[0])
+                                    || !RTFLOAT64U_ARE_IDENTICAL(&Res.ar64[1], &paTests[iTest].OutVal.ar64[1]))
                                  ? " - val" : "",
                                  FormatMxcsr(paTests[iTest].fMxcsrIn));
@@ -8854,6 +8738,4 @@
     };
 
-    X86FXSTATE State;
-    RT_ZERO(State);
     uint32_t cMinNormalPairs       = (cTests - 144) / 4;
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR64I32); iFn++)
@@ -8886,44 +8768,36 @@
                     for (uint8_t iFz = 0; iFz < 2; iFz++)
                     {
-                        State.MXCSR = (fMxcsr & ~X86_MXCSR_RC_MASK)
-                                    | (iRounding  << X86_MXCSR_RC_SHIFT)
-                                    | (iDaz ? X86_MXCSR_DAZ : 0)
-                                    | (iFz  ? X86_MXCSR_FZ  : 0)
-                                    | X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResM; RT_ZERO(ResM);
-                        pfn(&State, &ResM, &ResM.uResult, &TestData.InVal);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResM.MXCSR;
-                        TestData.OutVal    = ResM.uResult;
+                        uint32_t uMxCsrIn = (fMxcsr & ~X86_MXCSR_RC_MASK)
+                                          | (iRounding  << X86_MXCSR_RC_SHIFT)
+                                          | (iDaz ? X86_MXCSR_DAZ : 0)
+                                          | (iFz  ? X86_MXCSR_FZ  : 0)
+                                          | X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrOutM = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutM;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        State.MXCSR = State.MXCSR & ~X86_MXCSR_XCPT_MASK;
-                        IEMSSERESULT ResU; RT_ZERO(ResU);
-                        pfn(&State, &ResU, &ResU.uResult, &TestData.InVal);
-                        TestData.fMxcsrIn  = State.MXCSR;
-                        TestData.fMxcsrOut = ResU.MXCSR;
-                        TestData.OutVal    = ResU.uResult;
+                        uMxCsrIn = uMxCsrIn & ~X86_MXCSR_XCPT_MASK;
+                        uint32_t uMxCsrOutU = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                        TestData.fMxcsrIn  = uMxCsrIn;
+                        TestData.fMxcsrOut = uMxCsrOutU;
                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                        uint16_t fXcpt = (ResM.MXCSR | ResU.MXCSR) & X86_MXCSR_XCPT_FLAGS;
+                        uint16_t fXcpt = (uMxCsrOutM | uMxCsrOutU) & X86_MXCSR_XCPT_FLAGS;
                         if (fXcpt)
                         {
-                            State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | fXcpt;
-                            IEMSSERESULT Res1; RT_ZERO(Res1);
-                            pfn(&State, &Res1, &Res1.uResult, &TestData.InVal);
-                            TestData.fMxcsrIn  = State.MXCSR;
-                            TestData.fMxcsrOut = Res1.MXCSR;
-                            TestData.OutVal    = Res1.uResult;
+                            uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | fXcpt;
+                            uint32_t uMxCsrOut1 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                            TestData.fMxcsrIn  = uMxCsrIn;
+                            TestData.fMxcsrOut = uMxCsrOut1;
                             GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
 
-                            if (((Res1.MXCSR & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (Res1.MXCSR & X86_MXCSR_XCPT_FLAGS))
+                            if (((uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS) & fXcpt) != (uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS))
                             {
-                                fXcpt |= Res1.MXCSR & X86_MXCSR_XCPT_FLAGS;
-                                State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
-                                IEMSSERESULT Res2; RT_ZERO(Res2);
-                                pfn(&State, &Res2, &Res2.uResult, &TestData.InVal);
-                                TestData.fMxcsrIn  = State.MXCSR;
-                                TestData.fMxcsrOut = Res2.MXCSR;
-                                TestData.OutVal    = Res2.uResult;
+                                fXcpt |= uMxCsrOut1 & X86_MXCSR_XCPT_FLAGS;
+                                uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | (fXcpt << X86_MXCSR_XCPT_MASK_SHIFT);
+                                uint32_t uMxCsrOut2 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                                TestData.fMxcsrIn  = uMxCsrIn;
+                                TestData.fMxcsrOut = uMxCsrOut2;
                                 GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                             }
@@ -8932,10 +8806,8 @@
                                     if (fUnmasked & fXcpt)
                                     {
-                                        State.MXCSR = (State.MXCSR & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
-                                        IEMSSERESULT Res3; RT_ZERO(Res3);
-                                        pfn(&State, &Res3, &Res3.uResult, &TestData.InVal);
-                                        TestData.fMxcsrIn  = State.MXCSR;
-                                        TestData.fMxcsrOut = Res3.MXCSR;
-                                        TestData.OutVal    = Res3.uResult;
+                                        uMxCsrIn = (uMxCsrIn & ~X86_MXCSR_XCPT_MASK) | ((fXcpt & ~fUnmasked) << X86_MXCSR_XCPT_MASK_SHIFT);
+                                        uint32_t uMxCsrOut3 = pfn(uMxCsrIn, &TestData.OutVal, &TestData.OutVal, &TestData.InVal);
+                                        TestData.fMxcsrIn  = uMxCsrIn;
+                                        TestData.fMxcsrOut = uMxCsrOut3;
                                         GenerateBinaryWrite(&BinOut, &TestData, sizeof(TestData));
                                     }
@@ -8952,7 +8824,4 @@
 static void SseConvertXmmR64I32Test(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
-
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertXmmR64I32); iFn++)
     {
@@ -8969,13 +8838,12 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++)
             {
-                IEMSSERESULT Res; RT_ZERO(Res);
-
-                State.MXCSR = paTests[iTest].fMxcsrIn;
-                pfn(&State, &Res, &Res.uResult, &paTests[iTest].InVal);
-                if (   Res.MXCSR != paTests[iTest].fMxcsrOut
-                    || Res.uResult.ai32[0] != paTests[iTest].OutVal.ai32[0]
-                    || Res.uResult.ai32[1] != paTests[iTest].OutVal.ai32[1]
-                    || Res.uResult.ai32[2] != paTests[iTest].OutVal.ai32[2]
-                    || Res.uResult.ai32[3] != paTests[iTest].OutVal.ai32[3])
+                X86XMMREG Res; RT_ZERO(Res);
+
+                uint32_t fMxCsr = pfn(paTests[iTest].fMxcsrIn, &Res, &Res, &paTests[iTest].InVal);
+                if (   fMxCsr != paTests[iTest].fMxcsrOut
+                    || Res.ai32[0] != paTests[iTest].OutVal.ai32[0]
+                    || Res.ai32[1] != paTests[iTest].OutVal.ai32[1]
+                    || Res.ai32[2] != paTests[iTest].OutVal.ai32[2]
+                    || Res.ai32[3] != paTests[iTest].OutVal.ai32[3])
                     RTTestFailed(g_hTest, "#%04u%s: mxcsr=%#08x in1=%s'%s \n"
                                           "%s               -> mxcsr=%#08x    %RI32'%RI32'%RI32'%RI32\n"
@@ -8983,15 +8851,15 @@
                                  iTest, iVar ? "/n" : "", paTests[iTest].fMxcsrIn,
                                  FormatR64(&paTests[iTest].InVal.ar64[0]), FormatR64(&paTests[iTest].InVal.ar64[1]),
-                                 iVar ? "  " : "", Res.MXCSR,
-                                 Res.uResult.ai32[0], Res.uResult.ai32[1],
-                                 Res.uResult.ai32[2], Res.uResult.ai32[3],
+                                 iVar ? "  " : "", fMxCsr,
+                                 Res.ai32[0], Res.ai32[1],
+                                 Res.ai32[2], Res.ai32[3],
                                  iVar ? "  " : "", paTests[iTest].fMxcsrOut,
                                  paTests[iTest].OutVal.ai32[0], paTests[iTest].OutVal.ai32[1],
                                  paTests[iTest].OutVal.ai32[2], paTests[iTest].OutVal.ai32[3],
-                                 MxcsrDiff(Res.MXCSR, paTests[iTest].fMxcsrOut),
-                                   (   Res.uResult.ai32[0] != paTests[iTest].OutVal.ai32[0]
-                                    || Res.uResult.ai32[1] != paTests[iTest].OutVal.ai32[1]
-                                    || Res.uResult.ai32[2] != paTests[iTest].OutVal.ai32[2]
-                                    || Res.uResult.ai32[3] != paTests[iTest].OutVal.ai32[3])
+                                 MxcsrDiff(fMxCsr, paTests[iTest].fMxcsrOut),
+                                   (   Res.ai32[0] != paTests[iTest].OutVal.ai32[0]
+                                    || Res.ai32[1] != paTests[iTest].OutVal.ai32[1]
+                                    || Res.ai32[2] != paTests[iTest].OutVal.ai32[2]
+                                    || Res.ai32[3] != paTests[iTest].OutVal.ai32[3])
                                  ? " - val" : "",
                                  FormatMxcsr(paTests[iTest].fMxcsrIn));
@@ -9131,7 +8999,4 @@
 static void SseConvertMmXmmTest(void)
 {
-    X86FXSTATE State;
-    RT_ZERO(State);
-
     for (size_t iFn = 0; iFn < RT_ELEMENTS(g_aSseConvertMmXmm); iFn++)
     {
Index: trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
===================================================================
--- trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp	(revision 104128)
+++ trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp	(revision 104129)
@@ -1078,4 +1078,6 @@
 #define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
     do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
+#define IEM_MC_CALL_AVX_AIMPL_NEW_3(a_pfnAImpl, a0, a1, a2) \
+    do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (void)fMcBegin; } while (0)
 #define IEM_MC_CALL_AVX_AIMPL_4(a_pfnAImpl, a0, a1, a2, a3) \
     do { (void)fAvxHost; (void)fAvxWrite; CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0)
