Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py	(revision 104182)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py	(revision 104183)
@@ -3162,5 +3162,4 @@
     'IEM_MC_IF_GREG_BIT_SET':                                    (McBlock.parseMcGenericCond,       True,  False, True,  ),
     'IEM_MC_IF_LOCAL_IS_Z':                                      (McBlock.parseMcGenericCond,       True,  False, True,  ),
-    'IEM_MC_IF_MXCSR_XCPT_PENDING':                              (McBlock.parseMcGenericCond,       True,  True,  g_fNativeSimd),
     'IEM_MC_IF_RCX_IS_NZ':                                       (McBlock.parseMcGenericCond,       True,  False, True,  ),
     'IEM_MC_IF_RCX_IS_NOT_ONE':                                  (McBlock.parseMcGenericCond,       True,  False, True,  ),
@@ -3261,5 +3260,4 @@
     'IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO':                          (McBlock.parseMcGeneric,           True,  True,  False, ),
     'IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED':                    (McBlock.parseMcGeneric,           True,  True,  True,  ),
-    'IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT':                   (McBlock.parseMcGeneric,           True,  True,  True,  ),
     'IEM_MC_REF_EFLAGS':                                         (McBlock.parseMcGeneric,           False, False, True,  ),
     'IEM_MC_REF_FPUREG':                                         (McBlock.parseMcGeneric,           False, False, False, ),
Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h	(revision 104182)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h	(revision 104183)
@@ -3487,9 +3487,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtpi2ps_u128, pDst, u64Src);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3517,9 +3514,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtpi2ps_u128, pDst, u64Src);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3552,9 +3546,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtpi2pd_u128, pDst, u64Src);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3582,9 +3573,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtpi2pd_u128, pDst, u64Src);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3616,9 +3604,6 @@
             IEM_MC_REF_GREG_I64_CONST(pi64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i64, pr32Dst, pi64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3642,9 +3627,6 @@
             IEM_MC_FETCH_MEM_I64(i64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i64, pr32Dst, pi64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3668,9 +3650,6 @@
             IEM_MC_REF_GREG_I32_CONST(pi32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i32, pr32Dst, pi32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3694,9 +3673,6 @@
             IEM_MC_FETCH_MEM_I32(i32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2ss_r32_i32, pr32Dst, pi32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3729,9 +3705,6 @@
             IEM_MC_REF_GREG_I64_CONST(pi64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i64, pr64Dst, pi64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3755,9 +3728,6 @@
             IEM_MC_FETCH_MEM_I64(i64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i64, pr64Dst, pi64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3781,9 +3751,5 @@
             IEM_MC_REF_GREG_I32_CONST(pi32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i32, pr64Dst, pi32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3807,9 +3773,5 @@
             IEM_MC_FETCH_MEM_I32(i32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsi2sd_r64_i32, pr64Dst, pi32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3923,9 +3885,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttps2pi_u128, pu64Dst, u64Src);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3952,9 +3911,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttps2pi_u128, pu64Dst, u64Src);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3986,9 +3942,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttpd2pi_u128, pu64Dst, pSrc);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4016,9 +3969,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttpd2pi_u128, pu64Dst, pSrc);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4050,9 +4000,6 @@
             IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i64_r32, pi64Dst, pu32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4076,9 +4023,6 @@
             IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i64_r32, pi64Dst, pu32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4102,9 +4046,6 @@
             IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i32_r32, pi32Dst, pu32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4128,9 +4069,6 @@
             IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttss2si_i32_r32, pi32Dst, pu32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4163,9 +4101,6 @@
             IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i64_r64, pi64Dst, pu64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4189,9 +4124,6 @@
             IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i64_r64, pi64Dst, pu64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4215,9 +4147,6 @@
             IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i32_r64, pi32Dst, pu64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4241,9 +4170,6 @@
             IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvttsd2si_i32_r64, pi32Dst, pu64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4277,9 +4203,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtps2pi_u128, pu64Dst, u64Src);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4306,9 +4229,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtps2pi_u128, pu64Dst, u64Src);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4341,9 +4261,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtpd2pi_u128, pu64Dst, pSrc);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4371,9 +4288,6 @@
 
         IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtpd2pi_u128, pu64Dst, pSrc);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4405,9 +4319,6 @@
             IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i64_r32, pi64Dst, pu32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4431,9 +4342,6 @@
             IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i64_r32, pi64Dst, pu32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4457,9 +4365,6 @@
             IEM_MC_REF_XREG_U32_CONST(pu32Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i32_r32,  pi32Dst, pu32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4483,9 +4388,6 @@
             IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtss2si_i32_r32, pi32Dst, pu32Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4518,9 +4420,6 @@
             IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i64_r64, pi64Dst, pu64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4544,9 +4443,6 @@
             IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i64_r64, pi64Dst, pu64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4570,9 +4466,6 @@
             IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i32_r64, pi32Dst, pu64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4596,9 +4489,6 @@
             IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
             IEM_MC_CALL_SSE_AIMPL_2(iemAImpl_cvtsd2si_i32_r64, pi32Dst, pu64Src);
-            IEM_MC_IF_MXCSR_XCPT_PENDING() {
-                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-            } IEM_MC_ELSE() {
-                IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
-            } IEM_MC_ENDIF();
+            IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst);
 
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4636,9 +4526,6 @@
         IEM_MC_FETCH_XREG_R32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iDWord*/);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomiss_u128, pEFlags, uSrc1, uSrc2);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_COMMIT_EFLAGS(fEFlags);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_COMMIT_EFLAGS(fEFlags);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4666,9 +4553,6 @@
         IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomiss_u128, pEFlags, uSrc1, uSrc2);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_COMMIT_EFLAGS(fEFlags);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_COMMIT_EFLAGS(fEFlags);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4705,9 +4589,6 @@
         IEM_MC_FETCH_XREG_R64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm),  0 /*a_iQWord*/);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomisd_u128, pEFlags, uSrc1, uSrc2);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_COMMIT_EFLAGS(fEFlags);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_COMMIT_EFLAGS(fEFlags);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4735,9 +4616,6 @@
         IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_ucomisd_u128, pEFlags, uSrc1, uSrc2);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_COMMIT_EFLAGS(fEFlags);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_COMMIT_EFLAGS(fEFlags);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4778,9 +4656,6 @@
         IEM_MC_FETCH_XREG_R32(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm),  0 /*a_iDWord*/);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comiss_u128, pEFlags, uSrc1, uSrc2);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_COMMIT_EFLAGS(fEFlags);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_COMMIT_EFLAGS(fEFlags);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4808,9 +4683,6 @@
         IEM_MC_FETCH_XREG_R32(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDWord*/);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comiss_u128, pEFlags, uSrc1, uSrc2);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_COMMIT_EFLAGS(fEFlags);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_COMMIT_EFLAGS(fEFlags);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4847,9 +4719,6 @@
         IEM_MC_FETCH_XREG_R64(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm),  0 /*a_iQWord*/);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comisd_u128, pEFlags, uSrc1, uSrc2);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_COMMIT_EFLAGS(fEFlags);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_COMMIT_EFLAGS(fEFlags);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -4877,9 +4746,6 @@
         IEM_MC_FETCH_XREG_R64(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQWord*/);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_comisd_u128, pEFlags, uSrc1, uSrc2);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_COMMIT_EFLAGS(fEFlags);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_COMMIT_EFLAGS(fEFlags);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11792,9 +11658,6 @@
         IEM_MC_FETCH_XREG_PAIR_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cmpps_u128, pDst, pSrc, bImmArg);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11822,9 +11685,6 @@
         IEM_MC_FETCH_MEM_XMM_ALIGN_SSE_AND_XREG_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cmpps_u128, pDst, pSrc, bImmArg);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11857,9 +11717,6 @@
         IEM_MC_FETCH_XREG_PAIR_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cmppd_u128, pDst, pSrc, bImmArg);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11887,9 +11744,6 @@
         IEM_MC_FETCH_MEM_XMM_ALIGN_SSE_AND_XREG_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cmppd_u128, pDst, pSrc, bImmArg);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11922,9 +11776,6 @@
         IEM_MC_FETCH_XREG_PAIR_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cmpss_u128, pDst, pSrc, bImmArg);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11953,9 +11804,6 @@
                                               0 /*a_iDword*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cmpss_u128, pDst, pSrc, bImmArg);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -11988,9 +11836,6 @@
         IEM_MC_FETCH_XREG_PAIR_XMM(Src, IEM_GET_MODRM_REG(pVCpu, bRm), IEM_GET_MODRM_RM(pVCpu, bRm));
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cmpsd_u128, pDst, pSrc, bImmArg);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -12019,9 +11864,6 @@
                                               0 /*a_iQword */, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
         IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cmpsd_u128, pDst, pSrc, bImmArg);
-        IEM_MC_IF_MXCSR_XCPT_PENDING() {
-            IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
-        } IEM_MC_ELSE() {
-            IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst);
-        } IEM_MC_ENDIF();
+        IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+        IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst);
 
         IEM_MC_ADVANCE_RIP_AND_FINISH();
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp	(revision 104182)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp	(revision 104183)
@@ -466,5 +466,4 @@
 #define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr)        IEM_LIVENESS_MARK_XCPT_OR_CALL()
 #define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT()             IEM_LIVENESS_MARK_XCPT_OR_CALL(); IEM_LIVENESS_CR4_INPUT() /** @todo revisit when implemented. */
-#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT()                   IEM_LIVENESS_MARK_XCPT_OR_CALL(); IEM_LIVENESS_CR4_INPUT()
 
 #define IEM_MC_LOCAL(a_Type, a_Name)                                NOP()
@@ -1172,5 +1171,4 @@
 #define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) {
 #define IEM_MC_IF_FCW_IM()                              {
-#define IEM_MC_IF_MXCSR_XCPT_PENDING()                  {
 
 #define IEM_MC_ELSE()                                   } /*else*/ {
Index: trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h	(revision 104182)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h	(revision 104183)
@@ -1194,51 +1194,4 @@
 
 
-#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
-    off = iemNativeEmitRaiseSseAvxSimdFpXcpt(pReNative, off, pCallEntry->idxInstr)
-
-/**
- * Emits code to raise a SIMD floating point (either \#UD or \#XF) should be raised.
- *
- * @returns New code buffer offset, UINT32_MAX on failure.
- * @param   pReNative       The native recompile state.
- * @param   off             The code buffer offset.
- * @param   idxInstr        The current instruction.
- */
-DECL_INLINE_THROW(uint32_t)
-iemNativeEmitRaiseSseAvxSimdFpXcpt(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr)
-{
-    /*
-     * Make sure we don't have any outstanding guest register writes as we may
-     * raise an \#UD or \#NM and all guest register must be up to date in CPUMCTX.
-     */
-    off = iemNativeRegFlushPendingWrites(pReNative, off);
-
-#ifdef IEMNATIVE_WITH_INSTRUCTION_COUNTING
-    off = iemNativeEmitStoreImmToVCpuU8(pReNative, off, idxInstr, RT_UOFFSETOF(VMCPUCC, iem.s.idxTbCurInstr));
-#else
-    RT_NOREF(idxInstr);
-#endif
-
-    /* Allocate a temporary CR4 register. */
-    uint8_t const idxCr4Reg       = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_Cr4, kIemNativeGstRegUse_ReadOnly);
-    uint8_t const idxLabelRaiseXf = iemNativeLabelCreate(pReNative, kIemNativeLabelType_RaiseXf);
-    uint8_t const idxLabelRaiseUd = iemNativeLabelCreate(pReNative, kIemNativeLabelType_RaiseUd);
-
-    /*
-     * if (!(cr4 & X86_CR4_OSXMMEEXCPT))
-     *     return raisexcpt();
-     */
-    off = iemNativeEmitTestBitInGprAndJmpToLabelIfNotSet(pReNative, off, idxCr4Reg, X86_CR4_OSXMMEEXCPT_BIT, idxLabelRaiseXf);
-
-    /* raise \#UD exception unconditionally. */
-    off = iemNativeEmitJmpToLabel(pReNative, off, idxLabelRaiseUd);
-
-    /* Free but don't flush the CR4 register. */
-    iemNativeRegFreeTmp(pReNative, idxCr4Reg);
-
-    return off;
-}
-
-
 #define IEM_MC_RAISE_DIVIDE_ERROR() \
     off = iemNativeEmitRaiseDivideError(pReNative, off, pCallEntry->idxInstr)
@@ -2089,43 +2042,4 @@
 }
 
-
-#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-
-#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
-    off = iemNativeEmitIfMxcsrXcptPending(pReNative, off); \
-    do {
-
-/** Emits code for IEM_MC_IF_MXCSR_XCPT_PENDING. */
-DECL_INLINE_THROW(uint32_t)
-iemNativeEmitIfMxcsrXcptPending(PIEMRECOMPILERSTATE pReNative, uint32_t off)
-{
-    PIEMNATIVECOND const pEntry = iemNativeCondPushIf(pReNative, &off);
-
-    uint8_t const idxGstMxcsrReg = iemNativeRegAllocTmpForGuestReg(pReNative, &off, kIemNativeGstReg_MxCsr,
-                                                                   kIemNativeGstRegUse_Calculation);
-    uint8_t const idxRegTmp      = iemNativeRegAllocTmp(pReNative, &off);
-
-    /* mov tmp0, mxcsr */
-    off = iemNativeEmitLoadGprFromGpr(pReNative, off, idxRegTmp, idxGstMxcsrReg);
-    /* tmp0 &= X86_MXCSR_XCPT_FLAGS */
-    off = iemNativeEmitAndGprByImm(pReNative, off, idxRegTmp, X86_MXCSR_XCPT_FLAGS);
-    /* mxcsr &= X86_MXCSR_XCPT_MASK */
-    off = iemNativeEmitAndGprByImm(pReNative, off, idxGstMxcsrReg, X86_MXCSR_XCPT_MASK);
-    /* mxcsr ~= mxcsr */
-    off = iemNativeEmitInvBitsGpr(pReNative, off, idxGstMxcsrReg, idxGstMxcsrReg);
-    /* mxcsr >>= X86_MXCSR_XCPT_MASK_SHIFT */
-    off = iemNativeEmitShiftGprRight(pReNative, off, idxGstMxcsrReg, X86_MXCSR_XCPT_MASK_SHIFT);
-    /* tmp0 &= mxcsr */
-    off = iemNativeEmitAndGprByGpr(pReNative, off, idxRegTmp, idxGstMxcsrReg);
-
-    off = iemNativeEmitTestIfGprIsZeroAndJmpToLabel(pReNative, off, idxRegTmp, true /*f64Bit*/, pEntry->idxLabelElse);
-    iemNativeRegFreeTmp(pReNative, idxGstMxcsrReg);
-    iemNativeRegFreeTmp(pReNative, idxRegTmp);
-
-    iemNativeCondStartIfBlock(pReNative, off);
-    return off;
-}
-
-#endif
 
 
Index: trunk/src/VBox/VMM/include/IEMMc.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMMc.h	(revision 104182)
+++ trunk/src/VBox/VMM/include/IEMMc.h	(revision 104183)
@@ -187,10 +187,4 @@
             return iemRaiseUndefinedOpcode(pVCpu); \
         } \
-    } while (0)
-#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
-    do { \
-        if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
-            return iemRaiseSimdFpException(pVCpu); \
-        return iemRaiseUndefinedOpcode(pVCpu); \
     } while (0)
 
@@ -3161,7 +3155,4 @@
 #define IEM_MC_IF_FCW_IM() \
     if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
-#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
-        if ((  ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
-             & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
 
 #define IEM_MC_ELSE()                                   } else {
Index: trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
===================================================================
--- trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp	(revision 104182)
+++ trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp	(revision 104183)
@@ -617,5 +617,4 @@
 #define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) do { (void)fMcBegin; } while (0)
 #define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() do { (void)fMcBegin; } while (0)
-#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT()       do { (void)fMcBegin; } while (0)
 
 #define CHK_VAR(a_Name)                                 do { RT_CONCAT(iVarCheck_,a_Name) = 1; } while (0)
@@ -1119,5 +1118,4 @@
     if (g_fRandom != fFpuRead) {
 #define IEM_MC_IF_FCW_IM()                                              (void)fMcBegin; if (g_fRandom != fFpuRead) {
-#define IEM_MC_IF_MXCSR_XCPT_PENDING()                                  (void)fMcBegin; if (g_fRandom != fSseRead) {
 #define IEM_MC_ELSE()                                                   } else {
 #define IEM_MC_ENDIF()                                                  } do { (void)fMcBegin; } while (0)
