VirtualBox

Changeset 104190 in vbox for trunk


Ignore:
Timestamp:
Apr 5, 2024 1:28:25 PM (10 months ago)
Author:
vboxsync
Message:

ValidationKit/bootsectors: Implement testcases for [v]pslldq, [v]psrldq instructions; bugref:9898

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

    r104077 r104190  
    28712871EMIT_INSTR_PLUS_ICEBP_XMM_890  vpsllvq
    28722872EMIT_INSTR_PLUS_ICEBP_YMM_890  vpsllvq
     2873
     2874;
     2875; [V]PSLLDQ
     2876;
     2877EMIT_INSTR_PLUS_ICEBP       pslldq,  XMM1, 000h
     2878EMIT_INSTR_PLUS_ICEBP       pslldq,  XMM1, 005h
     2879EMIT_INSTR_PLUS_ICEBP       pslldq,  XMM1, 012h
     2880EMIT_INSTR_PLUS_ICEBP       vpslldq, XMM1, XMM2, 000h
     2881EMIT_INSTR_PLUS_ICEBP       vpslldq, XMM1, XMM2, 005h
     2882EMIT_INSTR_PLUS_ICEBP       vpslldq, XMM1, XMM2, 012h
     2883EMIT_INSTR_PLUS_ICEBP       vpslldq, YMM1, YMM2, 000h
     2884EMIT_INSTR_PLUS_ICEBP       vpslldq, YMM1, YMM2, 005h
     2885EMIT_INSTR_PLUS_ICEBP       vpslldq, YMM1, YMM2, 012h
     2886EMIT_INSTR_PLUS_ICEBP_C64   pslldq,  XMM8, 000h
     2887EMIT_INSTR_PLUS_ICEBP_C64   pslldq,  XMM8, 005h
     2888EMIT_INSTR_PLUS_ICEBP_C64   pslldq,  XMM8, 012h
     2889EMIT_INSTR_PLUS_ICEBP_C64   vpslldq, XMM8, XMM9, 000h
     2890EMIT_INSTR_PLUS_ICEBP_C64   vpslldq, XMM8, XMM9, 005h
     2891EMIT_INSTR_PLUS_ICEBP_C64   vpslldq, XMM8, XMM9, 012h
     2892EMIT_INSTR_PLUS_ICEBP_C64   vpslldq, YMM8, YMM9, 000h
     2893EMIT_INSTR_PLUS_ICEBP_C64   vpslldq, YMM8, YMM9, 005h
     2894EMIT_INSTR_PLUS_ICEBP_C64   vpslldq, YMM8, YMM9, 012h
     2895
     2896;
     2897; [V]PSRLDQ
     2898;
     2899EMIT_INSTR_PLUS_ICEBP       psrldq,  XMM1, 000h
     2900EMIT_INSTR_PLUS_ICEBP       psrldq,  XMM1, 005h
     2901EMIT_INSTR_PLUS_ICEBP       psrldq,  XMM1, 012h
     2902EMIT_INSTR_PLUS_ICEBP       vpsrldq, XMM1, XMM2, 000h
     2903EMIT_INSTR_PLUS_ICEBP       vpsrldq, XMM1, XMM2, 005h
     2904EMIT_INSTR_PLUS_ICEBP       vpsrldq, XMM1, XMM2, 012h
     2905EMIT_INSTR_PLUS_ICEBP       vpsrldq, YMM1, YMM2, 000h
     2906EMIT_INSTR_PLUS_ICEBP       vpsrldq, YMM1, YMM2, 005h
     2907EMIT_INSTR_PLUS_ICEBP       vpsrldq, YMM1, YMM2, 012h
     2908EMIT_INSTR_PLUS_ICEBP_C64   psrldq,  XMM8, 000h
     2909EMIT_INSTR_PLUS_ICEBP_C64   psrldq,  XMM8, 005h
     2910EMIT_INSTR_PLUS_ICEBP_C64   psrldq,  XMM8, 012h
     2911EMIT_INSTR_PLUS_ICEBP_C64   vpsrldq, XMM8, XMM9, 000h
     2912EMIT_INSTR_PLUS_ICEBP_C64   vpsrldq, XMM8, XMM9, 005h
     2913EMIT_INSTR_PLUS_ICEBP_C64   vpsrldq, XMM8, XMM9, 012h
     2914EMIT_INSTR_PLUS_ICEBP_C64   vpsrldq, YMM8, YMM9, 000h
     2915EMIT_INSTR_PLUS_ICEBP_C64   vpsrldq, YMM8, YMM9, 005h
     2916EMIT_INSTR_PLUS_ICEBP_C64   vpsrldq, YMM8, YMM9, 012h
    28732917
    28742918;

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

    r104077 r104190  
    86368636        {  bs3CpuInstr3_vpsrlvq_YMM8_YMM9_YMM10_icebp_c64, 255,         RM_REG, T_AVX2_256,  8, 9,  10, RT_ELEMENTS(s_aValues64), s_aValues64  },
    86378637        {  bs3CpuInstr3_vpsrlvq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256,  8, 9, 255, RT_ELEMENTS(s_aValues64), s_aValues64  },
     8638    };
     8639    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     8640    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     8641    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     8642                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
     8643}
     8644
     8645
     8646/*
     8647 * [V]PSLLDQ/[V]PSRLDQ  - Shift Double Quadword Left / Right Logical
     8648 */
     8649BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pslldq_v_psrldq(uint8_t bMode)
     8650{
     8651    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesX00[] =
     8652    {
     8653        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8654            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8655            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
     8656        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8657            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8658            /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) },  /* no shift */
     8659    };
     8660    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesL05[] =
     8661    {
     8662        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8663            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8664            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
     8665        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8666            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8667            /* => */ RTUINT256_INIT_C(0x633294f95c8eec40, 0x7256330000000000, 0x9962c343d3cda023, 0x8499fd0000000000) },  /* 5 bytes left */
     8668    };
     8669    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesR05[] =
     8670    {
     8671        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8672            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8673            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
     8674        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8675            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8676            /* => */ RTUINT256_INIT_C(0x00000000001edddd, 0xac09633294f95c8e, 0x00000000008800e9, 0x5bbf9962c343d3cd) },  /* 5 bytes right */
     8677    };
     8678    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesX12[] =
     8679    {
     8680        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8681            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8682            /* => */ RTUINT256_INIT_C(0, 0, 0, 0) },
     8683        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     8684            /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
     8685            /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) },  /* shift too far */
     8686    };
     8687    static BS3CPUINSTR3_TEST1_T const s_aTests16[] = {
     8688        {  bs3CpuInstr3_pslldq_XMM1_000h_icebp_c16,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8689        {  bs3CpuInstr3_pslldq_XMM1_005h_icebp_c16,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8690        {  bs3CpuInstr3_pslldq_XMM1_012h_icebp_c16,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8691        {  bs3CpuInstr3_vpslldq_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8692        {  bs3CpuInstr3_vpslldq_XMM1_XMM2_005h_icebp_c16, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8693        {  bs3CpuInstr3_vpslldq_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8694        {  bs3CpuInstr3_vpslldq_YMM1_YMM2_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8695        {  bs3CpuInstr3_vpslldq_YMM1_YMM2_005h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8696        {  bs3CpuInstr3_vpslldq_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8697
     8698        {  bs3CpuInstr3_psrldq_XMM1_000h_icebp_c16,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8699        {  bs3CpuInstr3_psrldq_XMM1_005h_icebp_c16,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8700        {  bs3CpuInstr3_psrldq_XMM1_012h_icebp_c16,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8701        {  bs3CpuInstr3_vpsrldq_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8702        {  bs3CpuInstr3_vpsrldq_XMM1_XMM2_005h_icebp_c16, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8703        {  bs3CpuInstr3_vpsrldq_XMM1_XMM2_012h_icebp_c16, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8704        {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8705        {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_005h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8706        {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_012h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8707    };
     8708    static BS3CPUINSTR3_TEST1_T const s_aTests32[] = {
     8709        {  bs3CpuInstr3_pslldq_XMM1_000h_icebp_c32,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8710        {  bs3CpuInstr3_pslldq_XMM1_005h_icebp_c32,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8711        {  bs3CpuInstr3_pslldq_XMM1_012h_icebp_c32,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8712        {  bs3CpuInstr3_vpslldq_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8713        {  bs3CpuInstr3_vpslldq_XMM1_XMM2_005h_icebp_c32, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8714        {  bs3CpuInstr3_vpslldq_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8715        {  bs3CpuInstr3_vpslldq_YMM1_YMM2_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8716        {  bs3CpuInstr3_vpslldq_YMM1_YMM2_005h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8717        {  bs3CpuInstr3_vpslldq_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8718
     8719        {  bs3CpuInstr3_psrldq_XMM1_000h_icebp_c32,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8720        {  bs3CpuInstr3_psrldq_XMM1_005h_icebp_c32,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8721        {  bs3CpuInstr3_psrldq_XMM1_012h_icebp_c32,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8722        {  bs3CpuInstr3_vpsrldq_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8723        {  bs3CpuInstr3_vpsrldq_XMM1_XMM2_005h_icebp_c32, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8724        {  bs3CpuInstr3_vpsrldq_XMM1_XMM2_012h_icebp_c32, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8725        {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8726        {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_005h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8727        {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_012h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8728    };
     8729    static BS3CPUINSTR3_TEST1_T const s_aTests64[] = {
     8730        {  bs3CpuInstr3_pslldq_XMM1_000h_icebp_c64,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8731        {  bs3CpuInstr3_pslldq_XMM1_005h_icebp_c64,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8732        {  bs3CpuInstr3_pslldq_XMM1_012h_icebp_c64,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8733        {  bs3CpuInstr3_vpslldq_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8734        {  bs3CpuInstr3_vpslldq_XMM1_XMM2_005h_icebp_c64, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8735        {  bs3CpuInstr3_vpslldq_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8736        {  bs3CpuInstr3_vpslldq_YMM1_YMM2_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8737        {  bs3CpuInstr3_vpslldq_YMM1_YMM2_005h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8738        {  bs3CpuInstr3_vpslldq_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8739
     8740        {  bs3CpuInstr3_psrldq_XMM1_000h_icebp_c64,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8741        {  bs3CpuInstr3_psrldq_XMM1_005h_icebp_c64,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8742        {  bs3CpuInstr3_psrldq_XMM1_012h_icebp_c64,       255, RM_REG, T_SSE2,     1, 1, 2, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8743        {  bs3CpuInstr3_vpsrldq_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8744        {  bs3CpuInstr3_vpsrldq_XMM1_XMM2_005h_icebp_c64, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8745        {  bs3CpuInstr3_vpsrldq_XMM1_XMM2_012h_icebp_c64, 255, RM_REG, T_AVX_128,  1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8746        {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8747        {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_005h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8748        {  bs3CpuInstr3_vpsrldq_YMM1_YMM2_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 1, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8749
     8750        {  bs3CpuInstr3_pslldq_XMM8_000h_icebp_c64,       255, RM_REG, T_SSE2,     8, 8, 9, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8751        {  bs3CpuInstr3_pslldq_XMM8_005h_icebp_c64,       255, RM_REG, T_SSE2,     8, 8, 9, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8752        {  bs3CpuInstr3_pslldq_XMM8_012h_icebp_c64,       255, RM_REG, T_SSE2,     8, 8, 9, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8753        {  bs3CpuInstr3_vpslldq_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_AVX_128,  8, 9, 8, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8754        {  bs3CpuInstr3_vpslldq_XMM8_XMM9_005h_icebp_c64, 255, RM_REG, T_AVX_128,  8, 9, 8, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8755        {  bs3CpuInstr3_vpslldq_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128,  8, 9, 8, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8756        {  bs3CpuInstr3_vpslldq_YMM8_YMM9_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8757        {  bs3CpuInstr3_vpslldq_YMM8_YMM9_005h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesL05), s_aValuesL05  },
     8758        {  bs3CpuInstr3_vpslldq_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8759
     8760        {  bs3CpuInstr3_psrldq_XMM8_000h_icebp_c64,       255, RM_REG, T_SSE2,     8, 8, 9, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8761        {  bs3CpuInstr3_psrldq_XMM8_005h_icebp_c64,       255, RM_REG, T_SSE2,     8, 8, 9, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8762        {  bs3CpuInstr3_psrldq_XMM8_012h_icebp_c64,       255, RM_REG, T_SSE2,     8, 8, 9, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8763        {  bs3CpuInstr3_vpsrldq_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_AVX_128,  8, 9, 8, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8764        {  bs3CpuInstr3_vpsrldq_XMM8_XMM9_005h_icebp_c64, 255, RM_REG, T_AVX_128,  8, 9, 8, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8765        {  bs3CpuInstr3_vpsrldq_XMM8_XMM9_012h_icebp_c64, 255, RM_REG, T_AVX_128,  8, 9, 8, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
     8766        {  bs3CpuInstr3_vpsrldq_YMM8_YMM9_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesX00), s_aValuesX00  },
     8767        {  bs3CpuInstr3_vpsrldq_YMM8_YMM9_005h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesR05), s_aValuesR05  },
     8768        {  bs3CpuInstr3_vpsrldq_YMM8_YMM9_012h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 8, RT_ELEMENTS(s_aValuesX12), s_aValuesX12  },
    86388769    };
    86398770    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
    … …  
    1401714148        { "vpsravd",                                        bs3CpuInstr3_vpsravd, 0 },
    1401814149        { "vpsrlvd/vpsrlvq",                                bs3CpuInstr3_vpsrlvd_vpsrlvq, 0 },
     14150        { "[v]pslldq/[v]psrldq",                            bs3CpuInstr3_v_pslldq_v_psrldq, 0 },
    1401914151#endif
    1402014152#if defined(ALL_TESTS)
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