Changeset 104206 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Apr 5, 2024 8:28:19 PM (11 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162643

Message:

VMM/IEM: Refactoring assembly helpers to not pass eflags by reference but instead by value and return the updated value (via eax/w0) - first chunk: IMUL(two ops), BSF, BSR, LZCNT, TZCNT, POPCNT. bugref:10376

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAllAImpl.asm (modified) (14 diffs)
• IEMAllAImplC.cpp (modified) (9 diffs)
• IEMAllInstCommon.cpp.h (modified) (15 diffs)
• IEMAllInstOneByte.cpp.h (modified) (18 diffs)
• IEMAllInstTwoByte0f.cpp.h (modified) (13 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -473 +473 @@
 ;;
 ; Calculates the new EFLAGS based on the CPU EFLAGS (%2), a clear mask (%3),
-; signed input (%4[%5]) and parity index (%6).
-;
-; This is used by MUL and IMUL, where we got result (%4 & %6) in xAX which is
-; also T0. So, we have to use T1 for the EFLAGS calculation and save T0/xAX
-; while we extract the %2 flags from the CPU EFLAGS or use T2 (only AMD64).
-;
-; @remarks  Clobbers T0, T1, stack, %6, EFLAGS.
+; signed input (%4[%5]) and parity index (%6), storing the result into EAX (T0).
+;
+; @note     %4 & %6 must not be RAX, EAX, or AX! So, don't use with full MUL/IMUL.
+
+; @remarks  Clobbers T0, T1, stack, %6, EFLAGS, %1.
 ; @param        1       The parameter (A0..A3) holding the eflags value.
 ; @param        2       The mask of modified flags to save.
@@ -486 +484 @@
 ; @param        5       The width of the %4 register in bits (8, 16, 32, or 64).
 ; @param        6       The (full) register containing the parity table index. Will be modified!
-
-%macro IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF 6
- %ifdef RT_ARCH_AMD64
-        pushf
-        pop     T2
- %else
-        push    T0
+%macro IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_RETVAL 6
         pushf
         pop     T0
- %endif
-        mov     T1_32, %1               ; load flags.
-        and     T1_32, ~(%2 | %3 | X86_EFL_PF | X86_EFL_SF)  ; clear the modified, always cleared flags and the two flags we calc.
- %ifdef RT_ARCH_AMD64
-        and     T2_32, (%2)             ; select the modified flags.
-        or      T1_32, T2_32            ; combine the flags.
- %else
+        and     %1, ~(%2 | %3 | X86_EFL_PF | X86_EFL_SF)  ; clear the modified, always cleared flags and the two flags we calc.
         and     T0_32, (%2)             ; select the modified flags.
-        or      T1_32, T0_32            ; combine the flags.
-        pop     T0
- %endif
-
-        ; First calculate SF as it's likely to be refereing to the same register as %6 does.
+        or      T0_32, %1               ; combine the flags.
+
+        ; First calculate SF as it is the same register as %6 (only %6 is always full width).
         bt      %4, %5 - 1
         jnc     %%sf_clear
-        or      T1_32, X86_EFL_SF
+        or      T0_32, X86_EFL_SF
  %%sf_clear:
 
@@ -516 +500 @@
         and     %6, 0xff
  %ifdef RT_ARCH_AMD64
-        lea     T2, [NAME(g_afParity) xWrtRIP]
-        or      T1_8, [T2 + %6]
+        lea     T1, [NAME(g_afParity) xWrtRIP]
+        or      T0_8, [T1 + %6]
  %else
-        or      T1_8, [NAME(g_afParity) + %6]
+        or      T0_8, [NAME(g_afParity) + %6]
  %endif
 
-        mov     %1, T1_32               ; save the result.
+        ;mov     %1, T0_32               ; save the result.
+        ; ASSUMES T0 = eax!
 %endmacro
 
@@ -1411 +1396 @@
 ; system where the 64-bit accesses requires hand coding.
 ;
-; All the functions takes a pointer to the destination memory operand in A0,
-; the source register operand in A1 and a pointer to eflags in A2.
+; All the functions takes a pointer to the destination memory operand in A1,
+; the source register operand in A2 and the incoming eflags in A0.
 ;
 ; In the ZF case the destination register is 'undefined', however it seems that
@@ -1434 +1419 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
-        %1      T0_16, A1_16
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
+        %1      T0_16, A2_16
 %if %4 != 0
         jz      .unchanged_dst
 %endif
-        mov     [A0], T0_16
+        mov     [A1], T0_16
 .unchanged_dst:
-        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, 0
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %2, %3, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16
@@ -1476 +1461 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
-        %1      T0_32, A1_32
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
+        %1      T0_32, A2_32
 %if %4 != 0
         jz      .unchanged_dst
 %endif
-        mov     [A0], T0_32
+        mov     [A1], T0_32
 .unchanged_dst:
-        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, 0
+        IEM_SAVE_FLAGS_RETVAL             A0_32, %2, %3, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -1519 +1504 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
-        %1      T0, A1
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
+        %1      T0, A2
 %if %4 != 0
         jz      .unchanged_dst
 %endif
-        mov     [A0], T0
+        mov     [A1], T0
 .unchanged_dst:
-        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, 0
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %2, %3, 0
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -1571 +1556 @@
 ; system where the 64-bit accesses requires hand coding.
 ;
-; All the functions takes a pointer to the destination memory operand in A0,
-; the source register operand in A1 and a pointer to eflags in A2.
+; All the functions takes a pointer to the destination memory operand in A1,
+; the source register operand in A2 and eflags in A0.
 ;
 ; ASSUMES Intel and AMD set EFLAGS the same way.
@@ -1587 +1572 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, 0
-        %1      T0_16, A1_16
-        mov     [A0], T0_16
-        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, %4
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %2, %3, 0
+        %1      T0_16, A2_16
+        mov     [A1], T0_16
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %2, %3, %4
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16
@@ -1596 +1581 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, 0
-        %1      T0_32, A1_32
-        mov     [A0], T0_32
-        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, %4
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %2, %3, 0
+        %1      T0_32, A2_32
+        mov     [A1], T0_32
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %2, %3, %4
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -1606 +1591 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, 0
-        %1      T0, A1
-        mov     [A0], T0
-        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, %4
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %2, %3, 0
+        %1      T0, A2
+        mov     [A1], T0
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %2, %3, %4
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -1630 +1615 @@
 BEGINPROC_FASTCALL iemAImpl_imul_two_u16 %+ %3, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS_OLD                    A2, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
-        imul    A1_16, word [A0]
-        mov     [A0], A1_16
+        IEM_MAYBE_LOAD_FLAGS                        A0_32, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
+        imul    A2_16, word [A1]
+        mov     [A1], A2_16
  %if %4 != 1
-        IEM_SAVE_FLAGS_OLD                          A2, %1, %2, 0
+        IEM_SAVE_FLAGS_RETVAL                       A0_32, %1, %2, 0
  %else
-        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD    A2, %1, X86_EFL_AF | X86_EFL_ZF, A1_16, 16, A1 ; intel
+        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_RETVAL A0_32, %1, X86_EFL_AF | X86_EFL_ZF, A2_16, 16, A2 ; intel
  %endif
         EPILOGUE_3_ARGS
@@ -1643 +1628 @@
 BEGINPROC_FASTCALL iemAImpl_imul_two_u32 %+ %3, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS_OLD                    A2, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
-        imul    A1_32, dword [A0]
-        mov     [A0], A1_32
+        IEM_MAYBE_LOAD_FLAGS                        A0_32, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
+        imul    A2_32, dword [A1]
+        mov     [A1], A2_32
  %if %4 != 1
-        IEM_SAVE_FLAGS_OLD                          A2, %1, %2, 0
+        IEM_SAVE_FLAGS_RETVAL                       A0_32, %1, %2, 0
  %else
-        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD    A2, %1, X86_EFL_AF | X86_EFL_ZF, A1_32, 32, A1 ; intel
+        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_RETVAL A0_32, %1, X86_EFL_AF | X86_EFL_ZF, A2_32, 32, A2 ; intel
  %endif
         EPILOGUE_3_ARGS
@@ -1657 +1642 @@
 BEGINPROC_FASTCALL iemAImpl_imul_two_u64 %+ %3, 16
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS_OLD                    A2, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
-        imul    A1, qword [A0]
-        mov     [A0], A1
+        IEM_MAYBE_LOAD_FLAGS                        A0_32, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
+        imul    A2, qword [A1]
+        mov     [A1], A2
  %if %4 != 1
-        IEM_SAVE_FLAGS_OLD                          A2, %1, %2, 0
+        IEM_SAVE_FLAGS_RETVAL                       A0_32, %1, %2, 0
  %else
-        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD    A2, %1, X86_EFL_AF | X86_EFL_ZF, A1, 64, A1 ; intel
+        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_RETVAL A0_32, %1, X86_EFL_AF | X86_EFL_ZF, A2, 64, A2 ; intel
  %endif
         EPILOGUE_3_ARGS_EX 8

trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

@@ -1486 +1486 @@
  *       but we restrict ourselves to emulating these recent marchs.
  */
-#define SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlag, a_iBit) do { \
+#define SET_BIT_SEARCH_RESULT_INTEL(a_puDst, a_fEFlagsVar, a_iBit) do { \
         unsigned iBit = (a_iBit); \
-        uint32_t fEfl = *pfEFlags & ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF); \
+        a_fEFlagsVar &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF); \
         if (iBit) \
         { \
-            *puDst    = --iBit; \
-            fEfl     |= IEM_EFL_CALC_PARITY(iBit); \
+            *(a_puDst)    = --iBit; \
+            a_fEFlagsVar |= IEM_EFL_CALC_PARITY(iBit); \
         } \
         else \
-            fEfl     |= X86_EFL_ZF | X86_EFL_PF; \
-        *pfEFlags = fEfl; \
+            a_fEFlagsVar |= X86_EFL_ZF | X86_EFL_PF; \
     } while (0)
-#define SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlag, a_iBit) do { \
+#define SET_BIT_SEARCH_RESULT_AMD(a_puDst, a_fEFlagsVar, a_iBit) do { \
         unsigned const iBit = (a_iBit); \
         if (iBit) \
         { \
-            *puDst     = iBit - 1; \
-            *pfEFlags &= ~X86_EFL_ZF; \
+            *(a_puDst)    = iBit - 1; \
+            a_fEFlagsVar &= ~X86_EFL_ZF; \
         } \
         else \
-            *pfEFlags |= X86_EFL_ZF; \
+            a_fEFlagsVar |= X86_EFL_ZF; \
     } while (0)
 
@@ -1513 +1512 @@
  */
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU64(uSrc));
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64_intel,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU64(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u64_amd,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitFirstSetU64(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsf_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitFirstSetU64(uSrc));
+    return fEFlags;
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsf_u64_intel,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitFirstSetU64(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsf_u64_amd,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_AMD(puDst, fEFlags, ASMBitFirstSetU64(uSrc));
+    return fEFlags;
 }
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU32(uSrc));
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32_intel,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU32(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u32_amd,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitFirstSetU32(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsf_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitFirstSetU32(uSrc));
+    return fEFlags;
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsf_u32_intel,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitFirstSetU32(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsf_u32_amd,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_AMD(puDst, fEFlags, ASMBitFirstSetU32(uSrc));
+    return fEFlags;
 }
 
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU16(uSrc));
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16_intel,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitFirstSetU16(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsf_u16_amd,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitFirstSetU16(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsf_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitFirstSetU16(uSrc));
+    return fEFlags;
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsf_u16_intel,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitFirstSetU16(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsf_u16_amd,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_AMD(puDst, fEFlags, ASMBitFirstSetU16(uSrc));
+    return fEFlags;
 }
 
@@ -1570 +1578 @@
  */
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU64(uSrc));
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64_intel,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU64(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u64_amd,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitLastSetU64(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsr_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitLastSetU64(uSrc));
+    return fEFlags;
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsr_u64_intel,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitLastSetU64(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsr_u64_amd,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_AMD(puDst, fEFlags, ASMBitLastSetU64(uSrc));
+    return fEFlags;
 }
 
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU32(uSrc));
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32_intel,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU32(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u32_amd,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitLastSetU32(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsr_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitLastSetU32(uSrc));
+    return fEFlags;
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsr_u32_intel,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitLastSetU32(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsr_u32_amd,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_AMD(puDst, fEFlags, ASMBitLastSetU32(uSrc));
+    return fEFlags;
 }
 
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU16(uSrc));
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16_intel,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_INTEL(puDst, pfEFlags, ASMBitLastSetU16(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_bsr_u16_amd,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_SEARCH_RESULT_AMD(puDst, pfEFlags, ASMBitLastSetU16(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsr_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitLastSetU16(uSrc));
+    return fEFlags;
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsr_u16_intel,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_INTEL(puDst, fEFlags, ASMBitLastSetU16(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_bsr_u16_amd,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    SET_BIT_SEARCH_RESULT_AMD(puDst, fEFlags, ASMBitLastSetU16(uSrc));
+    return fEFlags;
 }
 
@@ -1626 +1643 @@
  * Helpers for LZCNT and TZCNT.
  */
-#define SET_BIT_CNT_SEARCH_RESULT_INTEL(a_puDst, a_uSrc, a_pfEFlags, a_uResult) do { \
+#define SET_BIT_CNT_SEARCH_RESULT_INTEL(a_puDst, a_uSrc, a_fEFlagsVar, a_uResult) do { \
         unsigned const uResult = (a_uResult); \
         *(a_puDst) = uResult; \
-        uint32_t fEfl = *(a_pfEFlags) & ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF); \
+        a_fEFlagsVar &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF); \
         if (uResult) \
-            fEfl |= IEM_EFL_CALC_PARITY(uResult); \
+            a_fEFlagsVar |= IEM_EFL_CALC_PARITY(uResult); \
         else \
-            fEfl |= X86_EFL_ZF | X86_EFL_PF; \
+            a_fEFlagsVar |= X86_EFL_ZF | X86_EFL_PF; \
         if (!a_uSrc) \
-            fEfl |= X86_EFL_CF; \
-        *(a_pfEFlags) = fEfl; \
+            a_fEFlagsVar |= X86_EFL_CF; \
     } while (0)
-#define SET_BIT_CNT_SEARCH_RESULT_AMD(a_puDst, a_uSrc, a_pfEFlags, a_uResult) do { \
+#define SET_BIT_CNT_SEARCH_RESULT_AMD(a_puDst, a_uSrc, a_fEFlagsVar, a_uResult) do { \
         unsigned const uResult = (a_uResult); \
         *(a_puDst) = uResult; \
-        uint32_t fEfl = *(a_pfEFlags) & ~(X86_EFL_ZF | X86_EFL_CF); \
+        a_fEFlagsVar &= ~(X86_EFL_ZF | X86_EFL_CF); \
         if (!uResult) \
-            fEfl |= X86_EFL_ZF; \
+            a_fEFlagsVar |= X86_EFL_ZF; \
         if (!a_uSrc) \
-            fEfl |= X86_EFL_CF; \
-        *(a_pfEFlags) = fEfl; \
+            a_fEFlagsVar |= X86_EFL_CF; \
     } while (0)
 
@@ -1654 +1669 @@
  */
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_lzcnt_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    iemAImpl_lzcnt_u64_intel(puDst, uSrc, pfEFlags);
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_lzcnt_u64_intel,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, pfEFlags, ASMCountLeadingZerosU64(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_lzcnt_u64_amd,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, pfEFlags, ASMCountLeadingZerosU64(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_lzcnt_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    return iemAImpl_lzcnt_u64_intel(fEFlags, puDst, uSrc);
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_lzcnt_u64_intel,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, fEFlags, ASMCountLeadingZerosU64(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_lzcnt_u64_amd,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, fEFlags, ASMCountLeadingZerosU64(uSrc));
+    return fEFlags;
 }
 
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_lzcnt_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    iemAImpl_lzcnt_u32_intel(puDst, uSrc, pfEFlags);
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_lzcnt_u32_intel,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, pfEFlags, ASMCountLeadingZerosU32(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_lzcnt_u32_amd,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, pfEFlags, ASMCountLeadingZerosU32(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_lzcnt_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    return iemAImpl_lzcnt_u32_intel(fEFlags, puDst, uSrc);
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_lzcnt_u32_intel,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, fEFlags, ASMCountLeadingZerosU32(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_lzcnt_u32_amd,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, fEFlags, ASMCountLeadingZerosU32(uSrc));
+    return fEFlags;
 }
 
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_lzcnt_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    iemAImpl_lzcnt_u16_intel(puDst, uSrc, pfEFlags);
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_lzcnt_u16_intel,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, pfEFlags, ASMCountLeadingZerosU16(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_lzcnt_u16_amd,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, pfEFlags, ASMCountLeadingZerosU16(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_lzcnt_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    return iemAImpl_lzcnt_u16_intel(fEFlags, puDst, uSrc);
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_lzcnt_u16_intel,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, fEFlags, ASMCountLeadingZerosU16(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_lzcnt_u16_amd,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, fEFlags, ASMCountLeadingZerosU16(uSrc));
+    return fEFlags;
 }
 
@@ -1711 +1732 @@
  */
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_tzcnt_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    iemAImpl_tzcnt_u64_intel(puDst, uSrc, pfEFlags);
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_tzcnt_u64_intel,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, pfEFlags, ASMCountTrailingZerosU64(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_tzcnt_u64_amd,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, pfEFlags, ASMCountTrailingZerosU64(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_tzcnt_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    return iemAImpl_tzcnt_u64_intel(fEFlags, puDst, uSrc);
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_tzcnt_u64_intel,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, fEFlags, ASMCountTrailingZerosU64(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_tzcnt_u64_amd,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, fEFlags, ASMCountTrailingZerosU64(uSrc));
+    return fEFlags;
 }
 
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_tzcnt_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    iemAImpl_tzcnt_u32_intel(puDst, uSrc, pfEFlags);
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_tzcnt_u32_intel,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, pfEFlags, ASMCountTrailingZerosU32(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_tzcnt_u32_amd,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, pfEFlags, ASMCountTrailingZerosU32(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_tzcnt_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    return iemAImpl_tzcnt_u32_intel(fEFlags, puDst, uSrc);
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_tzcnt_u32_intel,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, fEFlags, ASMCountTrailingZerosU32(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_tzcnt_u32_amd,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, fEFlags, ASMCountTrailingZerosU32(uSrc));
+    return fEFlags;
 }
 
 
 #if !defined(RT_ARCH_AMD64) || defined(IEM_WITHOUT_ASSEMBLY)
-IEM_DECL_IMPL_DEF(void, iemAImpl_tzcnt_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    iemAImpl_tzcnt_u16_intel(puDst, uSrc, pfEFlags);
-}
-#endif
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_tzcnt_u16_intel,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, pfEFlags, ASMCountTrailingZerosU16(uSrc));
-}
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_tzcnt_u16_amd,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, pfEFlags, ASMCountTrailingZerosU16(uSrc));
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_tzcnt_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    return iemAImpl_tzcnt_u16_intel(fEFlags, puDst, uSrc);
+}
+#endif
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_tzcnt_u16_intel,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_INTEL(puDst, uSrc, fEFlags, ASMCountTrailingZerosU16(uSrc));
+    return fEFlags;
+}
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_tzcnt_u16_amd,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    SET_BIT_CNT_SEARCH_RESULT_AMD(puDst, uSrc, fEFlags, ASMCountTrailingZerosU16(uSrc));
+    return fEFlags;
 }
 
@@ -1967 +1994 @@
 
 #define EMIT_POPCNT(a_cBits, a_Type, a_Suffix) \
-IEM_DECL_IMPL_DEF(void, RT_CONCAT3(iemAImpl_popcnt_u,a_cBits,a_Suffix),(a_Type *puDst, a_Type uSrc, uint32_t *pfEFlags)) \
+IEM_DECL_IMPL_DEF(uint32_t, RT_CONCAT3(iemAImpl_popcnt_u,a_cBits,a_Suffix),(uint32_t fEFlags, a_Type *puDst, a_Type uSrc)) \
 { \
-    uint32_t    fEfl = *pfEFlags & ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF); \
+    fEFlags &= ~(X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF); \
     a_Type      uResult; \
     if (uSrc) \
@@ -1975 +2002 @@
     else \
     { \
-        fEfl |= X86_EFL_ZF; \
-        uResult = 0; \
+        fEFlags |= X86_EFL_ZF; \
+        uResult  = 0; \
     } \
-    *puDst    = uResult; \
-    *pfEFlags = fEfl; \
+    *puDst = uResult; \
+    return fEFlags; \
 }
 
@@ -2622 +2649 @@
  */
 # define EMIT_IMUL_TWO(a_cBits, a_uType) \
-IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u ## a_cBits,(a_uType *puDst, a_uType uSrc, uint32_t *pfEFlags)) \
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_imul_two_u ## a_cBits,(uint32_t fEFlags, a_uType *puDst, a_uType uSrc)) \
 { \
     a_uType uIgn; \
-    iemAImpl_imul_u ## a_cBits(puDst, &uIgn, uSrc, pfEFlags); \
+    iemAImpl_imul_u ## a_cBits(puDst, &uIgn, uSrc, &fEFlags); \
+    return fEFlags; \
 } \
 \
-IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u ## a_cBits ## _intel,(a_uType *puDst, a_uType uSrc, uint32_t *pfEFlags)) \
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_imul_two_u ## a_cBits ## _intel,(uint32_t fEFlags, a_uType *puDst, a_uType uSrc)) \
 { \
     a_uType uIgn; \
-    iemAImpl_imul_u ## a_cBits ## _intel(puDst, &uIgn, uSrc, pfEFlags); \
+    iemAImpl_imul_u ## a_cBits ## _intel(puDst, &uIgn, uSrc, &fEFlags); \
+    return fEFlags; \
 } \
 \
-IEM_DECL_IMPL_DEF(void, iemAImpl_imul_two_u ## a_cBits ## _amd,(a_uType *puDst, a_uType uSrc, uint32_t *pfEFlags)) \
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_imul_two_u ## a_cBits ## _amd,(uint32_t fEFlags, a_uType *puDst, a_uType uSrc)) \
 { \
     a_uType uIgn; \
-    iemAImpl_imul_u ## a_cBits ## _amd(puDst, &uIgn, uSrc, pfEFlags); \
+    iemAImpl_imul_u ## a_cBits ## _amd(puDst, &uIgn, uSrc, &fEFlags); \
+    return fEFlags; \
 }
 

trunk/src/VBox/VMM/VMMAll/IEMAllInstCommon.cpp.h

@@ -46 +46 @@
 
 /** Function table for the BSF instruction. */
-IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsf =
+IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf =
 {
     NULL,  NULL,
@@ -55 +55 @@
 
 /** Function table for the BSF instruction, AMD EFLAGS variant. */
-IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsf_amd =
+IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf_amd =
 {
     NULL,  NULL,
@@ -64 +64 @@
 
 /** Function table for the BSF instruction, Intel EFLAGS variant. */
-IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsf_intel =
+IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf_intel =
 {
     NULL,  NULL,
@@ -73 +73 @@
 
 /** EFLAGS variation selection table for the BSF instruction. */
-IEM_STATIC const IEMOPBINTODOSIZES * const g_iemAImpl_bsf_eflags[] =
+IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_bsf_eflags[] =
 {
     &g_iemAImpl_bsf,
@@ -82 +82 @@
 
 /** Function table for the BSR instruction. */
-IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsr =
+IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr =
 {
     NULL,  NULL,
@@ -91 +91 @@
 
 /** Function table for the BSR instruction, AMD EFLAGS variant. */
-IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsr_amd =
+IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr_amd =
 {
     NULL,  NULL,
@@ -100 +100 @@
 
 /** Function table for the BSR instruction, Intel EFLAGS variant. */
-IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsr_intel =
+IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr_intel =
 {
     NULL,  NULL,
@@ -109 +109 @@
 
 /** EFLAGS variation selection table for the BSR instruction. */
-IEM_STATIC const IEMOPBINTODOSIZES * const g_iemAImpl_bsr_eflags[] =
+IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_bsr_eflags[] =
 {
     &g_iemAImpl_bsr,
@@ -118 +118 @@
 
 /** Function table for the IMUL instruction. */
-IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_imul_two =
+IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two =
 {
     NULL,  NULL,
@@ -127 +127 @@
 
 /** Function table for the IMUL instruction, AMD EFLAGS variant. */
-IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_imul_two_amd =
+IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two_amd =
 {
     NULL,  NULL,
@@ -136 +136 @@
 
 /** Function table for the IMUL instruction, Intel EFLAGS variant. */
-IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_imul_two_intel =
+IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two_intel =
 {
     NULL,  NULL,
@@ -145 +145 @@
 
 /** EFLAGS variation selection table for the IMUL instruction. */
-IEM_STATIC const IEMOPBINTODOSIZES * const g_iemAImpl_imul_two_eflags[] =
+IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_imul_two_eflags[] =
 {
     &g_iemAImpl_imul_two,
@@ -154 +154 @@
 
 /** EFLAGS variation selection table for the 16-bit IMUL instruction. */
-IEM_STATIC PFNIEMAIMPLBINTODOU16 const g_iemAImpl_imul_two_u16_eflags[] =
+IEM_STATIC PFNIEMAIMPLBINU16 const g_iemAImpl_imul_two_u16_eflags[] =
 {
     iemAImpl_imul_two_u16,
@@ -163 +163 @@
 
 /** EFLAGS variation selection table for the 32-bit IMUL instruction. */
-IEM_STATIC PFNIEMAIMPLBINTODOU32 const g_iemAImpl_imul_two_u32_eflags[] =
+IEM_STATIC PFNIEMAIMPLBINU32 const g_iemAImpl_imul_two_u32_eflags[] =
 {
     iemAImpl_imul_two_u32,
@@ -172 +172 @@
 
 /** EFLAGS variation selection table for the 64-bit IMUL instruction. */
-IEM_STATIC PFNIEMAIMPLBINTODOU64 const g_iemAImpl_imul_two_u64_eflags[] =
+IEM_STATIC PFNIEMAIMPLBINU64 const g_iemAImpl_imul_two_u64_eflags[] =
 {
     iemAImpl_imul_two_u64,

trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h

@@ -3386 +3386 @@
         case IEMMODE_16BIT:
         {
-            PFNIEMAIMPLBINTODOU16 const pfnAImplU16 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u16_eflags);
+            PFNIEMAIMPLBINU16 const pfnAImplU16 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u16_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3395 +3395 @@
                 IEM_MC_LOCAL(uint16_t,              u16Tmp);
                 IEM_MC_FETCH_GREG_U16(u16Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
-                IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst, u16Tmp,        0);
-                IEM_MC_ARG_CONST(uint16_t,          u16Src,/*=*/ u16Imm,    1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,                2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU16, pu16Dst, u16Src, pEFlags);
+
+                IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst, u16Tmp,        1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,              0);
+                IEM_MC_ARG_CONST(uint16_t,          u16Src,/*=*/ u16Imm,    2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU16, fEFlagsIn, pu16Dst, u16Src);
                 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3418 +3419 @@
                 IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
 
-                IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst,    u16Tmp, 0);
-                IEM_MC_ARG_CONST(uint16_t,          u16Src,     u16Imm, 1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,            2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU16, pu16Dst, u16Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst,    u16Tmp,     1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,              0);
+                IEM_MC_ARG_CONST(uint16_t,          u16Src,     u16Imm,     2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU16, fEFlagsIn, pu16Dst, u16Src);
                 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3433 +3434 @@
         case IEMMODE_32BIT:
         {
-            PFNIEMAIMPLBINTODOU32 const pfnAImplU32 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u32_eflags);
+            PFNIEMAIMPLBINU32 const pfnAImplU32 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u32_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3443 +3444 @@
                 IEM_MC_FETCH_GREG_U32(u32Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
 
-                IEM_MC_ARG_LOCAL_REF(uint32_t *,    pu32Dst,     u32Tmp,    0);
-                IEM_MC_ARG_CONST(uint32_t,          u32Src,/*=*/ u32Imm,    1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,                2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU32, pu32Dst, u32Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint32_t *,    pu32Dst,     u32Tmp,    1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,              0);
+                IEM_MC_ARG_CONST(uint32_t,          u32Src,/*=*/ u32Imm,    2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU32, fEFlagsIn, pu32Dst, u32Src);
                 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3466 +3467 @@
                 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
 
-                IEM_MC_ARG_LOCAL_REF(uint32_t *,    pu32Dst,    u32Tmp, 0);
-                IEM_MC_ARG_CONST(uint32_t,          u32Src,     u32Imm, 1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,            2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU32, pu32Dst, u32Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint32_t *,    pu32Dst,    u32Tmp,     1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,              0);
+                IEM_MC_ARG_CONST(uint32_t,          u32Src,     u32Imm,     2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU32, fEFlagsIn, pu32Dst, u32Src);
                 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3481 +3482 @@
         case IEMMODE_64BIT:
         {
-            PFNIEMAIMPLBINTODOU64 const pfnAImplU64 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u64_eflags);
+            PFNIEMAIMPLBINU64 const pfnAImplU64 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u64_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3491 +3492 @@
                 IEM_MC_FETCH_GREG_U64(u64Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
 
-                IEM_MC_ARG_LOCAL_REF(uint64_t *,    pu64Dst,     u64Tmp,    0);
-                IEM_MC_ARG_CONST(uint64_t,          u64Src,/*=*/ u64Imm,    1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,                2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU64, pu64Dst, u64Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint64_t *,    pu64Dst,     u64Tmp,    1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,              0);
+                IEM_MC_ARG_CONST(uint64_t,          u64Src,/*=*/ u64Imm,    2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU64, fEFlagsIn, pu64Dst, u64Src);
                 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3514 +3515 @@
                 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
 
-                IEM_MC_ARG_LOCAL_REF(uint64_t *,    pu64Dst,      u64Tmp,                   0);
-                IEM_MC_ARG_CONST(uint64_t,          u64Src, /*=*/ (int64_t)(int32_t)u32Imm, 1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,                                2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU64, pu64Dst, u64Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint64_t *,    pu64Dst,      u64Tmp,                   1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,                              0);
+                IEM_MC_ARG_CONST(uint64_t,          u64Src, /*=*/ (int64_t)(int32_t)u32Imm, 2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU64, fEFlagsIn, pu64Dst, u64Src);
                 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3588 +3589 @@
         case IEMMODE_16BIT:
         {
-            PFNIEMAIMPLBINTODOU16 const pfnAImplU16 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u16_eflags);
+            PFNIEMAIMPLBINU16 const pfnAImplU16 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u16_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3599 +3600 @@
                 IEM_MC_FETCH_GREG_U16(u16Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
 
-                IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst,    u16Tmp,         0);
-                IEM_MC_ARG_CONST(uint16_t,          u16Src,/*=*/ (int8_t)u8Imm, 1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,                    2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU16, pu16Dst, u16Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst,    u16Tmp,         1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,                  0);
+                IEM_MC_ARG_CONST(uint16_t,          u16Src,/*=*/ (int8_t)u8Imm, 2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU16, fEFlagsIn, pu16Dst, u16Src);
                 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3623 +3624 @@
                 IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
 
-                IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst,    u16Tmp, 0);
-                IEM_MC_ARG_CONST(uint16_t,          u16Src,     u16Imm, 1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,            2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU16, pu16Dst, u16Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint16_t *,    pu16Dst,    u16Tmp,         1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,                  0);
+                IEM_MC_ARG_CONST(uint16_t,          u16Src,     u16Imm,         2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU16, fEFlagsIn, pu16Dst, u16Src);
                 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3638 +3639 @@
         case IEMMODE_32BIT:
         {
-            PFNIEMAIMPLBINTODOU32 const pfnAImplU32 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u32_eflags);
+            PFNIEMAIMPLBINU32 const pfnAImplU32 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u32_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3648 +3649 @@
                 IEM_MC_FETCH_GREG_U32(u32Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
 
-                IEM_MC_ARG_LOCAL_REF(uint32_t *,    pu32Dst,            u32Tmp, 0);
-                IEM_MC_ARG_CONST(uint32_t,          u32Src,/*=*/ (int8_t)u8Imm, 1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,                    2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU32, pu32Dst, u32Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint32_t *,    pu32Dst,            u32Tmp, 1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,                  0);
+                IEM_MC_ARG_CONST(uint32_t,          u32Src,/*=*/ (int8_t)u8Imm, 2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU32, fEFlagsIn, pu32Dst, u32Src);
                 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3671 +3672 @@
                 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
 
-                IEM_MC_ARG_LOCAL_REF(uint32_t *,    pu32Dst, u32Tmp,    0);
-                IEM_MC_ARG_CONST(uint32_t,          u32Src,  u32Imm,    1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,            2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU32, pu32Dst, u32Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint32_t *,    pu32Dst, u32Tmp,            1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,                  0);
+                IEM_MC_ARG_CONST(uint32_t,          u32Src,  u32Imm,            2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU32, fEFlagsIn, pu32Dst, u32Src);
                 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3686 +3687 @@
         case IEMMODE_64BIT:
         {
-            PFNIEMAIMPLBINTODOU64 const pfnAImplU64 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u64_eflags);
+            PFNIEMAIMPLBINU64 const pfnAImplU64 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u64_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3696 +3697 @@
                 IEM_MC_FETCH_GREG_U64(u64Tmp, IEM_GET_MODRM_RM(pVCpu, bRm));
 
-                IEM_MC_ARG_LOCAL_REF(uint64_t *,    pu64Dst,                       u64Tmp,  0);
-                IEM_MC_ARG_CONST(uint64_t,          u64Src, /*=*/ (int64_t)(int8_t)u8Imm,   1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,                                2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU64, pu64Dst, u64Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint64_t *,    pu64Dst,                       u64Tmp,  1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,                              0);
+                IEM_MC_ARG_CONST(uint64_t,          u64Src, /*=*/ (int64_t)(int8_t)u8Imm,   2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU64, fEFlagsIn, pu64Dst, u64Src);
                 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3719 +3720 @@
                 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffDst);
 
-                IEM_MC_ARG_LOCAL_REF(uint64_t *,    pu64Dst,      u64Tmp,                   0);
-                IEM_MC_ARG_CONST(uint64_t,          u64Src, /*=*/ (int64_t)(int8_t)u8Imm,   1);
-                IEM_MC_ARG(uint32_t *,              pEFlags,                                2);
-                IEM_MC_REF_EFLAGS(pEFlags);
-                IEM_MC_CALL_VOID_AIMPL_3(pfnAImplU64, pu64Dst, u64Src, pEFlags);
+                IEM_MC_ARG_LOCAL_REF(uint64_t *,    pu64Dst,      u64Tmp,                   1);
+                IEM_MC_ARG_EFLAGS(                  fEFlagsIn,                              0);
+                IEM_MC_ARG_CONST(uint64_t,          u64Src, /*=*/ (int64_t)(int8_t)u8Imm,   2);
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pfnAImplU64, fEFlagsIn, pu64Dst, u64Src);
                 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp);
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
 
                 IEM_MC_ADVANCE_RIP_AND_FINISH();

trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h

@@ -10004 +10004 @@
     IEMOP_HLP_MIN_386();
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
-    const IEMOPBINTODOSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_eflags);
+    const IEMOPBINSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_eflags);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
-    IEMOP_BODY_BINARY_TODO_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_MIN_386, imul, 0);
+    IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_MIN_386, imul, 0);
 }
 
@@ -10501 +10501 @@
 #ifndef TST_IEM_CHECK_MC
 # if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
-    static const IEMOPBINTODOSIZES s_Native =
+    static const IEMOPBINSIZES s_Native =
     {   NULL, NULL, iemAImpl_popcnt_u16, NULL, iemAImpl_popcnt_u32, NULL, iemAImpl_popcnt_u64, NULL };
 # endif
-    static const IEMOPBINTODOSIZES s_Fallback =
+    static const IEMOPBINSIZES s_Fallback =
     {   NULL, NULL, iemAImpl_popcnt_u16_fallback, NULL, iemAImpl_popcnt_u32_fallback, NULL, iemAImpl_popcnt_u64_fallback, NULL };
 #endif
-    const IEMOPBINTODOSIZES * const pImpl = IEM_SELECT_HOST_OR_FALLBACK(fPopCnt, &s_Native, &s_Fallback);
+    const IEMOPBINSIZES * const pImpl = IEM_SELECT_HOST_OR_FALLBACK(fPopCnt, &s_Native, &s_Fallback);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
-    IEMOP_BODY_BINARY_TODO_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, popcnt, 0);
+    IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, popcnt, 0);
 }
 
@@ -11005 +11005 @@
                 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
-                IEM_MC_ARG(uint16_t,   u16Src,  1); \
-                IEM_MC_ARG(uint32_t *, pEFlags, 2); \
                 \
+                IEM_MC_ARG(uint16_t,    u16Src,     2); \
                 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, bRm)); \
+                IEM_MC_ARG(uint16_t *,  pu16Dst,    1); \
                 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU16, fEFlagsIn, pu16Dst, u16Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                 IEM_MC_END(); \
                 break; \
-                \
+            \
             case IEMMODE_32BIT: \
                 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
-                IEM_MC_ARG(uint32_t,   u32Src,  1); \
-                IEM_MC_ARG(uint32_t *, pEFlags, 2); \
                 \
+                IEM_MC_ARG(uint32_t,    u32Src,     2); \
                 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, bRm)); \
+                IEM_MC_ARG(uint32_t *,  pu32Dst,    1); \
                 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU32, fEFlagsIn, pu32Dst, u32Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF) { \
                     IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \
@@ -11035 +11035 @@
                 IEM_MC_END(); \
                 break; \
-                \
+            \
             case IEMMODE_64BIT: \
                 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
-                IEM_MC_ARG(uint64_t,   u64Src,  1); \
-                IEM_MC_ARG(uint32_t *, pEFlags, 2); \
                 \
+                IEM_MC_ARG(uint64_t,    u64Src,     2); \
                 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, bRm)); \
+                IEM_MC_ARG(uint64_t *,  pu64Dst,    1); \
                 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU64, fEFlagsIn, pu64Dst, u64Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -11064 +11064 @@
             case IEMMODE_16BIT: \
                 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
-                IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
-                IEM_MC_ARG(uint16_t,   u16Src,  1); \
-                IEM_MC_ARG(uint32_t *, pEFlags, 2); \
-                IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst); \
-                \
+                IEM_MC_LOCAL(RTGCPTR,   GCPtrEffDst); \
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                \
+                IEM_MC_ARG(uint16_t,    u16Src,     2); \
                 IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                IEM_MC_ARG(uint16_t *,  pu16Dst,    1); \
                 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU16, pu16Dst, u16Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU16, fEFlagsIn, pu16Dst, u16Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -11082 +11082 @@
             case IEMMODE_32BIT: \
                 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
-                IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
-                IEM_MC_ARG(uint32_t,   u32Src,  1); \
-                IEM_MC_ARG(uint32_t *, pEFlags, 2); \
-                IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst); \
-                \
+                IEM_MC_LOCAL(RTGCPTR,   GCPtrEffDst); \
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                \
+                IEM_MC_ARG(uint32_t,    u32Src,     2); \
                 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                IEM_MC_ARG(uint32_t *,  pu32Dst,    1); \
                 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU32, pu32Dst, u32Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU32, fEFlagsIn, pu32Dst, u32Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 \
                 IEM_MC_IF_EFL_BIT_NOT_SET(X86_EFL_ZF) { \
@@ -11103 +11103 @@
             case IEMMODE_64BIT: \
                 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
-                IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
-                IEM_MC_ARG(uint64_t,   u64Src,  1); \
-                IEM_MC_ARG(uint32_t *, pEFlags, 2); \
-                IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst); \
-                \
+                IEM_MC_LOCAL(RTGCPTR,   GCPtrEffDst); \
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                \
+                IEM_MC_ARG(uint64_t,    u64Src,     2); \
                 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                IEM_MC_ARG(uint64_t *,  pu64Dst,    1); \
                 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnNormalU64, pu64Dst, u64Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU64, fEFlagsIn, pu64Dst, u64Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -11138 +11138 @@
     IEMOP_HLP_MIN_386();
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF);
-    PCIEMOPBINTODOSIZES const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_bsf_eflags);
+    PCIEMOPBINSIZES const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_bsf_eflags);
     IEMOP_BODY_BIT_SCAN_OPERATOR_RV_RM(pImpl);
 }
@@ -11159 +11159 @@
 
 #ifndef TST_IEM_CHECK_MC
-    static const IEMOPBINTODOSIZES s_iemAImpl_tzcnt =
+    static const IEMOPBINSIZES s_iemAImpl_tzcnt =
     {   NULL, NULL,     iemAImpl_tzcnt_u16, NULL,       iemAImpl_tzcnt_u32, NULL,       iemAImpl_tzcnt_u64, NULL };
-    static const IEMOPBINTODOSIZES s_iemAImpl_tzcnt_amd =
+    static const IEMOPBINSIZES s_iemAImpl_tzcnt_amd =
     {   NULL, NULL,     iemAImpl_tzcnt_u16_amd, NULL,   iemAImpl_tzcnt_u32_amd, NULL,   iemAImpl_tzcnt_u64_amd, NULL };
-    static const IEMOPBINTODOSIZES s_iemAImpl_tzcnt_intel =
+    static const IEMOPBINSIZES s_iemAImpl_tzcnt_intel =
     {   NULL, NULL,     iemAImpl_tzcnt_u16_intel, NULL, iemAImpl_tzcnt_u32_intel, NULL, iemAImpl_tzcnt_u64_intel, NULL };
-    static const IEMOPBINTODOSIZES * const s_iemAImpl_tzcnt_eflags[2][4] =
+    static const IEMOPBINSIZES * const s_iemAImpl_tzcnt_eflags[2][4] =
     {
         { &s_iemAImpl_tzcnt_intel, &s_iemAImpl_tzcnt_intel, &s_iemAImpl_tzcnt_amd, &s_iemAImpl_tzcnt_intel },
@@ -11172 +11172 @@
 #endif
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF);
-    const IEMOPBINTODOSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(s_iemAImpl_tzcnt_eflags,
+    const IEMOPBINSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(s_iemAImpl_tzcnt_eflags,
                                                                             IEM_GET_HOST_CPU_FEATURES(pVCpu)->fBmi1);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
-    IEMOP_BODY_BINARY_TODO_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, tzcnt, 0);
+    IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, tzcnt, 0);
 }
 
@@ -11193 +11193 @@
     IEMOP_HLP_MIN_386();
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF);
-    PCIEMOPBINTODOSIZES const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_bsr_eflags);
+    PCIEMOPBINSIZES const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_bsr_eflags);
     IEMOP_BODY_BIT_SCAN_OPERATOR_RV_RM(pImpl);
 }
@@ -11214 +11214 @@
 
 #ifndef TST_IEM_CHECK_MC
-    static const IEMOPBINTODOSIZES s_iemAImpl_lzcnt =
+    static const IEMOPBINSIZES s_iemAImpl_lzcnt =
     {   NULL, NULL,     iemAImpl_lzcnt_u16, NULL,       iemAImpl_lzcnt_u32, NULL,       iemAImpl_lzcnt_u64, NULL };
-    static const IEMOPBINTODOSIZES s_iemAImpl_lzcnt_amd =
+    static const IEMOPBINSIZES s_iemAImpl_lzcnt_amd =
     {   NULL,  NULL,    iemAImpl_lzcnt_u16_amd, NULL,   iemAImpl_lzcnt_u32_amd, NULL,   iemAImpl_lzcnt_u64_amd, NULL };
-    static const IEMOPBINTODOSIZES s_iemAImpl_lzcnt_intel =
+    static const IEMOPBINSIZES s_iemAImpl_lzcnt_intel =
     {   NULL,  NULL,    iemAImpl_lzcnt_u16_intel, NULL, iemAImpl_lzcnt_u32_intel, NULL, iemAImpl_lzcnt_u64_intel, NULL };
-    static const IEMOPBINTODOSIZES * const s_iemAImpl_lzcnt_eflags[2][4] =
+    static const IEMOPBINSIZES * const s_iemAImpl_lzcnt_eflags[2][4] =
     {
         { &s_iemAImpl_lzcnt_intel, &s_iemAImpl_lzcnt_intel, &s_iemAImpl_lzcnt_amd, &s_iemAImpl_lzcnt_intel },
@@ -11227 +11227 @@
 #endif
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF);
-    const IEMOPBINTODOSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(s_iemAImpl_lzcnt_eflags,
+    const IEMOPBINSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(s_iemAImpl_lzcnt_eflags,
                                                                             IEM_GET_HOST_CPU_FEATURES(pVCpu)->fBmi1);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
-    IEMOP_BODY_BINARY_TODO_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, lzcnt, 0);
+    IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, lzcnt, 0);
 }