Index: trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm	(revision 104262)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm	(revision 104263)
@@ -5065,4 +5065,44 @@
 
 
+;; Template for the vtestp{s,d} instructions
+;
+; @param    1       The instruction
+;
+; @param    A0      Pointer to the first source operand (aka readonly destination).
+; @param    A1      Pointer to the second source operand.
+; @param    A2      Pointer to the EFLAGS register.
+;
+%macro IEMIMPL_VTESTP_SD 1
+BEGINPROC_FASTCALL  iemAImpl_ %+ %1 %+ _u128, 12
+        PROLOGUE_3_ARGS
+        IEMIMPL_AVX_PROLOGUE
+
+        vmovdqu xmm0, [A0]
+        vmovdqu xmm1, [A1]
+        %1 xmm0, xmm1
+        IEM_SAVE_FLAGS_OLD A2, X86_EFL_ZF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_AF | X86_EFL_PF | X86_EFL_SF
+
+        IEMIMPL_AVX_EPILOGUE
+        EPILOGUE_3_ARGS
+ENDPROC             iemAImpl_ %+ %1 %+ _u128
+
+BEGINPROC_FASTCALL  iemAImpl_ %+ %1 %+ _u256, 12
+        PROLOGUE_3_ARGS
+        IEMIMPL_AVX_PROLOGUE
+
+        vmovdqu ymm0, [A0]
+        vmovdqu ymm1, [A1]
+        %1 ymm0, ymm1
+        IEM_SAVE_FLAGS_OLD A2, X86_EFL_ZF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_AF | X86_EFL_PF | X86_EFL_SF
+
+        IEMIMPL_AVX_EPILOGUE
+        EPILOGUE_3_ARGS
+ENDPROC             iemAImpl_ %+ %1 %+ _u256
+%endmacro
+
+IEMIMPL_VTESTP_SD vtestps
+IEMIMPL_VTESTP_SD vtestpd
+
+
 ;;
 ; Template for the [v]pmov{s,z}x* instructions
Index: trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp	(revision 104262)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp	(revision 104263)
@@ -15077,4 +15077,84 @@
 
 
+/* Worker for VEX.128 vtestp[s|d]. */
+static void iemAImpl_vtestp_sd_u128_worker(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint64_t fSignMask, uint32_t *pfEFlags)
+{
+    uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
+    RTUINT128U uTemp;
+    uTemp.au64[0] = puSrc1->au64[0] & puSrc2->au64[0];
+    uTemp.au64[1] = puSrc1->au64[1] & puSrc2->au64[1];
+    if (((  uTemp.au64[0]
+          | uTemp.au64[1]) & fSignMask) == 0)
+        fEfl |= X86_EFL_ZF;
+    uTemp.au64[0] = ~puSrc1->au64[0] & puSrc2->au64[0];
+    uTemp.au64[1] = ~puSrc1->au64[1] & puSrc2->au64[1];
+    if (((  uTemp.au64[0]
+          | uTemp.au64[1]) & fSignMask) == 0)
+        fEfl |= X86_EFL_CF;
+    *pfEFlags = fEfl;
+}
+
+
+/* Worker for VEX.256 vtestp[s|d]. */
+static void iemAImpl_vtestp_sd_u256_worker(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint64_t fSignMask, uint32_t *pfEFlags)
+{
+    uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS;
+    RTUINT256U uTemp;
+    uTemp.au64[0] = puSrc1->au64[0] & puSrc2->au64[0];
+    uTemp.au64[1] = puSrc1->au64[1] & puSrc2->au64[1];
+    uTemp.au64[2] = puSrc1->au64[2] & puSrc2->au64[2];
+    uTemp.au64[3] = puSrc1->au64[3] & puSrc2->au64[3];
+    if (((  uTemp.au64[0]
+          | uTemp.au64[1]
+          | uTemp.au64[2]
+          | uTemp.au64[3]) & fSignMask) == 0)
+        fEfl |= X86_EFL_ZF;
+    uTemp.au64[0] = ~puSrc1->au64[0] & puSrc2->au64[0];
+    uTemp.au64[1] = ~puSrc1->au64[1] & puSrc2->au64[1];
+    uTemp.au64[2] = ~puSrc1->au64[2] & puSrc2->au64[2];
+    uTemp.au64[3] = ~puSrc1->au64[3] & puSrc2->au64[3];
+    if (((  uTemp.au64[0]
+          | uTemp.au64[1]
+          | uTemp.au64[2]
+          | uTemp.au64[3]) & fSignMask) == 0)
+        fEfl |= X86_EFL_CF;
+    *pfEFlags = fEfl;
+}
+
+
+/*
+ * VTESTPS
+ */
+IEM_DECL_IMPL_DEF(void, iemAImpl_vtestps_u128_fallback,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pfEFlags))
+{
+    uint64_t const fSignMask = RT_BIT_64(63) | RT_BIT_64(31);
+    return iemAImpl_vtestp_sd_u128_worker(puSrc1, puSrc2, fSignMask, pfEFlags);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vtestps_u256_fallback,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pfEFlags))
+{
+    uint64_t const fSignMask = RT_BIT_64(63) | RT_BIT_64(31);
+    return iemAImpl_vtestp_sd_u256_worker(puSrc1, puSrc2, fSignMask, pfEFlags);
+}
+
+
+/*
+ * VTESTPD
+ */
+IEM_DECL_IMPL_DEF(void, iemAImpl_vtestpd_u128_fallback,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pfEFlags))
+{
+    uint64_t const fSignMask = RT_BIT_64(63);
+    return iemAImpl_vtestp_sd_u128_worker(puSrc1, puSrc2, fSignMask, pfEFlags);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_vtestpd_u256_fallback,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pfEFlags))
+{
+    uint64_t const fSignMask = RT_BIT_64(63);
+    return iemAImpl_vtestp_sd_u256_worker(puSrc1, puSrc2, fSignMask, pfEFlags);
+}
+
+
 /*
  * PMOVSXBW / VPMOVSXBW
Index: trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap2.cpp.h
===================================================================
--- trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap2.cpp.h	(revision 104262)
+++ trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap2.cpp.h	(revision 104263)
@@ -204,10 +204,139 @@
 
 
+/**
+ * Common worker for AVX instructions on the forms:
+ *     - vtestps/d    xmm1, xmm2/mem128
+ *     - vtestps/d    ymm1, ymm2/mem256
+ *
+ * Takes function table for function w/o implicit state parameter.
+ *
+ * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation.
+ */
+FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Wx, PCIEMOPMEDIAF2EFL, pImpl)
+{
+    Assert(pVCpu->iem.s.uVexLength <= 1);
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    if (IEM_IS_MODRM_REG_MODE(bRm))
+    {
+        /*
+         * Register, register.
+         */
+        if (pVCpu->iem.s.uVexLength)
+        {
+            IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
+            IEM_MC_LOCAL(RTUINT256U,            uSrc1);
+            IEM_MC_LOCAL(RTUINT256U,            uSrc2);
+            IEM_MC_ARG_LOCAL_REF(PCRTUINT256U,  puSrc1, uSrc1, 0);
+            IEM_MC_ARG_LOCAL_REF(PCRTUINT256U,  puSrc2, uSrc2, 1);
+            IEM_MC_ARG(uint32_t *,              pEFlags,       2);
+            IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+            IEM_MC_PREPARE_AVX_USAGE();
+            IEM_MC_FETCH_YREG_U256(uSrc1,   IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_FETCH_YREG_U256(uSrc2,   IEM_GET_MODRM_RM(pVCpu, bRm));
+            IEM_MC_REF_EFLAGS(pEFlags);
+            IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puSrc1, puSrc2, pEFlags);
+            IEM_MC_ADVANCE_RIP_AND_FINISH();
+            IEM_MC_END();
+        }
+        else
+        {
+            IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
+            IEM_MC_ARG(PCRTUINT128U,            puSrc1,  0);
+            IEM_MC_ARG(PCRTUINT128U,            puSrc2,  1);
+            IEM_MC_ARG(uint32_t *,              pEFlags, 2);
+            IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+            IEM_MC_PREPARE_AVX_USAGE();
+            IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm));
+            IEM_MC_REF_EFLAGS(pEFlags);
+            IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puSrc1, puSrc2, pEFlags);
+            IEM_MC_ADVANCE_RIP_AND_FINISH();
+            IEM_MC_END();
+        }
+    }
+    else
+    {
+        /*
+         * Register, memory.
+         */
+        if (pVCpu->iem.s.uVexLength)
+        {
+            IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
+            IEM_MC_LOCAL(RTUINT256U,            uSrc1);
+            IEM_MC_LOCAL(RTUINT256U,            uSrc2);
+            IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
+            IEM_MC_ARG_LOCAL_REF(PCRTUINT256U,  puSrc1, uSrc1, 0);
+            IEM_MC_ARG_LOCAL_REF(PCRTUINT256U,  puSrc2, uSrc2, 1);
+            IEM_MC_ARG(uint32_t *,              pEFlags,       2);
+
+            IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
+            IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+            IEM_MC_PREPARE_AVX_USAGE();
+
+            IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+            IEM_MC_FETCH_YREG_U256(uSrc1,      IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_REF_EFLAGS(pEFlags);
+            IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puSrc1, puSrc2, pEFlags);
+
+            IEM_MC_ADVANCE_RIP_AND_FINISH();
+            IEM_MC_END();
+        }
+        else
+        {
+            IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0);
+            IEM_MC_LOCAL(RTUINT128U,            uSrc2);
+            IEM_MC_LOCAL(RTGCPTR,               GCPtrEffSrc);
+            IEM_MC_ARG(PCRTUINT128U,            puSrc1,        0);
+            IEM_MC_ARG_LOCAL_REF(PCRTUINT128U,  puSrc2, uSrc2, 1);
+            IEM_MC_ARG(uint32_t *,              pEFlags,       2);
+
+            IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+            IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx);
+            IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+            IEM_MC_PREPARE_AVX_USAGE();
+
+            IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2,  pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+            IEM_MC_REF_XREG_U128_CONST(puSrc1,  IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_REF_EFLAGS(pEFlags);
+            IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puSrc1, puSrc2, pEFlags);
+
+            IEM_MC_ADVANCE_RIP_AND_FINISH();
+            IEM_MC_END();
+        }
+    }
+}
+
+
 /*  Opcode VEX.0F38 0x0e - invalid. */
-/**  Opcode VEX.66.0F38 0x0e. */
-FNIEMOP_STUB(iemOp_vtestps_Vx_Wx);
+
+
+/**  Opcode VEX.66.0F38 0x0e.
+ * AVX,AVX */
+FNIEMOP_DEF(iemOp_vtestps_Vx_Wx)
+{
+    /** @todo We need to check VEX.W somewhere... it is documented to \#UD on all
+     *        CPU modes. */
+    IEMOP_MNEMONIC2(VEX_RM, VTESTPS, vtestps, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_W_ZERO);
+    IEMOPMEDIAF2EFL_INIT_VARS(vtestps);
+    return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
+}
+
+
 /*  Opcode VEX.0F38 0x0f - invalid. */
-/**  Opcode VEX.66.0F38 0x0f. */
-FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx);
+
+
+/**  Opcode VEX.66.0F38 0x0f.
+ * AVX,AVX */
+FNIEMOP_DEF(iemOp_vtestpd_Vx_Wx)
+{
+    /** @todo We need to check VEX.W somewhere... it is documented to \#UD on all
+     *        CPU modes. */
+    IEMOP_MNEMONIC2(VEX_RM, VTESTPD, vtestpd, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_W_ZERO);
+    IEMOPMEDIAF2EFL_INIT_VARS(vtestpd);
+    return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback));
+}
 
 
Index: trunk/src/VBox/VMM/include/IEMInternal.h
===================================================================
--- trunk/src/VBox/VMM/include/IEMInternal.h	(revision 104262)
+++ trunk/src/VBox/VMM/include/IEMInternal.h	(revision 104263)
@@ -3849,7 +3849,48 @@
 
 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
+typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128;
 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
+typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256;
 FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
 FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
+FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback;
+FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback;
+FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback;
+FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback;
+
+/**
+ * Function table for media instruction taking two full sized media source
+ * registers, and updating EFLAGS but no additional state (AVX).
+ */
+typedef struct IEMOPMEDIAF2EFL
+{
+    PFNIEMAIMPLF2EFL128 pfnU128;
+    PFNIEMAIMPLF2EFL256 pfnU256;
+} IEMOPMEDIAF2EFL;
+/** Pointer to a media operation function table for 3 full sized ops (AVX). */
+typedef IEMOPMEDIAF2EFL const *PCIEMOPMEDIAF2EFL;
+
+/** @def IEMOPMEDIAF2EFL_INIT_VARS_EX
+ * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
+ * given functions as initializers.  For use in AVX functions where a pair of
+ * functions are only used once and the function table need not be public. */
+#ifndef TST_IEM_CHECK_MC
+# if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
+#  define IEMOPMEDIAF2EFL_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
+    static IEMOPMEDIAF2EFL const s_Host     = { a_pfnHostU128,     a_pfnHostU256 }; \
+    static IEMOPMEDIAF2EFL const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
+# else
+#  define IEMOPMEDIAF2EFL_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
+    static IEMOPMEDIAF2EFL const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
+# endif
+#else
+# define IEMOPMEDIAF2EFL_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
+#endif
+/** @def IEMOPMEDIAF2EFL_INIT_VARS
+ * Generate AVX function tables for the @a a_InstrNm instruction.
+ * @sa IEMOPMEDIAF2EFL_INIT_VARS_EX */
+#define IEMOPMEDIAF2EFL_INIT_VARS(a_InstrNm) \
+    IEMOPMEDIAF2EFL_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128),           RT_CONCAT3(iemAImpl_,a_InstrNm,_u256), \
+                                 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback),  RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
 
 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */
Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac	(revision 104262)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac	(revision 104263)
@@ -1770,4 +1770,22 @@
 EMIT_INSTR_PLUS_ICEBP vbroadcasti128, YMM1, FSxBX
 EMIT_INSTR_PLUS_ICEBP_C64 vbroadcasti128, YMM9, FSxBX
+
+;
+; VTESTPS
+;
+EMIT_INSTR_PLUS_ICEBP_XMM vtestps
+EMIT_INSTR_PLUS_ICEBP_YMM vtestps
+EMIT_INSTR_PLUS_ICEBP_XMM_98 vtestps
+EMIT_INSTR_PLUS_ICEBP_C64 vtestps, YMM9, YMM8
+EMIT_INSTR_PLUS_ICEBP_C64 vtestps, YMM9, FSxBX
+
+;
+; VTESTPD
+;
+EMIT_INSTR_PLUS_ICEBP_XMM vtestpd
+EMIT_INSTR_PLUS_ICEBP_YMM vtestpd
+EMIT_INSTR_PLUS_ICEBP_XMM_98 vtestpd
+EMIT_INSTR_PLUS_ICEBP_C64 vtestpd, YMM9, YMM8
+EMIT_INSTR_PLUS_ICEBP_C64 vtestpd, YMM9, FSxBX
 
 ;
Index: trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
===================================================================
--- trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32	(revision 104262)
+++ trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32	(revision 104263)
@@ -12790,4 +12790,146 @@
         {  bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64,  255,         RM_REG, T_AVX_256,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
         {  bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS);
+}
+
+
+/*
+ * VTESTPS
+ */
+BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vtestps(uint8_t bMode)
+{
+    static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
+            /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
+            /* => */ { 0, X86_EFL_CF, X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0, 0x7fffffff, 0, 0x7fffffff),
+            /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
+            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
+            /*src1*/ RTUINT256_INIT_C(0x7fffffff7fffffff, 0x4000000070000000, 0, 0x7fffff070000000),
+            /* => */ { 0, X86_EFL_ZF, X86_EFL_ZF } },
+        {   /*src2*/ RTUINT256_INIT_C(0xfacade00ffffffff, 0xf00dcafef1234567, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0xffffffff81234567, 0xfa7edeadfadec0de, 0, 0),
+            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0xf007ba11fa15efad, 0x8ffffffffe1afe15),
+            /*src1*/ RTUINT256_INIT_C(0x70bacc00707a11ed, 0, 0x8f00eefffeedc001, 0xfeeb1e00ffffffff),
+            /* => */ { 0, X86_EFL_CF, X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0xfa7edeadfadec0de, 0xfffffffff1234567, 0xfacade00ffffffff, 0xf00dcafef1234567),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0xfffffffff1234567, 0xfa7edeadfadec0de),
+            /* => */ { 0, X86_EFL_CF, 0 } },
+        {   /*src2*/ RTUINT256_INIT_C(0xfeeb1ebe8f1edbed, 0xfeeb1ebe8f1edbed, 0, 0x80ee8eee800080ee),
+            /*src1*/ RTUINT256_INIT_C(0, 0x8feab0108f0f0f0f, 0x80dd000081234567, 0x70bacc00707a11ed),
+            /* => */ { 0, X86_EFL_ZF, 0 } },
+        {   /*src2*/ RTUINT256_INIT_C(0xf01dc01dba5eba11, 0xacce55ed9defec75, 0, 0x70bacc00707a11ed),
+            /*src1*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0x70bacc00707a11ed, 0),
+            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF } },
+        {   /*src2*/ RTUINT256_INIT_C(0xcafec01dea7e5ef, 0x8f6f6ff080608fff, 0xefdb0f5fe793f600, 0x99fb1c399ff0cce),
+            /*src1*/ RTUINT256_INIT_C(0, 0x8ff7123497dcaeb4, 0, 0xd0d0c01dea7eeedf),
+            /* => */ { 0, 0, 0 } },
+    };
+
+    static BS3CPUINSTR3_TEST4_T const s_aTests16[] =
+    {
+        {  bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c16,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c16,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST4_T const s_aTests32[] =
+    {
+        {  bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c32,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c32,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST4_T const s_aTests64[] =
+    {
+        {  bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c64,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c64,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_XMM9_XMM8_icebp_c64,  255,         RM_REG, T_AVX_128,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_YMM9_YMM8_icebp_c64,  255,         RM_REG, T_AVX_256,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestps_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS);
+}
+
+
+/*
+ * VTESTPD
+ */
+BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vtestpd(uint8_t bMode)
+{
+    static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0x8000000000000000, 0x8fffffff00000000, 0x80000000ffffffff, 0xffffffffffffffff),
+            /*src1*/ RTUINT256_INIT_C(0x8000000000000000, 0x80000000ffffffff, 0x80000000f000f000, 0xffffffffffffffff),
+            /* => */ { 0, X86_EFL_CF, X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000),
+            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000),
+            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
+            /* => */ { 0, X86_EFL_ZF, X86_EFL_ZF } },
+        {   /*src2*/ RTUINT256_INIT_C(0xfacade007fffffff, 0xf00dcafe71234567, 0x7ab1ebadbad7ab1e, 0),
+            /*src1*/ RTUINT256_INIT_C(0xffffffff81234567, 0xfa7edeadfadec0de, 0x7fffffffffffffff, 0x7ab1ebadbad7ab1e),
+            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0xf007ba11fa15efad, 0x8ffffffffe1afe15),
+            /*src1*/ RTUINT256_INIT_C(0x70bacc00707a11ed, 0, 0x8f00eefffeedc001, 0xfeeb1e00ffffffff),
+            /* => */ { 0, X86_EFL_CF, X86_EFL_CF } },
+        {   /*src2*/ RTUINT256_INIT_C(0xfa7edeadfadec0de, 0xfffffffff1234567, 0xfacade00f00e0000, 0xf00dcafef1234567),
+            /*src1*/ RTUINT256_INIT_C(0x7fffffffffffffff, 0, 0xe1234567f1234567, 0x8a7edead0adec0de),
+            /* => */ { 0, X86_EFL_CF, 0 } },
+        {   /*src2*/ RTUINT256_INIT_C(0xfeeb1ebe7f1edbed, 0xfeeb1ebe8f1edbed, 0x7fffffffffffffff, 0x80ee8eee800080ee),
+            /*src1*/ RTUINT256_INIT_C(0, 0x8feab0108f0f0f0f, 0x80dd000081234567, 0x70bacc00707a11ed),
+            /* => */ { 0, X86_EFL_ZF, 0 } },
+        {   /*src2*/ RTUINT256_INIT_C(0xf01dc01dba5eba11, 0xacce55ed9defec75, 0x1fa7ca751abcdef0, 0x70bacc00f07a11ed),
+            /*src1*/ RTUINT256_INIT_C(0x7000f000f000f000, 0x70bacc00707a11ed, 0x70bacc00f07a11ed, 0x7fffffff0fff0fff),
+            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF } },
+        {   /*src2*/ RTUINT256_INIT_C(0xcafec01dea7e5ef, 0xdf6f6ff080608fff, 0xefdb0f5f6793f600, 0x99fb1c3300f0cced),
+            /*src1*/ RTUINT256_INIT_C(0, 0x9ff7123477dcaeb4, 0, 0xb0d0c01d7a7eeedf),
+            /* => */ { 0, 0, 0 } },
+    };
+
+    static BS3CPUINSTR3_TEST4_T const s_aTests16[] =
+    {
+        {  bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c16,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c16,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST4_T const s_aTests32[] =
+    {
+        {  bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c32,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c32,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+    };
+    static BS3CPUINSTR3_TEST4_T const s_aTests64[] =
+    {
+        {  bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c64,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_XMM9_XMM8_icebp_c64,  255,         RM_REG, T_AVX_128,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c64,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_YMM9_YMM8_icebp_c64,  255,         RM_REG, T_AVX_256,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
+        {  bs3CpuInstr3_vtestpd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
     };
     static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -14059,4 +14201,10 @@
 #endif
 #if defined(ALL_TESTS)
+        { "vtestps",                                        bs3CpuInstr3_vtestps, 0 },
+#endif
+#if defined(ALL_TESTS)
+        { "vtestpd",                                        bs3CpuInstr3_vtestpd, 0 },
+#endif
+#if defined(ALL_TESTS)
         { "[v]pavgb/[v]pavgw",                              bs3CpuInstr3_v_pavgb_pavgw, 0 },
 #endif
