Changeset 104278 in vbox for trunk/src/VBox/VMM/VMMAll/target-x86

Timestamp:

Apr 10, 2024 1:52:25 PM (10 months ago)

Author:

vboxsync

Message:

VMM/IEM: Implement a native emitter for the pxor,xorps,xorpd instructions, bugref:10652

File:

• trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

@@ -1872 +1872 @@
 
 
+
+#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
+/*********************************************************************************************************************************
+*   SIMD emitters.                                                                                                               *
+*********************************************************************************************************************************/
+
+/**
+ * Common emitter for the PXOR, XORPS, XORPD instructions - guest register / guest register variant.
+ */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmit_pxor_rr_u128(PIEMRECOMPILERSTATE pReNative, uint32_t off,
+                           uint8_t const idxSimdGstRegDst, uint8_t const idxSimdGstRegSrc)
+{
+    uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst),
+                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate);
+    uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc),
+                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly);
+
+#ifdef RT_ARCH_AMD64
+    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 5);
+
+    /* pxor xmm, xmm */
+    pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    if (idxSimdRegDst >= 8 || idxSimdRegSrc >= 8)
+        pCodeBuf[off++] =   (idxSimdRegSrc >= 8 ? X86_OP_REX_B : 0)
+                          | (idxSimdRegDst >= 8 ? X86_OP_REX_R : 0);
+    pCodeBuf[off++] = 0x0f;
+    pCodeBuf[off++] = 0xef;
+    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxSimdRegDst & 7, idxSimdRegSrc & 7);
+
+#elif defined(RT_ARCH_ARM64)
+    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
+
+    pCodeBuf[off++] = Armv8A64MkVecInstrEor(idxSimdRegDst, idxSimdRegDst, idxSimdRegSrc);
+#else
+# error "port me"
+#endif
+
+    iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst);
+    iemNativeSimdRegFreeTmp(pReNative, idxSimdRegSrc);
+
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+    return off;
+}
+
+
+/**
+ * Common emitter for the PXOR, XORPS, XORPD instructions - guest register / recompiler variable variant.
+ */
+DECL_INLINE_THROW(uint32_t)
+iemNativeEmit_pxor_rv_u128(PIEMRECOMPILERSTATE pReNative, uint32_t off,
+                           uint8_t const idxSimdGstRegDst, uint8_t const idxVarSrc)
+{
+    IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVarSrc);
+    IEMNATIVE_ASSERT_VAR_SIZE(pReNative, idxVarSrc, sizeof(RTUINT128U));
+
+    uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst),
+                                                                          kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate);
+    uint8_t const idxSimdRegSrc = iemNativeVarSimdRegisterAcquire(pReNative, idxVarSrc, &off, true /*fInitialized*/);
+
+
+#ifdef RT_ARCH_AMD64
+    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 5);
+
+    /* pxor xmm, xmm */
+    pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
+    if (idxSimdRegDst >= 8 || idxSimdRegSrc >= 8)
+        pCodeBuf[off++] =   (idxSimdRegSrc >= 8 ? X86_OP_REX_B : 0)
+                          | (idxSimdRegDst >= 8 ? X86_OP_REX_R : 0);
+    pCodeBuf[off++] = 0x0f;
+    pCodeBuf[off++] = 0xef;
+    pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxSimdRegDst & 7, idxSimdRegSrc & 7);
+
+#elif defined(RT_ARCH_ARM64)
+    PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1);
+
+    pCodeBuf[off++] = Armv8A64MkVecInstrEor(idxSimdRegDst, idxSimdRegDst, idxSimdRegSrc);
+#else
+# error "port me"
+#endif
+
+    iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst);
+    iemNativeVarRegisterRelease(pReNative, idxVarSrc);
+
+    IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
+    return off;
+}
+#endif
+
 #endif /* !VMM_INCLUDED_SRC_VMMAll_target_x86_IEMAllN8veEmit_x86_h */