Changeset 104294 in vbox

Timestamp:

Apr 11, 2024 12:28:26 PM (8 months ago)

Author:

vboxsync

Message:

VMM/IEM: Implement native emitters for psllw,pslld,psllq, bugref:10652

Location:

trunk

Files:

• include/iprt/armv8.h (modified) (3 diffs)
• src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (3 diffs)
• src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h (modified) (2 diffs)

trunk/include/iprt/armv8.h

@@ -4616 +4616 @@
 typedef enum ARMV8INSTRUSHIFTSZ
 {
-    kArmv8InstrShiftSz_U8  = 16,  /**< Byte. */
-    kArmv8InstrShiftSz_U16 = 32,  /**< Halfword. */
-    kArmv8InstrShiftSz_U32 = 64,  /**< 32-bit. */
-    kArmv8InstrShiftSz_U64 = 128  /**< 64-bit. */
+    kArmv8InstrShiftSz_U8  =  8,  /**< Byte. */
+    kArmv8InstrShiftSz_U16 = 16,  /**< Halfword. */
+    kArmv8InstrShiftSz_U32 = 32,  /**< 32-bit. */
+    kArmv8InstrShiftSz_U64 = 64   /**< 64-bit. */
 } ARMV8INSTRUSHIFTSZ;
 
@@ -4646 +4646 @@
                || (enmSz == kArmv8InstrShiftSz_U64 && cShift <= 64)));
 
-    return UINT32_C(0xf000400)
+    return UINT32_C(0x0f000400)
          | ((uint32_t)f128Bit << 30)
          | ((uint32_t)fUnsigned << 29)
-         | (((uint32_t)enmSz - cShift) << 16)
+         | ((((uint32_t)enmSz << 1) - cShift) << 16)
          | ((uint32_t)fRound << 13)
          | ((uint32_t)fAccum << 12)
@@ -4655 +4655 @@
          | iVecRegDst;
 }
+
+
+/**
+ * A64: Encodes SHL (vector, register).
+ *
+ * @returns The encoded instruction.
+ * @param   iVecRegDst  The vector register to put the result into.
+ * @param   iVecRegSrc  The vector source register.
+ * @param   cShift      Number of bits to shift.
+ * @param   enmSz       Element size.
+ * @param   f128Bit     Flag whether this operates on the full 128-bit (true, default) of the vector register
+ *                      or just the low 64-bit (false).
+ */
+DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShlImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
+                                                     bool f128Bit = true)
+{
+    Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
+    Assert(   (enmSz == kArmv8InstrShiftSz_U8 &&  cShift < 8)
+           || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
+           || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32)
+           || (enmSz == kArmv8InstrShiftSz_U64 && cShift < 64));
+
+    return UINT32_C(0x0f005400)
+         | ((uint32_t)f128Bit << 30)
+         | (((uint32_t)enmSz | cShift) << 16)
+         | (iVecRegSrc << 5)
+         | iVecRegDst;
+}
 /** @} */
 

trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h

@@ -6612 +6612 @@
 {
 //    IEMOP_MNEMONIC2(RI, PSLLW, psllw, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
-    SSE2_SHIFT_BODY_Imm(psllw, bRm, 0);
+    SSE2_SHIFT_BODY_Imm(psllw, bRm, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 
@@ -6688 +6688 @@
 {
 //    IEMOP_MNEMONIC2(RI, PSLLD, pslld, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
-    SSE2_SHIFT_BODY_Imm(pslld, bRm, 0);
+    SSE2_SHIFT_BODY_Imm(pslld, bRm, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 
@@ -6756 +6756 @@
 {
 //    IEMOP_MNEMONIC2(RI, PSLLQ, psllq, Ux, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_X86_SSE, 0);
-    SSE2_SHIFT_BODY_Imm(psllq, bRm, 0);
+    SSE2_SHIFT_BODY_Imm(psllq, bRm, RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64);
 }
 

trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

@@ -2057 +2057 @@
             uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst), \
                                                                                   kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); \
-            PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 5); \
+            PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6); \
             pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; \
             if (idxSimdRegDst >= 8) \
@@ -2097 +2097 @@
 IEMNATIVE_NATIVE_EMIT_SHIFT_RIGHT_IMM_U128(psrlq, 64, kArmv8InstrShiftSz_U64, 0x73);
 
+
+/**
+ * Common emitter for the shift left with immediate instructions.
+ */
+#ifdef RT_ARCH_AMD64
+# define IEMNATIVE_NATIVE_EMIT_SHIFT_LEFT_IMM_U128(a_Instr, a_cShiftMax, a_ArmElemSz, a_bOpcX86) \
+    DECL_INLINE_THROW(uint32_t) \
+    RT_CONCAT3(iemNativeEmit_,a_Instr,_ri_u128)(PIEMRECOMPILERSTATE pReNative, uint32_t off, \
+                                                uint8_t const idxSimdGstRegDst, uint8_t const bImm) \
+    { \
+        if (bImm) \
+        { \
+            uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst), \
+                                                                                  kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); \
+            PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6); \
+            pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; \
+            if (idxSimdRegDst >= 8) \
+                pCodeBuf[off++] = X86_OP_REX_B; \
+            pCodeBuf[off++] = 0x0f; \
+            pCodeBuf[off++] = (a_bOpcX86); \
+            pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 6, idxSimdRegDst & 7); \
+            pCodeBuf[off++] = bImm; \
+            iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); \
+            IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off); \
+        } \
+        /* Immediate 0 is a nop. */ \
+        return off; \
+    }
+#elif defined(RT_ARCH_ARM64)
+# define IEMNATIVE_NATIVE_EMIT_SHIFT_LEFT_IMM_U128(a_Instr, a_cShiftMax, a_ArmElemSz, a_bOpcX86) \
+    DECL_INLINE_THROW(uint32_t) \
+    RT_CONCAT3(iemNativeEmit_,a_Instr,_ri_u128)(PIEMRECOMPILERSTATE pReNative, uint32_t off, \
+                                                uint8_t const idxSimdGstRegDst, uint8_t const bImm) \
+    { \
+        if (bImm) /* bImm == 0 is a nop */ \
+        { \
+            uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst), \
+                                                                                  kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); \
+            PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1); \
+            if (bImm < (a_cShiftMax)) \
+                pCodeBuf[off++] = Armv8A64MkVecInstrShlImm(idxSimdRegDst, idxSimdRegDst, bImm, (a_ArmElemSz)); \
+            else /* Everything >= a_cShiftMax sets the register to zero. */ \
+                pCodeBuf[off++] = Armv8A64MkVecInstrEor(idxSimdRegDst, idxSimdRegDst, idxSimdRegDst); \
+            iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); \
+            IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off); \
+        } \
+        return off; \
+    }
+#else
+# error "Port me"
+#endif
+
+IEMNATIVE_NATIVE_EMIT_SHIFT_LEFT_IMM_U128(psllw, 16, kArmv8InstrShiftSz_U16, 0x71);
+IEMNATIVE_NATIVE_EMIT_SHIFT_LEFT_IMM_U128(pslld, 32, kArmv8InstrShiftSz_U32, 0x72);
+IEMNATIVE_NATIVE_EMIT_SHIFT_LEFT_IMM_U128(psllq, 64, kArmv8InstrShiftSz_U64, 0x73);
+
 #endif