Changeset 104322 in vbox
- Timestamp:
- Apr 12, 2024 3:18:43 PM (8 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllN8veHlpA-arm64.S
r104230 r104322 32 32 #include <iprt/asmdefs-arm.h> 33 33 34 #ifdef AssertCompile 35 # undef AssertCompile 36 #endif 37 #define AssertCompile(a_Expr) 38 #define INCLUDED_FROM_ARM64_ASSEMBLY 39 #include "IEMN8veRecompiler.h" 40 41 #define IEM_HLP_FUNCTION_ALIGNMENT 0x20 34 42 35 43 BEGINCODE 36 44 37 45 .extern NAME(iemThreadedFunc_BltIn_LogCpuStateWorker) 46 47 #ifdef IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON 48 /** 49 * This is the common prologue of a TB, saving all volatile registers 50 * and creating the stack frame for saving temporary values. 51 * 52 * @param pVCpu (x0) The cross-context vCPU structure pointer. 53 * @param pCpumCtx (x1) The cross-context CPUM context structure pointer. 54 * @param pTbStart (x2) The TB instruction start pointer. 55 */ 56 ALIGNCODE(IEM_HLP_FUNCTION_ALIGNMENT) 57 BEGINPROC_HIDDEN iemNativeTbEntry 58 # ifdef RT_OS_DARWIN 59 pacibsp 60 # endif 61 stp x19, x20, [sp, #-IEMNATIVE_FRAME_SAVE_REG_SIZE]! /* Allocate space for saving registers and place x19+x20 at the bottom. */ 62 stp x21, x22, [sp, #0x10] /* Save x21 thru x28 (SP remains unchanged). */ 63 stp x23, x24, [sp, #0x20] 64 stp x25, x26, [sp, #0x30] 65 stp x27, x28, [sp, #0x40] 66 stp x29, x30, [sp, #0x50] /* Save the BP and LR (ret address) registers at the top of the frame. */ 67 add x29, sp, #(IEMNATIVE_FRAME_SAVE_REG_SIZE - 16) /* Set BP to point to the old BP stack address */ 68 sub sp, sp, #IEMNATIVE_FRAME_VAR_SIZE /* Allocate the variable area from SP. */ 69 mov IEMNATIVE_REG_FIXED_PVMCPU_ASM, x0 70 mov IEMNATIVE_REG_FIXED_PCPUMCTX_ASM, x1 71 # ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP 72 str x29, [IEMNATIVE_REG_FIXED_PVMCPU_ASM, #0x7c8] /* Save the frame pointer to pvTbFramePointerR3 */ /** @todo Get rid of this hardcoded assumption */ 73 # endif 74 /* 75 * Everything is done, jump to the start of the TB. 76 */ 77 br x2 78 #endif 79 38 80 39 81 /** … … 53 95 * it ourselves, I think. 54 96 */ 97 ALIGNCODE(IEM_HLP_FUNCTION_ALIGNMENT) 55 98 BEGINPROC_HIDDEN iemNativeTbLongJmp 56 99 /* … … 81 124 * so the impact of inserting LogCpuState is minimal to the other TB code. 82 125 */ 126 ALIGNCODE(IEM_HLP_FUNCTION_ALIGNMENT) 83 127 BEGINPROC_HIDDEN iemNativeHlpAsmSafeWrapLogCpuState 84 128 #ifdef RT_OS_DARWIN -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veHlpA.asm
r103376 r104322 32 32 %include "VBox/asmdefs.mac" 33 33 34 ;; @todo r=aeichner The following is copied from IEMInternal.h 35 ;%define VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP - not enabled right now on amd64 36 37 ;; @todo r=aeichner The following defines are copied from IEMN8veRecompiler.h 38 39 ; /** @def IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON 40 ; * Enables having only a single prologue for native TBs. */ 41 %define IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON 42 43 ; /** An stack alignment adjustment (between non-volatile register pushes and 44 ; * the stack variable area, so the latter better aligned). */ 45 %define IEMNATIVE_FRAME_ALIGN_SIZE 8 46 47 ; /** The size of the area for stack variables and spills and stuff. 48 ; * @note This limit is duplicated in the python script(s). We add 0x40 for 49 ; * alignment padding. */ 50 %define IEMNATIVE_FRAME_VAR_SIZE (0xc0 + 0x40) 51 52 ; This needs to correspond to IEMNATIVE_REG_FIXED_PVMCPU in IEMN8veRecompiler.h 53 %define IEMNATIVE_REG_FIXED_PVMCPU_ASM xBX 54 55 ; /** Number of stack arguments slots for calls made from the frame. */ 56 %ifdef RT_OS_WINDOWS 57 %define IEMNATIVE_FRAME_STACK_ARG_COUNT 4 58 %else 59 %define IEMNATIVE_FRAME_STACK_ARG_COUNT 2 60 %endif 61 ; /** Number of any shadow arguments (spill area) for calls we make. */ 62 %ifdef RT_OS_WINDOWS 63 %define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 4 64 %else 65 %define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0 66 %endif 67 34 68 35 69 BEGINCODE … … 37 71 extern NAME(iemThreadedFunc_BltIn_LogCpuStateWorker) 38 72 extern NAME(iemNativeHlpCheckTlbLookup) 73 74 %ifdef IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON 75 ;; 76 ; This is the common prologue of a TB, saving all volatile registers 77 ; and creating the stack frame for saving temporary values. 78 ; 79 ; @param pVCpu (gcc:rdi, msc:rcx) The cross-context vCPU structure pointer. 80 ; @param pTbStart (gcc:rsi, msc:rdx) The TB instruction start pointer. 81 ; 82 BEGINPROC iemNativeTbEntry 83 push rbp 84 mov rbp, rsp 85 push rbx 86 %ifdef ASM_CALL64_MSC 87 mov IEMNATIVE_REG_FIXED_PVMCPU_ASM, rcx 88 push rsi 89 push rdi 90 %else 91 mov IEMNATIVE_REG_FIXED_PVMCPU_ASM, rdi 92 %endif 93 push r12 94 push r13 95 push r14 96 push r15 97 %ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP 98 %error "Port me" 99 %endif 100 sub rsp, IEMNATIVE_FRAME_ALIGN_SIZE \ 101 + IEMNATIVE_FRAME_VAR_SIZE \ 102 + IEMNATIVE_FRAME_STACK_ARG_COUNT * 8 \ 103 + IEMNATIVE_FRAME_SHADOW_ARG_COUNT * 8 \ 104 105 %ifdef ASM_CALL64_MSC 106 jmp rdx 107 %else 108 jmp rsi 109 %endif 110 ENDPROC iemNativeTbEntry 111 %endif 39 112 40 113 -
trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompiler.cpp
r104283 r104322 6402 6402 6403 6403 6404 #ifndef IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON 6404 6405 /** 6405 6406 * Emits a standard prolog. … … 6515 6516 return off; 6516 6517 } 6518 #endif 6517 6519 6518 6520 … … 9110 9112 IEMNATIVE_TRY_SETJMP(pReNative, rc) 9111 9113 { 9114 #ifndef IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON 9112 9115 /* 9113 9116 * Emit prolog code (fixed). 9114 9117 */ 9115 9118 off = iemNativeEmitProlog(pReNative, off); 9119 #endif 9116 9120 9117 9121 /* -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdRecompiler.cpp
r104321 r104322 2689 2689 iemThreadedLogCurInstr(pVCpu, "EXn", 0); 2690 2690 # endif 2691 # ifdef RT_ARCH_AMD64 2691 2692 # ifndef IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON 2693 # ifdef RT_ARCH_AMD64 2692 2694 VBOXSTRICTRC const rcStrict = ((PFNIEMTBNATIVE)pTb->Native.paInstructions)(pVCpu); 2695 # else 2696 VBOXSTRICTRC const rcStrict = ((PFNIEMTBNATIVE)pTb->Native.paInstructions)(pVCpu, &pVCpu->cpum.GstCtx); 2697 # endif 2693 2698 # else 2694 VBOXSTRICTRC const rcStrict = ((PFNIEMTBNATIVE)pTb->Native.paInstructions)(pVCpu, &pVCpu->cpum.GstCtx); 2699 # ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP 2700 AssertCompileMemberOffset(VMCPUCC, iem.s.pvTbFramePointerR3, 0x7c8); /* This is assumed in iemNativeTbEntry */ 2701 # endif 2702 # ifdef RT_ARCH_AMD64 2703 VBOXSTRICTRC const rcStrict = iemNativeTbEntry(pVCpu, (uintptr_t)pTb->Native.paInstructions); 2704 # else 2705 VBOXSTRICTRC const rcStrict = iemNativeTbEntry(pVCpu, &pVCpu->cpum.GstCtx, (uintptr_t)pTb->Native.paInstructions); 2706 # endif 2695 2707 # endif 2708 2696 2709 # ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP 2697 2710 pVCpu->iem.s.pvTbFramePointerR3 = NULL; -
trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
r104274 r104322 68 68 /** Always count instructions for now. */ 69 69 # define IEMNATIVE_WITH_INSTRUCTION_COUNTING 70 #endif 71 72 /** @def IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON 73 * Enables having only a single prologue for native TBs. */ 74 #if 1 || defined(DOXYGEN_RUNNING) 75 # define IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON 70 76 #endif 71 77 … … 199 205 #elif defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING) 200 206 # define IEMNATIVE_REG_FIXED_PVMCPU ARMV8_A64_REG_X28 207 # define IEMNATIVE_REG_FIXED_PVMCPU_ASM x28 201 208 # define IEMNATIVE_REG_FIXED_PCPUMCTX ARMV8_A64_REG_X27 209 # define IEMNATIVE_REG_FIXED_PCPUMCTX_ASM x27 202 210 # define IEMNATIVE_REG_FIXED_TMP0 ARMV8_A64_REG_X15 203 211 # if defined(IEMNATIVE_WITH_DELAYED_PC_UPDATING) && 0 /* debug the updating with a shadow RIP. */ … … 417 425 418 426 427 /** @todo r=aeichner Can this be made prettier? */ 428 #ifndef INCLUDED_FROM_ARM64_ASSEMBLY 429 419 430 /** Native code generator label types. */ 420 431 typedef enum … … 2480 2491 2481 2492 2493 #ifdef IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON 2494 # ifdef RT_ARCH_AMD64 2495 extern "C" IEM_DECL_NATIVE_HLP_DEF(VBOXSTRICTRC, iemNativeTbEntry, (PVMCPUCC pVCpu, uintptr_t pTbInsn)); 2496 # elif defined(RT_ARCH_ARM64) 2497 extern "C" IEM_DECL_NATIVE_HLP_DEF(VBOXSTRICTRC, iemNativeTbEntry, (PVMCPUCC pVCpu, PCPUMCTX pCpumCtx, uintptr_t pTbInsn)); 2498 # endif 2499 #endif 2500 2501 #endif /* !INCLUDED_FROM_ARM64_ASSEMBLY */ 2502 2482 2503 /** @} */ 2483 2504
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