Changeset 104383 in vbox for trunk/src/VBox/VMM/include

Timestamp:

Apr 19, 2024 8:00:51 PM (10 months ago)

Author:

vboxsync

Message:

VMM/IEM: Automtically convert IEMInternal.h & IEMN8veRecompiler.h into nasm/yasm include files so IEMAllN8veHlpA.asm can make use of some of the constants define in them for the prolog code. [doxygen] bugref:10653 bugref:10370

Location:

trunk/src/VBox/VMM/include

Files:

• IEMInternal.h (modified) (1 diff)
• IEMN8veRecompiler.h (modified) (3 diffs)

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -212 +212 @@
  * Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
 #if !defined(IEM_WITH_THREE_0F_38) || defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
-# ifdef IEM_WITHOUT_THREE_0F_38
+# ifndef IEM_WITHOUT_THREE_0F_38
 #  define IEM_WITH_THREE_0F_38
 # endif

trunk/src/VBox/VMM/include/IEMN8veRecompiler.h

@@ -190 +190 @@
  * Dedicated temporary SIMD register. */
 #endif
-#ifdef RT_ARCH_AMD64
-# define IEMNATIVE_REG_FIXED_PVMCPU         X86_GREG_xBX
-# define IEMNATIVE_REG_FIXED_PVMCPU_ASM     xBX
-# define IEMNATIVE_REG_FIXED_TMP0           X86_GREG_x11
-# define IEMNATIVE_REG_FIXED_MASK           (  RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
-                                             | RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \
-                                             | RT_BIT_32(X86_GREG_xSP) \
-                                             | RT_BIT_32(X86_GREG_xBP) )
-
-# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
-#  define IEMNATIVE_SIMD_REG_FIXED_TMP0     5 /* xmm5/ymm5 */
-#  ifndef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
-#   ifndef _MSC_VER /* On Windows xmm6 through xmm15 are marked as callee saved. */
-#    define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
-#   endif
-#  endif
-#  ifdef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
-#   define IEMNATIVE_SIMD_REG_FIXED_MASK    (RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0))
-#  else
-#   define IEMNATIVE_SIMD_REG_FIXED_MASK    (  UINT32_C(0xffc0) \
-                                             | RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0))
-#  endif
-# endif
-
-#elif defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING)
+#if defined(RT_ARCH_ARM64) || defined(DOXYGEN_RUNNING) /* arm64 goes first because of doxygen */
 # define IEMNATIVE_REG_FIXED_PVMCPU         ARMV8_A64_REG_X28
 # define IEMNATIVE_REG_FIXED_PVMCPU_ASM     RT_CONCAT(x,IEMNATIVE_REG_FIXED_PVMCPU)
@@ -242 +218 @@
 #   define IEMNATIVE_SIMD_REG_FIXED_MASK    RT_BIT_32(ARMV8_A64_REG_Q30)
 #  else
-/*
- * ARM64 has 32 128-bit registers only, in order to support emulating 256-bit registers we pair
- * two real registers statically to one virtual for now, leaving us with only 16 256-bit registers.
- * We always pair v0 with v1, v2 with v3, etc. so we mark the higher register as fixed
- * and the register allocator assumes that it will be always free when the lower is picked.
- *
- * Also ARM64 declares the low 64-bit of v8-v15 as callee saved, so we don't touch them in order to avoid
- * having to save and restore them in the prologue/epilogue.
+/** @note
+ * ARM64 has 32 registers, but they are only 128-bit wide.  So, in order to
+ * support emulating 256-bit registers we pair two real registers statically to
+ * one virtual for now, leaving us with only 16 256-bit registers. We always
+ * pair v0 with v1, v2 with v3, etc. so we mark the higher register as fixed and
+ * the register allocator assumes that it will be always free when the lower is
+ * picked.
+ *
+ * Also ARM64 declares the low 64-bit of v8-v15 as callee saved, so we don't
+ * touch them in order to avoid having to save and restore them in the
+ * prologue/epilogue.
  */
 #   define IEMNATIVE_SIMD_REG_FIXED_MASK    (  UINT32_C(0xff00) \
@@ -269 +248 @@
                                              | RT_BIT_32(ARMV8_A64_REG_Q3) \
                                              | RT_BIT_32(ARMV8_A64_REG_Q1))
+#  endif
+# endif
+
+#elif defined(RT_ARCH_AMD64)
+# define IEMNATIVE_REG_FIXED_PVMCPU         X86_GREG_xBX
+# define IEMNATIVE_REG_FIXED_PVMCPU_ASM     xBX
+# define IEMNATIVE_REG_FIXED_TMP0           X86_GREG_x11
+# define IEMNATIVE_REG_FIXED_MASK           (  RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
+                                             | RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \
+                                             | RT_BIT_32(X86_GREG_xSP) \
+                                             | RT_BIT_32(X86_GREG_xBP) )
+
+# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
+#  define IEMNATIVE_SIMD_REG_FIXED_TMP0     5 /* xmm5/ymm5 */
+#  ifndef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
+#   ifndef _MSC_VER
+#    define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
+#   endif
+#  endif
+#  ifdef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
+#   define IEMNATIVE_SIMD_REG_FIXED_MASK    (RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0))
+#  else
+/** @note On Windows/AMD64 xmm6 through xmm15 are marked as callee saved. */
+#   define IEMNATIVE_SIMD_REG_FIXED_MASK    (  UINT32_C(0xffc0) \
+                                             | RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0))
 #  endif
 # endif