Changeset 104400 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Apr 23, 2024 1:22:27 AM (10 months ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-x0.c
r103005 r104400 3741 3741 BS3REGCTX CtxExpected; 3742 3742 unsigned iTest; 3743 unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler ? g_cBs3ThresholdNativeRecompiler : 1; 3744 unsigned iRecompRun; 3743 3745 3744 3746 /* make sure they're allocated */ … … 3851 3853 //Bs3TestPrintf("cs:rip=%04RX16:%04RX64\n", Ctx.cs, Ctx.rip.u); 3852 3854 3853 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3854 if (s_aTests[iTest].iWrap == 0 || !s_aTests[iTest].fOpSizePfx) 3855 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 3856 else 3857 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3855 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 3856 { 3857 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3858 if (s_aTests[iTest].iWrap == 0 || !s_aTests[iTest].fOpSizePfx) 3859 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 3860 else 3861 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3862 } 3858 3863 g_usBs3TestStep++; 3859 3864 3860 3865 /* Again single stepping: */ 3861 3866 //Bs3TestPrintf("stepping...\n"); 3862 Bs3RegSetDr6(0);3863 3867 Ctx.rflags.u16 |= X86_EFL_TF; 3864 3868 CtxExpected.rflags.u16 = Ctx.rflags.u16; 3865 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3866 if (s_aTests[iTest].iWrap == 0 || !s_aTests[iTest].fOpSizePfx) 3867 bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS); 3868 else 3869 { 3870 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3871 bs3CpuBasic2_CheckDr6InitVal(); 3869 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 3870 { 3871 Bs3RegSetDr6(0); 3872 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3873 if (s_aTests[iTest].iWrap == 0 || !s_aTests[iTest].fOpSizePfx) 3874 bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS); 3875 else 3876 { 3877 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3878 bs3CpuBasic2_CheckDr6InitVal(); 3879 } 3872 3880 } 3873 3881 Ctx.rflags.u16 &= ~X86_EFL_TF; … … 3891 3899 CtxExpected.rip.u = Ctx.rip.u = BS3_FP_OFF(s_aTests[iTest].pfnTest); 3892 3900 //Bs3TestPrintf("cs:rip=%04RX16:%04RX64 v1\n", Ctx.cs, Ctx.rip.u); 3893 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3894 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3901 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 3902 { 3903 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3904 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3905 } 3895 3906 g_usBs3TestStep++; 3896 3907 } … … 3911 3922 CtxExpected.rsp.u -= s_aTests[iTest].fOpSizePfx ? 4 : 2; 3912 3923 //Bs3TestPrintf("cs:rip=%04RX16:%04RX64 v2\n", Ctx.cs, Ctx.rip.u); 3913 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3914 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3924 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 3925 { 3926 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3927 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3928 } 3915 3929 g_usBs3TestStep++; 3916 3930 } … … 4064 4078 if (BS3_MODE_IS_16BIT_SYS(bMode)) 4065 4079 g_uBs3TrapEipHint = s_aTests[iTest].fOpSizePfx ? 0 : Ctx.rip.u32; 4066 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4067 4068 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 4080 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 4081 { 4082 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4083 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 4084 } 4069 4085 g_usBs3TestStep++; 4070 4086 4071 4087 /* Again single stepping: */ 4072 4088 //Bs3TestPrintf("stepping...\n"); 4073 Bs3RegSetDr6(0);4074 4089 Ctx.rflags.u16 |= X86_EFL_TF; 4075 4090 CtxExpected.rflags.u16 = Ctx.rflags.u16; 4076 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4077 bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS); 4091 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 4092 { 4093 Bs3RegSetDr6(0); 4094 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4095 bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS); 4096 } 4078 4097 Ctx.rflags.u16 &= ~X86_EFL_TF; 4079 4098 CtxExpected.rflags.u16 = Ctx.rflags.u16; … … 4677 4696 unsigned iTest; 4678 4697 BS3PTRUNION StkPtr; 4698 unsigned const cMaxRecompRuns = g_cBs3ThresholdNativeRecompiler ? g_cBs3ThresholdNativeRecompiler : 1; 4699 unsigned iRecompRun; 4679 4700 4680 4701 /* make sure they're allocated */ … … 4734 4755 //Bs3TestPrintf("cs:rip=%04RX16:%04RX64 -> %04RX16:%04RX64\n", Ctx.cs, Ctx.rip.u, CtxExpected.cs, CtxExpected.rip.u); 4735 4756 //Bs3TestPrintf("ss:rsp=%04RX16:%04RX64\n", Ctx.ss, Ctx.rsp.u); 4736 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx ? 4 : 2); 4737 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4738 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 4757 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 4758 { 4759 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx ? 4 : 2); 4760 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4761 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 4762 } 4739 4763 g_usBs3TestStep++; 4740 4764 4741 4765 /* Again single stepping: */ 4742 4766 //Bs3TestPrintf("stepping...\n"); 4743 Bs3RegSetDr6(X86_DR6_INIT_VAL);4744 4767 Ctx.rflags.u16 |= X86_EFL_TF; 4745 4768 CtxExpected.rflags.u16 = Ctx.rflags.u16; 4746 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx ? 4 : 2); 4747 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4748 bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS); 4769 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 4770 { 4771 Bs3RegSetDr6(X86_DR6_INIT_VAL); 4772 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx ? 4 : 2); 4773 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4774 bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS); 4775 } 4749 4776 Ctx.rflags.u16 &= ~X86_EFL_TF; 4750 4777 CtxExpected.rflags.u16 = Ctx.rflags.u16; … … 4812 4839 //Bs3TestPrintf("cs:rip=%04RX16:%04RX64 -> %04RX16:%04RX64\n", Ctx.cs, Ctx.rip.u, CtxExpected.cs, CtxExpected.rip.u); 4813 4840 //Bs3TestPrintf("ss:rsp=%04RX16:%04RX64\n", Ctx.ss, Ctx.rsp.u); 4814 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx ? 2 : 4); 4815 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4816 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 4841 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 4842 { 4843 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx ? 2 : 4); 4844 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4845 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 4846 } 4817 4847 g_usBs3TestStep++; 4818 4848 4819 4849 /* Again single stepping: */ 4820 4850 //Bs3TestPrintf("stepping...\n"); 4821 Bs3RegSetDr6(X86_DR6_INIT_VAL);4822 4851 Ctx.rflags.u16 |= X86_EFL_TF; 4823 4852 CtxExpected.rflags.u16 = Ctx.rflags.u16; 4824 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx ? 2 : 4); 4825 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4826 bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS); 4853 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 4854 { 4855 Bs3RegSetDr6(X86_DR6_INIT_VAL); 4856 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx ? 2 : 4); 4857 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4858 bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS); 4859 } 4827 4860 Ctx.rflags.u16 &= ~X86_EFL_TF; 4828 4861 CtxExpected.rflags.u16 = Ctx.rflags.u16; … … 4901 4934 //Bs3TestPrintf("cs:rip=%04RX16:%04RX64 -> %04RX16:%04RX64\n", Ctx.cs, Ctx.rip.u, CtxExpected.cs, CtxExpected.rip.u); 4902 4935 //Bs3TestPrintf("ss:rsp=%04RX16:%04RX64\n", Ctx.ss, Ctx.rsp.u); 4903 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx && !fFix64OpSize ? 2 : 8); 4904 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4905 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 4936 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 4937 { 4938 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx && !fFix64OpSize ? 2 : 8); 4939 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4940 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 4941 } 4906 4942 g_usBs3TestStep++; 4907 4943 4908 4944 /* Again single stepping: */ 4909 4945 //Bs3TestPrintf("stepping...\n"); 4910 Bs3RegSetDr6(X86_DR6_INIT_VAL);4911 4946 Ctx.rflags.u16 |= X86_EFL_TF; 4912 4947 CtxExpected.rflags.u16 = Ctx.rflags.u16; 4913 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx && !fFix64OpSize ? 2 : 8); 4914 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4915 bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS); 4948 for (iRecompRun = 0; iRecompRun < cMaxRecompRuns; iRecompRun++) 4949 { 4950 Bs3RegSetDr6(X86_DR6_INIT_VAL); 4951 bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx && !fFix64OpSize ? 2 : 8); 4952 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 4953 bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS); 4954 } 4916 4955 Ctx.rflags.u16 &= ~X86_EFL_TF; 4917 4956 CtxExpected.rflags.u16 = Ctx.rflags.u16;
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