VirtualBox

Changeset 10465 in vbox


Ignore:
Timestamp:
Jul 10, 2008 11:51:19 AM (17 years ago)
Author:
vboxsync
Message:

Cleaned up

Location:
trunk/src/VBox/VMM
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/HWACCM.cpp

    r9986 r10465  
    297297            LogRel(("HWACCM: Dual monitor treatment        = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
    298298
    299             LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS    = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
    300             val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
     299            LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS    = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
     300            val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
    301301            if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
    302302                LogRel(("HWACCM:    VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
    303303            if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
    304304                LogRel(("HWACCM:    VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
    305             val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
     305            val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
    306306            if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
    307307                LogRel(("HWACCM:    VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
    … …  
    309309                LogRel(("HWACCM:    VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
    310310
    311             LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS   = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
    312             val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
     311            LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS   = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
     312            val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
    313313            if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
    314314                LogRel(("HWACCM:    VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
    … …  
    343343            if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
    344344                LogRel(("HWACCM:    VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
    345             val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
     345
     346            val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
    346347            if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
    347348                LogRel(("HWACCM:    VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
    … …  
    377378                LogRel(("HWACCM:    VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
    378379
    379             LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS       = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
    380             val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
     380            LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS       = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
     381            val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
    381382            if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
    382383                LogRel(("HWACCM:    VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
    … …  
    385386            if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
    386387                LogRel(("HWACCM:    VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
    387             val = pVM->hwaccm.s.vmx.msr.vmx_entry;
     388            val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
    388389            if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
    389390                LogRel(("HWACCM:    VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
    … …  
    393394                LogRel(("HWACCM:    VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
    394395
    395             LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS        = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
    396             val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
     396            LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS        = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
     397            val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
    397398            if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
    398399                LogRel(("HWACCM:    VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
    399400            if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
    400401                LogRel(("HWACCM:    VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
    401             val = pVM->hwaccm.s.vmx.msr.vmx_exit;
     402            val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
    402403            if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
    403404                LogRel(("HWACCM:    VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));

  • trunk/src/VBox/VMM/HWACCMInternal.h

    r10359 r10465  
    143143typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
    144144
     145/* VT-x capability qword. */
     146typedef union
     147{
     148    struct
     149    {
     150        uint32_t        disallowed0;
     151        uint32_t        allowed1;
     152    } n;
     153    uint64_t            u;
     154} VMX_CAPABILITY;
     155
    145156/**
    146157 * HWACCM VM Instance data.
    … …  
    223234            uint64_t                feature_ctrl;
    224235            uint64_t                vmx_basic_info;
    225             uint64_t                vmx_pin_ctls;
    226             uint64_t                vmx_proc_ctls;
    227             uint64_t                vmx_exit;
    228             uint64_t                vmx_entry;
     236            VMX_CAPABILITY          vmx_pin_ctls;
     237            VMX_CAPABILITY          vmx_proc_ctls;
     238            VMX_CAPABILITY          vmx_exit;
     239            VMX_CAPABILITY          vmx_entry;
    229240            uint64_t                vmx_misc;
    230241            uint64_t                vmx_cr0_fixed0;

  • trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp

    r10301 r10465  
    8787            uint64_t                feature_ctrl;
    8888            uint64_t                vmx_basic_info;
    89             uint64_t                vmx_pin_ctls;
    90             uint64_t                vmx_proc_ctls;
    91             uint64_t                vmx_exit;
    92             uint64_t                vmx_entry;
     89            VMX_CAPABILITY          vmx_pin_ctls;
     90            VMX_CAPABILITY          vmx_proc_ctls;
     91            VMX_CAPABILITY          vmx_exit;
     92            VMX_CAPABILITY          vmx_entry;
    9393            uint64_t                vmx_misc;
    9494            uint64_t                vmx_cr0_fixed0;
    … …  
    210210
    211211                        HWACCMR0Globals.vmx.msr.vmx_basic_info  = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
    212                         HWACCMR0Globals.vmx.msr.vmx_pin_ctls    = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
    213                         HWACCMR0Globals.vmx.msr.vmx_proc_ctls  = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
    214                         HWACCMR0Globals.vmx.msr.vmx_exit        = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
    215                         HWACCMR0Globals.vmx.msr.vmx_entry       = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
     212                        HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u  = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
     213                        HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
     214                        HWACCMR0Globals.vmx.msr.vmx_exit.u      = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
     215                        HWACCMR0Globals.vmx.msr.vmx_entry.u     = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
    216216                        HWACCMR0Globals.vmx.msr.vmx_misc        = ASMRdMsr(MSR_IA32_VMX_MISC);
    217217                        HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0  = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);

  • trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

    r10464 r10465  
    166166    memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
    167167
    168     if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
     168    if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
    169169    {
    170170        /* Allocate one page for the virtual APIC mmio cache. */
    … …  
    254254     * Set required bits to one and zero according to the MSR capabilities.
    255255     */
    256     val  = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
     256    val  = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
    257257    /* External and non-maskable interrupts cause VM-exits. */
    258258    val  = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
    259     val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
     259    val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
    260260
    261261    rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
    … …  
    265265     * Set required bits to one and zero according to the MSR capabilities.
    266266     */
    267     val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
     267    val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
    268268    /* Program which event cause VM-exits and which features we want to use. */
    269269    val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
    … …  
    277277
    278278#if HC_ARCH_BITS == 64
    279     if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
     279    if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
    280280    {
    281281        /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
    … …  
    289289    /* Mask away the bits that the CPU doesn't support */
    290290    /** @todo make sure they don't conflict with the above requirements. */
    291     val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
     291    val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
    292292    pVM->hwaccm.s.vmx.proc_ctls = val;
    293293
    … …  
    304304     * Set required bits to one and zero according to the MSR capabilities.
    305305     */
    306     val  = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
     306    val  = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
    307307#if HC_ARCH_BITS == 64
    308308    val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
    … …  
    310310    /* else Must be zero when AMD64 is not available. */
    311311#endif
    312     val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
     312    val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
    313313    /* Don't acknowledge external interrupts on VM-exit. */
    314314    rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
    … …  
    356356
    357357    /* Clear MSR controls. */
    358     if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
     358    if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
    359359    {
    360360        /* Optional */
    … …  
    377377    AssertRC(rc);
    378378
    379     if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
     379    if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
    380380    {
    381381        Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
    … …  
    978978     * Set required bits to one and zero according to the MSR capabilities.
    979979     */
    980     val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
     980    val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
    981981    /* 64 bits guest mode? */
    982982    if (pCtx->msrEFER & MSR_K6_EFER_LMA)
    … …  
    985985
    986986    /* Mask away the bits that the CPU doesn't support */
    987     val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
     987    val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
    988988    rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
    989989    AssertRC(rc);
    … …  
    10471047
    10481048    /* allowed zero */
    1049     if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
     1049    if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
    10501050        Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
    10511051
    10521052    /* allowed one */
    1053     if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
     1053    if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
    10541054        Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
    10551055
    … …  
    10591059
    10601060    /* allowed zero */
    1061     if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
     1061    if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
    10621062        Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
    10631063
    10641064    /* allowed one */
    1065     if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
     1065    if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
    10661066        Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
    10671067
    … …  
    10711071
    10721072    /* allowed zero */
    1073     if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
     1073    if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
    10741074        Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
    10751075
    10761076    /* allowed one */
    1077     if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
     1077    if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
    10781078        Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
    10791079
    … …  
    10831083
    10841084    /* allowed zero */
    1085     if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
     1085    if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
    10861086        Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
    10871087
    10881088    /* allowed one */
    1089     if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
     1089    if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
    10901090        Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
    10911091#endif
    … …  
    17951795            case 8:
    17961796                /* CR8 contains the APIC TPR */
    1797                 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
     1797                Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
    17981798                break;
    17991799
    … …  
    18161816
    18171817            /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
    1818             Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
     1818            Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
    18191819
    18201820            rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
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