Changeset 104652 in vbox for trunk/src/VBox/ValidationKit/bootsectors

Timestamp:

May 16, 2024 9:19:53 AM (7 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: doxygen and nits.

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (7 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -238 +238 @@
 
 
+/**
+ * Returns the name of an X86 exception given the vector.
+ *
+ * @returns Name of the exception.
+ * @param   uVector     The exception vector.
+ */
 static const char BS3_FAR *bs3CpuInstr4XcptName(uint8_t uVector)
 {
@@ -270 +276 @@
 
 
+/**
+ * Gets the names of floating-point exception flags that are set for a given MXCSR.
+ *
+ * @returns Names of floating-point exception flags that are set.
+ * @param   pszBuf  Where to store the floating-point exception flags.
+ * @param   cchBuf  The size of the buffer.
+ * @param   fMxCsr  The MXCSR value.
+ */
 static size_t bs3CpuInstr4GetXcptFlags(char BS3_FAR *pszBuf, size_t cchBuf, uint32_t fMxCsr)
 {
     if (!(fMxCsr & X86_MXCSR_XCPT_FLAGS))
         return Bs3StrPrintf(pszBuf, cchBuf, " None");
-    return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", fMxCsr & X86_MXCSR_IE ? " IE" : "",
-                                                        fMxCsr & X86_MXCSR_DE ? " DE" : "",
-                                                        fMxCsr & X86_MXCSR_ZE ? " ZE" : "",
-                                                        fMxCsr & X86_MXCSR_OE ? " OE" : "",
-                                                        fMxCsr & X86_MXCSR_UE ? " UE" : "",
-                                                        fMxCsr & X86_MXCSR_PE ? " PE" : "");
+    return Bs3StrPrintf(pszBuf, cchBuf, "%s%s%s%s%s%s", fMxCsr & X86_MXCSR_IE ? " IE" : "", fMxCsr & X86_MXCSR_DE ? " DE" : "",
+                                                        fMxCsr & X86_MXCSR_ZE ? " ZE" : "", fMxCsr & X86_MXCSR_OE ? " OE" : "",
+                                                        fMxCsr & X86_MXCSR_UE ? " UE" : "", fMxCsr & X86_MXCSR_PE ? " PE" : "");
 }
 
@@ -426 +437 @@
 
 
+/**
+ * Frees the extended CPU contexts allocated by bs3CpuInstrXAllocExtCtxs.
+ *
+ * @param   pExtCtx1        The first extended context.
+ * @param   pExtCtx2        The second extended context.
+ */
 static void bs3CpuInstrXFreeExtCtxs(PBS3EXTCTX pExtCtx1, PBS3EXTCTX BS3_FAR pExtCtx2)
 {
@@ -469 +486 @@
 
 
-
-/**
- * Configures the buffer with electrict fences in paged modes.
+/**
+ * Configures the buffer with electric fences in paged modes.
  *
  * @returns Adjusted buffer pointer.
@@ -571 +587 @@
 
 /*
- * Code to make testing the tests faster.  `bs3CpuInstrX_SkipIt()' randomly
+ * Code to make testing the tests faster. `bs3CpuInstrX_SkipIt()' randomly
  * skips a large fraction of the micro-tests.  It is sufficiently random
  * that over a large number of runs, all micro-tests will be hit.
@@ -726 +742 @@
 
 
+/**
+ * Worker for bs3CpuInstrX_WorkerTestType1.
+ */
 static uint16_t bs3CpuInstr4_WorkerTestType1_Inner(uint8_t bMode, PBS3CPUINSTR4_TEST1_CTX_T pTestCtx,
                                                    PCBS3CPUINSTRX_CONFIG_SAVED_T pSavedCfg)
@@ -934 +953 @@
     Bs3RegCtxSaveForMode(&Ctx, bMode, 1024);
     bs3CpuInstr4SetupSseAndAvx(&Ctx, pExtCtx);
-    //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n",  pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]);
 
     /*